1 //===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIInstrInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
16 
17 #include "AMDGPUMIRFormatter.h"
18 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
19 #include "SIRegisterInfo.h"
20 #include "Utils/AMDGPUBaseInfo.h"
21 #include "llvm/ADT/SetVector.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/CodeGen/TargetSchedule.h"
24 
25 #define GET_INSTRINFO_HEADER
26 #include "AMDGPUGenInstrInfo.inc"
27 
28 namespace llvm {
29 
30 class APInt;
31 class GCNSubtarget;
32 class LiveVariables;
33 class MachineDominatorTree;
34 class MachineRegisterInfo;
35 class RegScavenger;
36 class TargetRegisterClass;
37 class ScheduleHazardRecognizer;
38 
39 /// Mark the MMO of a uniform load if there are no potentially clobbering stores
40 /// on any path from the start of an entry function to this load.
41 static const MachineMemOperand::Flags MONoClobber =
42     MachineMemOperand::MOTargetFlag1;
43 
44 class SIInstrInfo final : public AMDGPUGenInstrInfo {
45 private:
46   const SIRegisterInfo RI;
47   const GCNSubtarget &ST;
48   TargetSchedModel SchedModel;
49   mutable std::unique_ptr<AMDGPUMIRFormatter> Formatter;
50 
51   // The inverse predicate should have the negative value.
52   enum BranchPredicate {
53     INVALID_BR = 0,
54     SCC_TRUE = 1,
55     SCC_FALSE = -1,
56     VCCNZ = 2,
57     VCCZ = -2,
58     EXECNZ = -3,
59     EXECZ = 3
60   };
61 
62   using SetVectorType = SmallSetVector<MachineInstr *, 32>;
63 
64   static unsigned getBranchOpcode(BranchPredicate Cond);
65   static BranchPredicate getBranchPredicate(unsigned Opcode);
66 
67 public:
68   unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
69                               MachineRegisterInfo &MRI,
70                               MachineOperand &SuperReg,
71                               const TargetRegisterClass *SuperRC,
72                               unsigned SubIdx,
73                               const TargetRegisterClass *SubRC) const;
74   MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
75                                          MachineRegisterInfo &MRI,
76                                          MachineOperand &SuperReg,
77                                          const TargetRegisterClass *SuperRC,
78                                          unsigned SubIdx,
79                                          const TargetRegisterClass *SubRC) const;
80 private:
81   void swapOperands(MachineInstr &Inst) const;
82 
83   std::pair<bool, MachineBasicBlock *>
84   moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
85                    MachineDominatorTree *MDT = nullptr) const;
86 
87   void lowerSelect(SetVectorType &Worklist, MachineInstr &Inst,
88                    MachineDominatorTree *MDT = nullptr) const;
89 
90   void lowerScalarAbs(SetVectorType &Worklist,
91                       MachineInstr &Inst) const;
92 
93   void lowerScalarXnor(SetVectorType &Worklist,
94                        MachineInstr &Inst) const;
95 
96   void splitScalarNotBinop(SetVectorType &Worklist,
97                            MachineInstr &Inst,
98                            unsigned Opcode) const;
99 
100   void splitScalarBinOpN2(SetVectorType &Worklist,
101                           MachineInstr &Inst,
102                           unsigned Opcode) const;
103 
104   void splitScalar64BitUnaryOp(SetVectorType &Worklist,
105                                MachineInstr &Inst, unsigned Opcode,
106                                bool Swap = false) const;
107 
108   void splitScalar64BitAddSub(SetVectorType &Worklist, MachineInstr &Inst,
109                               MachineDominatorTree *MDT = nullptr) const;
110 
111   void splitScalar64BitBinaryOp(SetVectorType &Worklist, MachineInstr &Inst,
112                                 unsigned Opcode,
113                                 MachineDominatorTree *MDT = nullptr) const;
114 
115   void splitScalar64BitXnor(SetVectorType &Worklist, MachineInstr &Inst,
116                                 MachineDominatorTree *MDT = nullptr) const;
117 
118   void splitScalar64BitBCNT(SetVectorType &Worklist,
119                             MachineInstr &Inst) const;
120   void splitScalar64BitBFE(SetVectorType &Worklist,
121                            MachineInstr &Inst) const;
122   void movePackToVALU(SetVectorType &Worklist,
123                       MachineRegisterInfo &MRI,
124                       MachineInstr &Inst) const;
125 
126   void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
127                                     SetVectorType &Worklist) const;
128 
129   void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
130                                     MachineInstr &SCCDefInst,
131                                     SetVectorType &Worklist,
132                                     Register NewCond = Register()) const;
133   void addSCCDefsToVALUWorklist(MachineOperand &Op,
134                                 SetVectorType &Worklist) const;
135 
136   const TargetRegisterClass *
137   getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
138 
139   bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
140                                     const MachineInstr &MIb) const;
141 
142   Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
143 
144 protected:
145   bool swapSourceModifiers(MachineInstr &MI,
146                            MachineOperand &Src0, unsigned Src0OpName,
147                            MachineOperand &Src1, unsigned Src1OpName) const;
148 
149   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
150                                        unsigned OpIdx0,
151                                        unsigned OpIdx1) const override;
152 
153 public:
154   enum TargetOperandFlags {
155     MO_MASK = 0xf,
156 
157     MO_NONE = 0,
158     // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
159     MO_GOTPCREL = 1,
160     // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
161     MO_GOTPCREL32 = 2,
162     MO_GOTPCREL32_LO = 2,
163     // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
164     MO_GOTPCREL32_HI = 3,
165     // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
166     MO_REL32 = 4,
167     MO_REL32_LO = 4,
168     // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
169     MO_REL32_HI = 5,
170 
171     MO_FAR_BRANCH_OFFSET = 6,
172 
173     MO_ABS32_LO = 8,
174     MO_ABS32_HI = 9,
175   };
176 
177   explicit SIInstrInfo(const GCNSubtarget &ST);
178 
179   const SIRegisterInfo &getRegisterInfo() const {
180     return RI;
181   }
182 
183   const GCNSubtarget &getSubtarget() const {
184     return ST;
185   }
186 
187   bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
188                                          AAResults *AA) const override;
189 
190   bool isIgnorableUse(const MachineOperand &MO) const override;
191 
192   bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
193                                int64_t &Offset1,
194                                int64_t &Offset2) const override;
195 
196   bool getMemOperandsWithOffsetWidth(
197       const MachineInstr &LdSt,
198       SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
199       bool &OffsetIsScalable, unsigned &Width,
200       const TargetRegisterInfo *TRI) const final;
201 
202   bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
203                            ArrayRef<const MachineOperand *> BaseOps2,
204                            unsigned NumLoads, unsigned NumBytes) const override;
205 
206   bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
207                                int64_t Offset1, unsigned NumLoads) const override;
208 
209   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
210                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
211                    bool KillSrc) const override;
212 
213   void materializeImmediate(MachineBasicBlock &MBB,
214                             MachineBasicBlock::iterator MI,
215                             const DebugLoc &DL,
216                             unsigned DestReg,
217                             int64_t Value) const;
218 
219   const TargetRegisterClass *getPreferredSelectRegClass(
220                                unsigned Size) const;
221 
222   Register insertNE(MachineBasicBlock *MBB,
223                     MachineBasicBlock::iterator I, const DebugLoc &DL,
224                     Register SrcReg, int Value) const;
225 
226   Register insertEQ(MachineBasicBlock *MBB,
227                     MachineBasicBlock::iterator I, const DebugLoc &DL,
228                     Register SrcReg, int Value)  const;
229 
230   void storeRegToStackSlot(MachineBasicBlock &MBB,
231                            MachineBasicBlock::iterator MI, Register SrcReg,
232                            bool isKill, int FrameIndex,
233                            const TargetRegisterClass *RC,
234                            const TargetRegisterInfo *TRI) const override;
235 
236   void loadRegFromStackSlot(MachineBasicBlock &MBB,
237                             MachineBasicBlock::iterator MI, Register DestReg,
238                             int FrameIndex, const TargetRegisterClass *RC,
239                             const TargetRegisterInfo *TRI) const override;
240 
241   bool expandPostRAPseudo(MachineInstr &MI) const override;
242 
243   // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
244   // instructions. Returns a pair of generated instructions.
245   // Can split either post-RA with physical registers or pre-RA with
246   // virtual registers. In latter case IR needs to be in SSA form and
247   // and a REG_SEQUENCE is produced to define original register.
248   std::pair<MachineInstr*, MachineInstr*>
249   expandMovDPP64(MachineInstr &MI) const;
250 
251   // Returns an opcode that can be used to move a value to a \p DstRC
252   // register.  If there is no hardware instruction that can store to \p
253   // DstRC, then AMDGPU::COPY is returned.
254   unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
255 
256   const MCInstrDesc &getIndirectRegWriteMovRelPseudo(unsigned VecSize,
257                                                      unsigned EltSize,
258                                                      bool IsSGPR) const;
259 
260   const MCInstrDesc &getIndirectGPRIDXPseudo(unsigned VecSize,
261                                              bool IsIndirectSrc) const;
262   LLVM_READONLY
263   int commuteOpcode(unsigned Opc) const;
264 
265   LLVM_READONLY
266   inline int commuteOpcode(const MachineInstr &MI) const {
267     return commuteOpcode(MI.getOpcode());
268   }
269 
270   bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
271                              unsigned &SrcOpIdx2) const override;
272 
273   bool findCommutedOpIndices(MCInstrDesc Desc, unsigned & SrcOpIdx0,
274    unsigned & SrcOpIdx1) const;
275 
276   bool isBranchOffsetInRange(unsigned BranchOpc,
277                              int64_t BrOffset) const override;
278 
279   MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
280 
281   void insertIndirectBranch(MachineBasicBlock &MBB,
282                             MachineBasicBlock &NewDestBB,
283                             MachineBasicBlock &RestoreBB, const DebugLoc &DL,
284                             int64_t BrOffset, RegScavenger *RS) const override;
285 
286   bool analyzeBranchImpl(MachineBasicBlock &MBB,
287                          MachineBasicBlock::iterator I,
288                          MachineBasicBlock *&TBB,
289                          MachineBasicBlock *&FBB,
290                          SmallVectorImpl<MachineOperand> &Cond,
291                          bool AllowModify) const;
292 
293   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
294                      MachineBasicBlock *&FBB,
295                      SmallVectorImpl<MachineOperand> &Cond,
296                      bool AllowModify = false) const override;
297 
298   unsigned removeBranch(MachineBasicBlock &MBB,
299                         int *BytesRemoved = nullptr) const override;
300 
301   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
302                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
303                         const DebugLoc &DL,
304                         int *BytesAdded = nullptr) const override;
305 
306   bool reverseBranchCondition(
307     SmallVectorImpl<MachineOperand> &Cond) const override;
308 
309   bool canInsertSelect(const MachineBasicBlock &MBB,
310                        ArrayRef<MachineOperand> Cond, Register DstReg,
311                        Register TrueReg, Register FalseReg, int &CondCycles,
312                        int &TrueCycles, int &FalseCycles) const override;
313 
314   void insertSelect(MachineBasicBlock &MBB,
315                     MachineBasicBlock::iterator I, const DebugLoc &DL,
316                     Register DstReg, ArrayRef<MachineOperand> Cond,
317                     Register TrueReg, Register FalseReg) const override;
318 
319   void insertVectorSelect(MachineBasicBlock &MBB,
320                           MachineBasicBlock::iterator I, const DebugLoc &DL,
321                           Register DstReg, ArrayRef<MachineOperand> Cond,
322                           Register TrueReg, Register FalseReg) const;
323 
324   bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
325                       Register &SrcReg2, int64_t &CmpMask,
326                       int64_t &CmpValue) const override;
327 
328   bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
329                             Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
330                             const MachineRegisterInfo *MRI) const override;
331 
332   bool
333   areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
334                                   const MachineInstr &MIb) const override;
335 
336   static bool isFoldableCopy(const MachineInstr &MI);
337 
338   void removeModOperands(MachineInstr &MI) const;
339 
340   bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
341                      MachineRegisterInfo *MRI) const final;
342 
343   unsigned getMachineCSELookAheadLimit() const override { return 500; }
344 
345   MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
346                                       LiveIntervals *LIS) const override;
347 
348   bool isSchedulingBoundary(const MachineInstr &MI,
349                             const MachineBasicBlock *MBB,
350                             const MachineFunction &MF) const override;
351 
352   static bool isSALU(const MachineInstr &MI) {
353     return MI.getDesc().TSFlags & SIInstrFlags::SALU;
354   }
355 
356   bool isSALU(uint16_t Opcode) const {
357     return get(Opcode).TSFlags & SIInstrFlags::SALU;
358   }
359 
360   static bool isVALU(const MachineInstr &MI) {
361     return MI.getDesc().TSFlags & SIInstrFlags::VALU;
362   }
363 
364   bool isVALU(uint16_t Opcode) const {
365     return get(Opcode).TSFlags & SIInstrFlags::VALU;
366   }
367 
368   static bool isVMEM(const MachineInstr &MI) {
369     return isMUBUF(MI) || isMTBUF(MI) || isMIMG(MI);
370   }
371 
372   bool isVMEM(uint16_t Opcode) const {
373     return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode);
374   }
375 
376   static bool isSOP1(const MachineInstr &MI) {
377     return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
378   }
379 
380   bool isSOP1(uint16_t Opcode) const {
381     return get(Opcode).TSFlags & SIInstrFlags::SOP1;
382   }
383 
384   static bool isSOP2(const MachineInstr &MI) {
385     return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
386   }
387 
388   bool isSOP2(uint16_t Opcode) const {
389     return get(Opcode).TSFlags & SIInstrFlags::SOP2;
390   }
391 
392   static bool isSOPC(const MachineInstr &MI) {
393     return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
394   }
395 
396   bool isSOPC(uint16_t Opcode) const {
397     return get(Opcode).TSFlags & SIInstrFlags::SOPC;
398   }
399 
400   static bool isSOPK(const MachineInstr &MI) {
401     return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
402   }
403 
404   bool isSOPK(uint16_t Opcode) const {
405     return get(Opcode).TSFlags & SIInstrFlags::SOPK;
406   }
407 
408   static bool isSOPP(const MachineInstr &MI) {
409     return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
410   }
411 
412   bool isSOPP(uint16_t Opcode) const {
413     return get(Opcode).TSFlags & SIInstrFlags::SOPP;
414   }
415 
416   static bool isPacked(const MachineInstr &MI) {
417     return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
418   }
419 
420   bool isPacked(uint16_t Opcode) const {
421     return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
422   }
423 
424   static bool isVOP1(const MachineInstr &MI) {
425     return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
426   }
427 
428   bool isVOP1(uint16_t Opcode) const {
429     return get(Opcode).TSFlags & SIInstrFlags::VOP1;
430   }
431 
432   static bool isVOP2(const MachineInstr &MI) {
433     return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
434   }
435 
436   bool isVOP2(uint16_t Opcode) const {
437     return get(Opcode).TSFlags & SIInstrFlags::VOP2;
438   }
439 
440   static bool isVOP3(const MachineInstr &MI) {
441     return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
442   }
443 
444   bool isVOP3(uint16_t Opcode) const {
445     return get(Opcode).TSFlags & SIInstrFlags::VOP3;
446   }
447 
448   static bool isSDWA(const MachineInstr &MI) {
449     return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
450   }
451 
452   bool isSDWA(uint16_t Opcode) const {
453     return get(Opcode).TSFlags & SIInstrFlags::SDWA;
454   }
455 
456   static bool isVOPC(const MachineInstr &MI) {
457     return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
458   }
459 
460   bool isVOPC(uint16_t Opcode) const {
461     return get(Opcode).TSFlags & SIInstrFlags::VOPC;
462   }
463 
464   static bool isMUBUF(const MachineInstr &MI) {
465     return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
466   }
467 
468   bool isMUBUF(uint16_t Opcode) const {
469     return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
470   }
471 
472   static bool isMTBUF(const MachineInstr &MI) {
473     return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
474   }
475 
476   bool isMTBUF(uint16_t Opcode) const {
477     return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
478   }
479 
480   static bool isSMRD(const MachineInstr &MI) {
481     return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
482   }
483 
484   bool isSMRD(uint16_t Opcode) const {
485     return get(Opcode).TSFlags & SIInstrFlags::SMRD;
486   }
487 
488   bool isBufferSMRD(const MachineInstr &MI) const;
489 
490   static bool isDS(const MachineInstr &MI) {
491     return MI.getDesc().TSFlags & SIInstrFlags::DS;
492   }
493 
494   bool isDS(uint16_t Opcode) const {
495     return get(Opcode).TSFlags & SIInstrFlags::DS;
496   }
497 
498   bool isAlwaysGDS(uint16_t Opcode) const;
499 
500   static bool isMIMG(const MachineInstr &MI) {
501     return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
502   }
503 
504   bool isMIMG(uint16_t Opcode) const {
505     return get(Opcode).TSFlags & SIInstrFlags::MIMG;
506   }
507 
508   static bool isGather4(const MachineInstr &MI) {
509     return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
510   }
511 
512   bool isGather4(uint16_t Opcode) const {
513     return get(Opcode).TSFlags & SIInstrFlags::Gather4;
514   }
515 
516   static bool isFLAT(const MachineInstr &MI) {
517     return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
518   }
519 
520   // Is a FLAT encoded instruction which accesses a specific segment,
521   // i.e. global_* or scratch_*.
522   static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
523     auto Flags = MI.getDesc().TSFlags;
524     return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch);
525   }
526 
527   bool isSegmentSpecificFLAT(uint16_t Opcode) const {
528     auto Flags = get(Opcode).TSFlags;
529     return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch);
530   }
531 
532   static bool isFLATGlobal(const MachineInstr &MI) {
533     return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal;
534   }
535 
536   bool isFLATGlobal(uint16_t Opcode) const {
537     return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal;
538   }
539 
540   static bool isFLATScratch(const MachineInstr &MI) {
541     return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch;
542   }
543 
544   bool isFLATScratch(uint16_t Opcode) const {
545     return get(Opcode).TSFlags & SIInstrFlags::FlatScratch;
546   }
547 
548   // Any FLAT encoded instruction, including global_* and scratch_*.
549   bool isFLAT(uint16_t Opcode) const {
550     return get(Opcode).TSFlags & SIInstrFlags::FLAT;
551   }
552 
553   static bool isEXP(const MachineInstr &MI) {
554     return MI.getDesc().TSFlags & SIInstrFlags::EXP;
555   }
556 
557   bool isEXP(uint16_t Opcode) const {
558     return get(Opcode).TSFlags & SIInstrFlags::EXP;
559   }
560 
561   static bool isAtomicNoRet(const MachineInstr &MI) {
562     return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet;
563   }
564 
565   bool isAtomicNoRet(uint16_t Opcode) const {
566     return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet;
567   }
568 
569   static bool isAtomicRet(const MachineInstr &MI) {
570     return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet;
571   }
572 
573   bool isAtomicRet(uint16_t Opcode) const {
574     return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet;
575   }
576 
577   static bool isAtomic(const MachineInstr &MI) {
578     return MI.getDesc().TSFlags & (SIInstrFlags::IsAtomicRet |
579                                    SIInstrFlags::IsAtomicNoRet);
580   }
581 
582   bool isAtomic(uint16_t Opcode) const {
583     return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet |
584                                   SIInstrFlags::IsAtomicNoRet);
585   }
586 
587   static bool isWQM(const MachineInstr &MI) {
588     return MI.getDesc().TSFlags & SIInstrFlags::WQM;
589   }
590 
591   bool isWQM(uint16_t Opcode) const {
592     return get(Opcode).TSFlags & SIInstrFlags::WQM;
593   }
594 
595   static bool isDisableWQM(const MachineInstr &MI) {
596     return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
597   }
598 
599   bool isDisableWQM(uint16_t Opcode) const {
600     return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
601   }
602 
603   static bool isVGPRSpill(const MachineInstr &MI) {
604     return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;
605   }
606 
607   bool isVGPRSpill(uint16_t Opcode) const {
608     return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
609   }
610 
611   static bool isSGPRSpill(const MachineInstr &MI) {
612     return MI.getDesc().TSFlags & SIInstrFlags::SGPRSpill;
613   }
614 
615   bool isSGPRSpill(uint16_t Opcode) const {
616     return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
617   }
618 
619   static bool isDPP(const MachineInstr &MI) {
620     return MI.getDesc().TSFlags & SIInstrFlags::DPP;
621   }
622 
623   bool isDPP(uint16_t Opcode) const {
624     return get(Opcode).TSFlags & SIInstrFlags::DPP;
625   }
626 
627   static bool isTRANS(const MachineInstr &MI) {
628     return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
629   }
630 
631   bool isTRANS(uint16_t Opcode) const {
632     return get(Opcode).TSFlags & SIInstrFlags::TRANS;
633   }
634 
635   static bool isVOP3P(const MachineInstr &MI) {
636     return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
637   }
638 
639   bool isVOP3P(uint16_t Opcode) const {
640     return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
641   }
642 
643   static bool isVINTRP(const MachineInstr &MI) {
644     return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
645   }
646 
647   bool isVINTRP(uint16_t Opcode) const {
648     return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
649   }
650 
651   static bool isMAI(const MachineInstr &MI) {
652     return MI.getDesc().TSFlags & SIInstrFlags::IsMAI;
653   }
654 
655   bool isMAI(uint16_t Opcode) const {
656     return get(Opcode).TSFlags & SIInstrFlags::IsMAI;
657   }
658 
659   static bool isMFMA(const MachineInstr &MI) {
660     return isMAI(MI) && MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
661            MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64;
662   }
663 
664   static bool isDOT(const MachineInstr &MI) {
665     return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
666   }
667 
668   bool isDOT(uint16_t Opcode) const {
669     return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
670   }
671 
672   static bool isLDSDIR(const MachineInstr &MI) {
673     return MI.getDesc().TSFlags & SIInstrFlags::LDSDIR;
674   }
675 
676   bool isLDSDIR(uint16_t Opcode) const {
677     return get(Opcode).TSFlags & SIInstrFlags::LDSDIR;
678   }
679 
680   static bool isVINTERP(const MachineInstr &MI) {
681     return MI.getDesc().TSFlags & SIInstrFlags::VINTERP;
682   }
683 
684   bool isVINTERP(uint16_t Opcode) const {
685     return get(Opcode).TSFlags & SIInstrFlags::VINTERP;
686   }
687 
688   static bool isScalarUnit(const MachineInstr &MI) {
689     return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
690   }
691 
692   static bool usesVM_CNT(const MachineInstr &MI) {
693     return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
694   }
695 
696   static bool usesLGKM_CNT(const MachineInstr &MI) {
697     return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
698   }
699 
700   static bool sopkIsZext(const MachineInstr &MI) {
701     return MI.getDesc().TSFlags & SIInstrFlags::SOPK_ZEXT;
702   }
703 
704   bool sopkIsZext(uint16_t Opcode) const {
705     return get(Opcode).TSFlags & SIInstrFlags::SOPK_ZEXT;
706   }
707 
708   /// \returns true if this is an s_store_dword* instruction. This is more
709   /// specific than than isSMEM && mayStore.
710   static bool isScalarStore(const MachineInstr &MI) {
711     return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
712   }
713 
714   bool isScalarStore(uint16_t Opcode) const {
715     return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
716   }
717 
718   static bool isFixedSize(const MachineInstr &MI) {
719     return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
720   }
721 
722   bool isFixedSize(uint16_t Opcode) const {
723     return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
724   }
725 
726   static bool hasFPClamp(const MachineInstr &MI) {
727     return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
728   }
729 
730   bool hasFPClamp(uint16_t Opcode) const {
731     return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
732   }
733 
734   static bool hasIntClamp(const MachineInstr &MI) {
735     return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
736   }
737 
738   uint64_t getClampMask(const MachineInstr &MI) const {
739     const uint64_t ClampFlags = SIInstrFlags::FPClamp |
740                                 SIInstrFlags::IntClamp |
741                                 SIInstrFlags::ClampLo |
742                                 SIInstrFlags::ClampHi;
743       return MI.getDesc().TSFlags & ClampFlags;
744   }
745 
746   static bool usesFPDPRounding(const MachineInstr &MI) {
747     return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
748   }
749 
750   bool usesFPDPRounding(uint16_t Opcode) const {
751     return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
752   }
753 
754   static bool isFPAtomic(const MachineInstr &MI) {
755     return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
756   }
757 
758   bool isFPAtomic(uint16_t Opcode) const {
759     return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
760   }
761 
762   bool isVGPRCopy(const MachineInstr &MI) const {
763     assert(MI.isCopy());
764     Register Dest = MI.getOperand(0).getReg();
765     const MachineFunction &MF = *MI.getParent()->getParent();
766     const MachineRegisterInfo &MRI = MF.getRegInfo();
767     return !RI.isSGPRReg(MRI, Dest);
768   }
769 
770   bool hasVGPRUses(const MachineInstr &MI) const {
771     const MachineFunction &MF = *MI.getParent()->getParent();
772     const MachineRegisterInfo &MRI = MF.getRegInfo();
773     return llvm::any_of(MI.explicit_uses(),
774                         [&MRI, this](const MachineOperand &MO) {
775       return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
776   }
777 
778   /// Return true if the instruction modifies the mode register.q
779   static bool modifiesModeRegister(const MachineInstr &MI);
780 
781   /// Whether we must prevent this instruction from executing with EXEC = 0.
782   bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const;
783 
784   /// Returns true if the instruction could potentially depend on the value of
785   /// exec. If false, exec dependencies may safely be ignored.
786   bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
787 
788   bool isInlineConstant(const APInt &Imm) const;
789 
790   bool isInlineConstant(const APFloat &Imm) const {
791     return isInlineConstant(Imm.bitcastToAPInt());
792   }
793 
794   bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
795 
796   bool isInlineConstant(const MachineOperand &MO,
797                         const MCOperandInfo &OpInfo) const {
798     return isInlineConstant(MO, OpInfo.OperandType);
799   }
800 
801   /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
802   /// be an inline immediate.
803   bool isInlineConstant(const MachineInstr &MI,
804                         const MachineOperand &UseMO,
805                         const MachineOperand &DefMO) const {
806     assert(UseMO.getParent() == &MI);
807     int OpIdx = MI.getOperandNo(&UseMO);
808     if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) {
809       return false;
810     }
811 
812     return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]);
813   }
814 
815   /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
816   /// immediate.
817   bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
818     const MachineOperand &MO = MI.getOperand(OpIdx);
819     return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
820   }
821 
822   bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
823                         const MachineOperand &MO) const {
824     if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands)
825       return false;
826 
827     if (MI.isCopy()) {
828       unsigned Size = getOpSize(MI, OpIdx);
829       assert(Size == 8 || Size == 4);
830 
831       uint8_t OpType = (Size == 8) ?
832         AMDGPU::OPERAND_REG_IMM_INT64 : AMDGPU::OPERAND_REG_IMM_INT32;
833       return isInlineConstant(MO, OpType);
834     }
835 
836     return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
837   }
838 
839   bool isInlineConstant(const MachineOperand &MO) const {
840     const MachineInstr *Parent = MO.getParent();
841     return isInlineConstant(*Parent, Parent->getOperandNo(&MO));
842   }
843 
844   bool isLiteralConstant(const MachineOperand &MO,
845                          const MCOperandInfo &OpInfo) const {
846     return MO.isImm() && !isInlineConstant(MO, OpInfo.OperandType);
847   }
848 
849   bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const {
850     const MachineOperand &MO = MI.getOperand(OpIdx);
851     return MO.isImm() && !isInlineConstant(MI, OpIdx);
852   }
853 
854   // Returns true if this operand could potentially require a 32-bit literal
855   // operand, but not necessarily. A FrameIndex for example could resolve to an
856   // inline immediate value that will not require an additional 4-bytes; this
857   // assumes that it will.
858   bool isLiteralConstantLike(const MachineOperand &MO,
859                              const MCOperandInfo &OpInfo) const;
860 
861   bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
862                          const MachineOperand &MO) const;
863 
864   /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
865   /// This function will return false if you pass it a 32-bit instruction.
866   bool hasVALU32BitEncoding(unsigned Opcode) const;
867 
868   /// Returns true if this operand uses the constant bus.
869   bool usesConstantBus(const MachineRegisterInfo &MRI,
870                        const MachineOperand &MO,
871                        const MCOperandInfo &OpInfo) const;
872 
873   /// Return true if this instruction has any modifiers.
874   ///  e.g. src[012]_mod, omod, clamp.
875   bool hasModifiers(unsigned Opcode) const;
876 
877   bool hasModifiersSet(const MachineInstr &MI,
878                        unsigned OpName) const;
879   bool hasAnyModifiersSet(const MachineInstr &MI) const;
880 
881   bool canShrink(const MachineInstr &MI,
882                  const MachineRegisterInfo &MRI) const;
883 
884   MachineInstr *buildShrunkInst(MachineInstr &MI,
885                                 unsigned NewOpcode) const;
886 
887   bool verifyInstruction(const MachineInstr &MI,
888                          StringRef &ErrInfo) const override;
889 
890   unsigned getVALUOp(const MachineInstr &MI) const;
891 
892   /// Return the correct register class for \p OpNo.  For target-specific
893   /// instructions, this will return the register class that has been defined
894   /// in tablegen.  For generic instructions, like REG_SEQUENCE it will return
895   /// the register class of its machine operand.
896   /// to infer the correct register class base on the other operands.
897   const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
898                                            unsigned OpNo) const;
899 
900   /// Return the size in bytes of the operand OpNo on the given
901   // instruction opcode.
902   unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
903     const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
904 
905     if (OpInfo.RegClass == -1) {
906       // If this is an immediate operand, this must be a 32-bit literal.
907       assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
908       return 4;
909     }
910 
911     return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
912   }
913 
914   /// This form should usually be preferred since it handles operands
915   /// with unknown register classes.
916   unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
917     const MachineOperand &MO = MI.getOperand(OpNo);
918     if (MO.isReg()) {
919       if (unsigned SubReg = MO.getSubReg()) {
920         return RI.getSubRegIdxSize(SubReg) / 8;
921       }
922     }
923     return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
924   }
925 
926   /// Legalize the \p OpIndex operand of this instruction by inserting
927   /// a MOV.  For example:
928   /// ADD_I32_e32 VGPR0, 15
929   /// to
930   /// MOV VGPR1, 15
931   /// ADD_I32_e32 VGPR0, VGPR1
932   ///
933   /// If the operand being legalized is a register, then a COPY will be used
934   /// instead of MOV.
935   void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
936 
937   /// Check if \p MO is a legal operand if it was the \p OpIdx Operand
938   /// for \p MI.
939   bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
940                       const MachineOperand *MO = nullptr) const;
941 
942   /// Check if \p MO would be a valid operand for the given operand
943   /// definition \p OpInfo. Note this does not attempt to validate constant bus
944   /// restrictions (e.g. literal constant usage).
945   bool isLegalVSrcOperand(const MachineRegisterInfo &MRI,
946                           const MCOperandInfo &OpInfo,
947                           const MachineOperand &MO) const;
948 
949   /// Check if \p MO (a register operand) is a legal register for the
950   /// given operand description.
951   bool isLegalRegOperand(const MachineRegisterInfo &MRI,
952                          const MCOperandInfo &OpInfo,
953                          const MachineOperand &MO) const;
954 
955   /// Legalize operands in \p MI by either commuting it or inserting a
956   /// copy of src1.
957   void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const;
958 
959   /// Fix operands in \p MI to satisfy constant bus requirements.
960   void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const;
961 
962   /// Copy a value from a VGPR (\p SrcReg) to SGPR.  This function can only
963   /// be used when it is know that the value in SrcReg is same across all
964   /// threads in the wave.
965   /// \returns The SGPR register that \p SrcReg was copied to.
966   Register readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI,
967                               MachineRegisterInfo &MRI) const;
968 
969   void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const;
970   void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const;
971 
972   void legalizeGenericOperand(MachineBasicBlock &InsertMBB,
973                               MachineBasicBlock::iterator I,
974                               const TargetRegisterClass *DstRC,
975                               MachineOperand &Op, MachineRegisterInfo &MRI,
976                               const DebugLoc &DL) const;
977 
978   /// Legalize all operands in this instruction.  This function may create new
979   /// instructions and control-flow around \p MI.  If present, \p MDT is
980   /// updated.
981   /// \returns A new basic block that contains \p MI if new blocks were created.
982   MachineBasicBlock *
983   legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
984 
985   /// Change SADDR form of a FLAT \p Inst to its VADDR form if saddr operand
986   /// was moved to VGPR. \returns true if succeeded.
987   bool moveFlatAddrToVGPR(MachineInstr &Inst) const;
988 
989   /// Replace this instruction's opcode with the equivalent VALU
990   /// opcode.  This function will also move the users of \p MI to the
991   /// VALU if necessary. If present, \p MDT is updated.
992   MachineBasicBlock *moveToVALU(MachineInstr &MI,
993                                 MachineDominatorTree *MDT = nullptr) const;
994 
995   void insertNoop(MachineBasicBlock &MBB,
996                   MachineBasicBlock::iterator MI) const override;
997 
998   void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
999                    unsigned Quantity) const override;
1000 
1001   void insertReturn(MachineBasicBlock &MBB) const;
1002   /// Return the number of wait states that result from executing this
1003   /// instruction.
1004   static unsigned getNumWaitStates(const MachineInstr &MI);
1005 
1006   /// Returns the operand named \p Op.  If \p MI does not have an
1007   /// operand named \c Op, this function returns nullptr.
1008   LLVM_READONLY
1009   MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
1010 
1011   LLVM_READONLY
1012   const MachineOperand *getNamedOperand(const MachineInstr &MI,
1013                                         unsigned OpName) const {
1014     return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
1015   }
1016 
1017   /// Get required immediate operand
1018   int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
1019     int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
1020     return MI.getOperand(Idx).getImm();
1021   }
1022 
1023   uint64_t getDefaultRsrcDataFormat() const;
1024   uint64_t getScratchRsrcWords23() const;
1025 
1026   bool isLowLatencyInstruction(const MachineInstr &MI) const;
1027   bool isHighLatencyDef(int Opc) const override;
1028 
1029   /// Return the descriptor of the target-specific machine instruction
1030   /// that corresponds to the specified pseudo or native opcode.
1031   const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
1032     return get(pseudoToMCOpcode(Opcode));
1033   }
1034 
1035   unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1036   unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1037 
1038   unsigned isLoadFromStackSlot(const MachineInstr &MI,
1039                                int &FrameIndex) const override;
1040   unsigned isStoreToStackSlot(const MachineInstr &MI,
1041                               int &FrameIndex) const override;
1042 
1043   unsigned getInstBundleSize(const MachineInstr &MI) const;
1044   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
1045 
1046   bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
1047 
1048   bool isNonUniformBranchInstr(MachineInstr &Instr) const;
1049 
1050   void convertNonUniformIfRegion(MachineBasicBlock *IfEntry,
1051                                  MachineBasicBlock *IfEnd) const;
1052 
1053   void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry,
1054                                    MachineBasicBlock *LoopEnd) const;
1055 
1056   std::pair<unsigned, unsigned>
1057   decomposeMachineOperandsTargetFlags(unsigned TF) const override;
1058 
1059   ArrayRef<std::pair<int, const char *>>
1060   getSerializableTargetIndices() const override;
1061 
1062   ArrayRef<std::pair<unsigned, const char *>>
1063   getSerializableDirectMachineOperandTargetFlags() const override;
1064 
1065   ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
1066   getSerializableMachineMemOperandTargetFlags() const override;
1067 
1068   ScheduleHazardRecognizer *
1069   CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
1070                                  const ScheduleDAG *DAG) const override;
1071 
1072   ScheduleHazardRecognizer *
1073   CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
1074 
1075   ScheduleHazardRecognizer *
1076   CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
1077                                  const ScheduleDAGMI *DAG) const override;
1078 
1079   bool isBasicBlockPrologue(const MachineInstr &MI) const override;
1080 
1081   MachineInstr *createPHIDestinationCopy(MachineBasicBlock &MBB,
1082                                          MachineBasicBlock::iterator InsPt,
1083                                          const DebugLoc &DL, Register Src,
1084                                          Register Dst) const override;
1085 
1086   MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB,
1087                                     MachineBasicBlock::iterator InsPt,
1088                                     const DebugLoc &DL, Register Src,
1089                                     unsigned SrcSubReg,
1090                                     Register Dst) const override;
1091 
1092   bool isWave32() const;
1093 
1094   /// Return a partially built integer add instruction without carry.
1095   /// Caller must add source operands.
1096   /// For pre-GFX9 it will generate unused carry destination operand.
1097   /// TODO: After GFX9 it should return a no-carry operation.
1098   MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
1099                                     MachineBasicBlock::iterator I,
1100                                     const DebugLoc &DL,
1101                                     Register DestReg) const;
1102 
1103   MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
1104                                     MachineBasicBlock::iterator I,
1105                                     const DebugLoc &DL,
1106                                     Register DestReg,
1107                                     RegScavenger &RS) const;
1108 
1109   static bool isKillTerminator(unsigned Opcode);
1110   const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
1111 
1112   static bool isLegalMUBUFImmOffset(unsigned Imm) {
1113     return isUInt<12>(Imm);
1114   }
1115 
1116   /// Returns if \p Offset is legal for the subtarget as the offset to a FLAT
1117   /// encoded instruction. If \p Signed, this is for an instruction that
1118   /// interprets the offset as signed.
1119   bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
1120                          uint64_t FlatVariant) const;
1121 
1122   /// Split \p COffsetVal into {immediate offset field, remainder offset}
1123   /// values.
1124   std::pair<int64_t, int64_t> splitFlatOffset(int64_t COffsetVal,
1125                                               unsigned AddrSpace,
1126                                               uint64_t FlatVariant) const;
1127 
1128   /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
1129   /// Return -1 if the target-specific opcode for the pseudo instruction does
1130   /// not exist. If Opcode is not a pseudo instruction, this is identity.
1131   int pseudoToMCOpcode(int Opcode) const;
1132 
1133   /// \brief Check if this instruction should only be used by assembler.
1134   /// Return true if this opcode should not be used by codegen.
1135   bool isAsmOnlyOpcode(int MCOp) const;
1136 
1137   const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
1138                                          const TargetRegisterInfo *TRI,
1139                                          const MachineFunction &MF)
1140     const override;
1141 
1142   void fixImplicitOperands(MachineInstr &MI) const;
1143 
1144   MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
1145                                       ArrayRef<unsigned> Ops,
1146                                       MachineBasicBlock::iterator InsertPt,
1147                                       int FrameIndex,
1148                                       LiveIntervals *LIS = nullptr,
1149                                       VirtRegMap *VRM = nullptr) const override;
1150 
1151   unsigned getInstrLatency(const InstrItineraryData *ItinData,
1152                            const MachineInstr &MI,
1153                            unsigned *PredCost = nullptr) const override;
1154 
1155   const MIRFormatter *getMIRFormatter() const override {
1156     if (!Formatter.get())
1157       Formatter = std::make_unique<AMDGPUMIRFormatter>();
1158     return Formatter.get();
1159   }
1160 
1161   static unsigned getDSShaderTypeValue(const MachineFunction &MF);
1162 
1163   const TargetSchedModel &getSchedModel() const { return SchedModel; }
1164 
1165   // Enforce operand's \p OpName even alignment if required by target.
1166   // This is used if an operand is a 32 bit register but needs to be aligned
1167   // regardless.
1168   void enforceOperandRCAlignment(MachineInstr &MI, unsigned OpName) const;
1169 };
1170 
1171 /// \brief Returns true if a reg:subreg pair P has a TRC class
1172 inline bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P,
1173                          const TargetRegisterClass &TRC,
1174                          MachineRegisterInfo &MRI) {
1175   auto *RC = MRI.getRegClass(P.Reg);
1176   if (!P.SubReg)
1177     return RC == &TRC;
1178   auto *TRI = MRI.getTargetRegisterInfo();
1179   return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg);
1180 }
1181 
1182 /// \brief Create RegSubRegPair from a register MachineOperand
1183 inline
1184 TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O) {
1185   assert(O.isReg());
1186   return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
1187 }
1188 
1189 /// \brief Return the SubReg component from REG_SEQUENCE
1190 TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI,
1191                                                     unsigned SubReg);
1192 
1193 /// \brief Return the defining instruction for a given reg:subreg pair
1194 /// skipping copy like instructions and subreg-manipulation pseudos.
1195 /// Following another subreg of a reg:subreg isn't supported.
1196 MachineInstr *getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P,
1197                                MachineRegisterInfo &MRI);
1198 
1199 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1200 /// DefMI and the use at \p UseMI. Should be run on SSA. Currently does not
1201 /// attempt to track between blocks.
1202 bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
1203                                 Register VReg,
1204                                 const MachineInstr &DefMI,
1205                                 const MachineInstr &UseMI);
1206 
1207 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1208 /// DefMI and all its uses. Should be run on SSA. Currently does not attempt to
1209 /// track between blocks.
1210 bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
1211                                    Register VReg,
1212                                    const MachineInstr &DefMI);
1213 
1214 namespace AMDGPU {
1215 
1216   LLVM_READONLY
1217   int getVOPe64(uint16_t Opcode);
1218 
1219   LLVM_READONLY
1220   int getVOPe32(uint16_t Opcode);
1221 
1222   LLVM_READONLY
1223   int getSDWAOp(uint16_t Opcode);
1224 
1225   LLVM_READONLY
1226   int getDPPOp32(uint16_t Opcode);
1227 
1228   LLVM_READONLY
1229   int getBasicFromSDWAOp(uint16_t Opcode);
1230 
1231   LLVM_READONLY
1232   int getCommuteRev(uint16_t Opcode);
1233 
1234   LLVM_READONLY
1235   int getCommuteOrig(uint16_t Opcode);
1236 
1237   LLVM_READONLY
1238   int getAddr64Inst(uint16_t Opcode);
1239 
1240   /// Check if \p Opcode is an Addr64 opcode.
1241   ///
1242   /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
1243   LLVM_READONLY
1244   int getIfAddr64Inst(uint16_t Opcode);
1245 
1246   LLVM_READONLY
1247   int getAtomicNoRetOp(uint16_t Opcode);
1248 
1249   LLVM_READONLY
1250   int getSOPKOp(uint16_t Opcode);
1251 
1252   /// \returns SADDR form of a FLAT Global instruction given an \p Opcode
1253   /// of a VADDR form.
1254   LLVM_READONLY
1255   int getGlobalSaddrOp(uint16_t Opcode);
1256 
1257   /// \returns VADDR form of a FLAT Global instruction given an \p Opcode
1258   /// of a SADDR form.
1259   LLVM_READONLY
1260   int getGlobalVaddrOp(uint16_t Opcode);
1261 
1262   LLVM_READONLY
1263   int getVCMPXNoSDstOp(uint16_t Opcode);
1264 
1265   /// \returns ST form with only immediate offset of a FLAT Scratch instruction
1266   /// given an \p Opcode of an SS (SADDR) form.
1267   LLVM_READONLY
1268   int getFlatScratchInstSTfromSS(uint16_t Opcode);
1269 
1270   /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1271   /// of an SVS (SADDR + VADDR) form.
1272   LLVM_READONLY
1273   int getFlatScratchInstSVfromSVS(uint16_t Opcode);
1274 
1275   /// \returns SS (SADDR) form of a FLAT Scratch instruction given an \p Opcode
1276   /// of an SV (VADDR) form.
1277   LLVM_READONLY
1278   int getFlatScratchInstSSfromSV(uint16_t Opcode);
1279 
1280   /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1281   /// of an SS (SADDR) form.
1282   LLVM_READONLY
1283   int getFlatScratchInstSVfromSS(uint16_t Opcode);
1284 
1285   /// \returns earlyclobber version of a MAC MFMA is exists.
1286   LLVM_READONLY
1287   int getMFMAEarlyClobberOp(uint16_t Opcode);
1288 
1289   /// \returns v_cmpx version of a v_cmp instruction.
1290   LLVM_READONLY
1291   int getVCMPXOpFromVCMP(uint16_t Opcode);
1292 
1293   const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
1294   const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19);
1295   const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);
1296   const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
1297 
1298 } // end namespace AMDGPU
1299 
1300 namespace SI {
1301 namespace KernelInputOffsets {
1302 
1303 /// Offsets in bytes from the start of the input buffer
1304 enum Offsets {
1305   NGROUPS_X = 0,
1306   NGROUPS_Y = 4,
1307   NGROUPS_Z = 8,
1308   GLOBAL_SIZE_X = 12,
1309   GLOBAL_SIZE_Y = 16,
1310   GLOBAL_SIZE_Z = 20,
1311   LOCAL_SIZE_X = 24,
1312   LOCAL_SIZE_Y = 28,
1313   LOCAL_SIZE_Z = 32
1314 };
1315 
1316 } // end namespace KernelInputOffsets
1317 } // end namespace SI
1318 
1319 } // end namespace llvm
1320 
1321 #endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
1322