1 //===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIInstrInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
16 
17 #include "AMDGPUInstrInfo.h"
18 #include "SIDefines.h"
19 #include "SIRegisterInfo.h"
20 #include "Utils/AMDGPUBaseInfo.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/SetVector.h"
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineOperand.h"
28 #include "llvm/CodeGen/TargetSchedule.h"
29 #include "llvm/MC/MCInstrDesc.h"
30 #include "llvm/Support/Compiler.h"
31 #include <cassert>
32 #include <cstdint>
33 
34 #define GET_INSTRINFO_HEADER
35 #include "AMDGPUGenInstrInfo.inc"
36 
37 namespace llvm {
38 
39 class APInt;
40 class MachineDominatorTree;
41 class MachineRegisterInfo;
42 class RegScavenger;
43 class GCNSubtarget;
44 class TargetRegisterClass;
45 
46 class SIInstrInfo final : public AMDGPUGenInstrInfo {
47 private:
48   const SIRegisterInfo RI;
49   const GCNSubtarget &ST;
50   TargetSchedModel SchedModel;
51 
52   // The inverse predicate should have the negative value.
53   enum BranchPredicate {
54     INVALID_BR = 0,
55     SCC_TRUE = 1,
56     SCC_FALSE = -1,
57     VCCNZ = 2,
58     VCCZ = -2,
59     EXECNZ = -3,
60     EXECZ = 3
61   };
62 
63   using SetVectorType = SmallSetVector<MachineInstr *, 32>;
64 
65   static unsigned getBranchOpcode(BranchPredicate Cond);
66   static BranchPredicate getBranchPredicate(unsigned Opcode);
67 
68 public:
69   unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
70                               MachineRegisterInfo &MRI,
71                               MachineOperand &SuperReg,
72                               const TargetRegisterClass *SuperRC,
73                               unsigned SubIdx,
74                               const TargetRegisterClass *SubRC) const;
75   MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
76                                          MachineRegisterInfo &MRI,
77                                          MachineOperand &SuperReg,
78                                          const TargetRegisterClass *SuperRC,
79                                          unsigned SubIdx,
80                                          const TargetRegisterClass *SubRC) const;
81 private:
82   void swapOperands(MachineInstr &Inst) const;
83 
84   bool moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
85                         MachineDominatorTree *MDT = nullptr) const;
86 
87   void lowerScalarAbs(SetVectorType &Worklist,
88                       MachineInstr &Inst) const;
89 
90   void lowerScalarXnor(SetVectorType &Worklist,
91                        MachineInstr &Inst) const;
92 
93   void splitScalarNotBinop(SetVectorType &Worklist,
94                            MachineInstr &Inst,
95                            unsigned Opcode) const;
96 
97   void splitScalarBinOpN2(SetVectorType &Worklist,
98                           MachineInstr &Inst,
99                           unsigned Opcode) const;
100 
101   void splitScalar64BitUnaryOp(SetVectorType &Worklist,
102                                MachineInstr &Inst, unsigned Opcode) const;
103 
104   void splitScalar64BitAddSub(SetVectorType &Worklist, MachineInstr &Inst,
105                               MachineDominatorTree *MDT = nullptr) const;
106 
107   void splitScalar64BitBinaryOp(SetVectorType &Worklist, MachineInstr &Inst,
108                                 unsigned Opcode,
109                                 MachineDominatorTree *MDT = nullptr) const;
110 
111   void splitScalar64BitXnor(SetVectorType &Worklist, MachineInstr &Inst,
112                                 MachineDominatorTree *MDT = nullptr) const;
113 
114   void splitScalar64BitBCNT(SetVectorType &Worklist,
115                             MachineInstr &Inst) const;
116   void splitScalar64BitBFE(SetVectorType &Worklist,
117                            MachineInstr &Inst) const;
118   void movePackToVALU(SetVectorType &Worklist,
119                       MachineRegisterInfo &MRI,
120                       MachineInstr &Inst) const;
121 
122   void addUsersToMoveToVALUWorklist(unsigned Reg, MachineRegisterInfo &MRI,
123                                     SetVectorType &Worklist) const;
124 
125   void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
126                                     MachineInstr &SCCDefInst,
127                                     SetVectorType &Worklist) const;
128 
129   const TargetRegisterClass *
130   getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
131 
132   bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
133                                     const MachineInstr &MIb) const;
134 
135   unsigned findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
136 
137 protected:
138   bool swapSourceModifiers(MachineInstr &MI,
139                            MachineOperand &Src0, unsigned Src0OpName,
140                            MachineOperand &Src1, unsigned Src1OpName) const;
141 
142   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
143                                        unsigned OpIdx0,
144                                        unsigned OpIdx1) const override;
145 
146 public:
147   enum TargetOperandFlags {
148     MO_MASK = 0xf,
149 
150     MO_NONE = 0,
151     // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
152     MO_GOTPCREL = 1,
153     // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
154     MO_GOTPCREL32 = 2,
155     MO_GOTPCREL32_LO = 2,
156     // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
157     MO_GOTPCREL32_HI = 3,
158     // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
159     MO_REL32 = 4,
160     MO_REL32_LO = 4,
161     // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
162     MO_REL32_HI = 5,
163 
164     MO_LONG_BRANCH_FORWARD = 6,
165     MO_LONG_BRANCH_BACKWARD = 7,
166 
167     MO_ABS32_LO = 8,
168     MO_ABS32_HI = 9,
169   };
170 
171   explicit SIInstrInfo(const GCNSubtarget &ST);
172 
173   const SIRegisterInfo &getRegisterInfo() const {
174     return RI;
175   }
176 
177   bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
178                                          AAResults *AA) const override;
179 
180   bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
181                                int64_t &Offset1,
182                                int64_t &Offset2) const override;
183 
184   bool
185   getMemOperandsWithOffset(const MachineInstr &LdSt,
186                            SmallVectorImpl<const MachineOperand *> &BaseOps,
187                            int64_t &Offset,
188                            const TargetRegisterInfo *TRI) const final;
189 
190   bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
191                            ArrayRef<const MachineOperand *> BaseOps2,
192                            unsigned NumLoads) const override;
193 
194   bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
195                                int64_t Offset1, unsigned NumLoads) const override;
196 
197   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
198                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
199                    bool KillSrc) const override;
200 
201   unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineInstr &MI,
202                                     RegScavenger *RS, unsigned TmpReg,
203                                     unsigned Offset, unsigned Size) const;
204 
205   void materializeImmediate(MachineBasicBlock &MBB,
206                             MachineBasicBlock::iterator MI,
207                             const DebugLoc &DL,
208                             unsigned DestReg,
209                             int64_t Value) const;
210 
211   const TargetRegisterClass *getPreferredSelectRegClass(
212                                unsigned Size) const;
213 
214   unsigned insertNE(MachineBasicBlock *MBB,
215                     MachineBasicBlock::iterator I, const DebugLoc &DL,
216                     unsigned SrcReg, int Value) const;
217 
218   unsigned insertEQ(MachineBasicBlock *MBB,
219                     MachineBasicBlock::iterator I, const DebugLoc &DL,
220                     unsigned SrcReg, int Value)  const;
221 
222   void storeRegToStackSlot(MachineBasicBlock &MBB,
223                            MachineBasicBlock::iterator MI, Register SrcReg,
224                            bool isKill, int FrameIndex,
225                            const TargetRegisterClass *RC,
226                            const TargetRegisterInfo *TRI) const override;
227 
228   void loadRegFromStackSlot(MachineBasicBlock &MBB,
229                             MachineBasicBlock::iterator MI, Register DestReg,
230                             int FrameIndex, const TargetRegisterClass *RC,
231                             const TargetRegisterInfo *TRI) const override;
232 
233   bool expandPostRAPseudo(MachineInstr &MI) const override;
234 
235   // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
236   // instructions. Returns a pair of generated instructions.
237   // Can split either post-RA with physical registers or pre-RA with
238   // virtual registers. In latter case IR needs to be in SSA form and
239   // and a REG_SEQUENCE is produced to define original register.
240   std::pair<MachineInstr*, MachineInstr*>
241   expandMovDPP64(MachineInstr &MI) const;
242 
243   // Returns an opcode that can be used to move a value to a \p DstRC
244   // register.  If there is no hardware instruction that can store to \p
245   // DstRC, then AMDGPU::COPY is returned.
246   unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
247 
248   const MCInstrDesc &getIndirectRegWritePseudo(
249     unsigned VecSize, unsigned EltSize, bool IsSGPR) const;
250 
251   LLVM_READONLY
252   int commuteOpcode(unsigned Opc) const;
253 
254   LLVM_READONLY
255   inline int commuteOpcode(const MachineInstr &MI) const {
256     return commuteOpcode(MI.getOpcode());
257   }
258 
259   bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
260                              unsigned &SrcOpIdx2) const override;
261 
262   bool findCommutedOpIndices(MCInstrDesc Desc, unsigned & SrcOpIdx0,
263    unsigned & SrcOpIdx1) const;
264 
265   bool isBranchOffsetInRange(unsigned BranchOpc,
266                              int64_t BrOffset) const override;
267 
268   MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
269 
270   unsigned insertIndirectBranch(MachineBasicBlock &MBB,
271                                 MachineBasicBlock &NewDestBB,
272                                 const DebugLoc &DL,
273                                 int64_t BrOffset,
274                                 RegScavenger *RS = nullptr) const override;
275 
276   bool analyzeBranchImpl(MachineBasicBlock &MBB,
277                          MachineBasicBlock::iterator I,
278                          MachineBasicBlock *&TBB,
279                          MachineBasicBlock *&FBB,
280                          SmallVectorImpl<MachineOperand> &Cond,
281                          bool AllowModify) const;
282 
283   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
284                      MachineBasicBlock *&FBB,
285                      SmallVectorImpl<MachineOperand> &Cond,
286                      bool AllowModify = false) const override;
287 
288   unsigned removeBranch(MachineBasicBlock &MBB,
289                         int *BytesRemoved = nullptr) const override;
290 
291   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
292                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
293                         const DebugLoc &DL,
294                         int *BytesAdded = nullptr) const override;
295 
296   bool reverseBranchCondition(
297     SmallVectorImpl<MachineOperand> &Cond) const override;
298 
299   bool canInsertSelect(const MachineBasicBlock &MBB,
300                        ArrayRef<MachineOperand> Cond, unsigned DstReg,
301                        unsigned TrueReg, unsigned FalseReg, int &CondCycles,
302                        int &TrueCycles, int &FalseCycles) const override;
303 
304   void insertSelect(MachineBasicBlock &MBB,
305                     MachineBasicBlock::iterator I, const DebugLoc &DL,
306                     unsigned DstReg, ArrayRef<MachineOperand> Cond,
307                     unsigned TrueReg, unsigned FalseReg) const override;
308 
309   void insertVectorSelect(MachineBasicBlock &MBB,
310                           MachineBasicBlock::iterator I, const DebugLoc &DL,
311                           unsigned DstReg, ArrayRef<MachineOperand> Cond,
312                           unsigned TrueReg, unsigned FalseReg) const;
313 
314   unsigned getAddressSpaceForPseudoSourceKind(
315              unsigned Kind) const override;
316 
317   bool
318   areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
319                                   const MachineInstr &MIb) const override;
320 
321   bool isFoldableCopy(const MachineInstr &MI) const;
322 
323   bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
324                      MachineRegisterInfo *MRI) const final;
325 
326   unsigned getMachineCSELookAheadLimit() const override { return 500; }
327 
328   MachineInstr *convertToThreeAddress(MachineFunction::iterator &MBB,
329                                       MachineInstr &MI,
330                                       LiveVariables *LV) const override;
331 
332   bool isSchedulingBoundary(const MachineInstr &MI,
333                             const MachineBasicBlock *MBB,
334                             const MachineFunction &MF) const override;
335 
336   static bool isSALU(const MachineInstr &MI) {
337     return MI.getDesc().TSFlags & SIInstrFlags::SALU;
338   }
339 
340   bool isSALU(uint16_t Opcode) const {
341     return get(Opcode).TSFlags & SIInstrFlags::SALU;
342   }
343 
344   static bool isVALU(const MachineInstr &MI) {
345     return MI.getDesc().TSFlags & SIInstrFlags::VALU;
346   }
347 
348   bool isVALU(uint16_t Opcode) const {
349     return get(Opcode).TSFlags & SIInstrFlags::VALU;
350   }
351 
352   static bool isVMEM(const MachineInstr &MI) {
353     return isMUBUF(MI) || isMTBUF(MI) || isMIMG(MI);
354   }
355 
356   bool isVMEM(uint16_t Opcode) const {
357     return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode);
358   }
359 
360   static bool isSOP1(const MachineInstr &MI) {
361     return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
362   }
363 
364   bool isSOP1(uint16_t Opcode) const {
365     return get(Opcode).TSFlags & SIInstrFlags::SOP1;
366   }
367 
368   static bool isSOP2(const MachineInstr &MI) {
369     return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
370   }
371 
372   bool isSOP2(uint16_t Opcode) const {
373     return get(Opcode).TSFlags & SIInstrFlags::SOP2;
374   }
375 
376   static bool isSOPC(const MachineInstr &MI) {
377     return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
378   }
379 
380   bool isSOPC(uint16_t Opcode) const {
381     return get(Opcode).TSFlags & SIInstrFlags::SOPC;
382   }
383 
384   static bool isSOPK(const MachineInstr &MI) {
385     return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
386   }
387 
388   bool isSOPK(uint16_t Opcode) const {
389     return get(Opcode).TSFlags & SIInstrFlags::SOPK;
390   }
391 
392   static bool isSOPP(const MachineInstr &MI) {
393     return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
394   }
395 
396   bool isSOPP(uint16_t Opcode) const {
397     return get(Opcode).TSFlags & SIInstrFlags::SOPP;
398   }
399 
400   static bool isPacked(const MachineInstr &MI) {
401     return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
402   }
403 
404   bool isPacked(uint16_t Opcode) const {
405     return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
406   }
407 
408   static bool isVOP1(const MachineInstr &MI) {
409     return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
410   }
411 
412   bool isVOP1(uint16_t Opcode) const {
413     return get(Opcode).TSFlags & SIInstrFlags::VOP1;
414   }
415 
416   static bool isVOP2(const MachineInstr &MI) {
417     return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
418   }
419 
420   bool isVOP2(uint16_t Opcode) const {
421     return get(Opcode).TSFlags & SIInstrFlags::VOP2;
422   }
423 
424   static bool isVOP3(const MachineInstr &MI) {
425     return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
426   }
427 
428   bool isVOP3(uint16_t Opcode) const {
429     return get(Opcode).TSFlags & SIInstrFlags::VOP3;
430   }
431 
432   static bool isSDWA(const MachineInstr &MI) {
433     return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
434   }
435 
436   bool isSDWA(uint16_t Opcode) const {
437     return get(Opcode).TSFlags & SIInstrFlags::SDWA;
438   }
439 
440   static bool isVOPC(const MachineInstr &MI) {
441     return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
442   }
443 
444   bool isVOPC(uint16_t Opcode) const {
445     return get(Opcode).TSFlags & SIInstrFlags::VOPC;
446   }
447 
448   static bool isMUBUF(const MachineInstr &MI) {
449     return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
450   }
451 
452   bool isMUBUF(uint16_t Opcode) const {
453     return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
454   }
455 
456   static bool isMTBUF(const MachineInstr &MI) {
457     return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
458   }
459 
460   bool isMTBUF(uint16_t Opcode) const {
461     return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
462   }
463 
464   static bool isSMRD(const MachineInstr &MI) {
465     return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
466   }
467 
468   bool isSMRD(uint16_t Opcode) const {
469     return get(Opcode).TSFlags & SIInstrFlags::SMRD;
470   }
471 
472   bool isBufferSMRD(const MachineInstr &MI) const;
473 
474   static bool isDS(const MachineInstr &MI) {
475     return MI.getDesc().TSFlags & SIInstrFlags::DS;
476   }
477 
478   bool isDS(uint16_t Opcode) const {
479     return get(Opcode).TSFlags & SIInstrFlags::DS;
480   }
481 
482   bool isAlwaysGDS(uint16_t Opcode) const;
483 
484   static bool isMIMG(const MachineInstr &MI) {
485     return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
486   }
487 
488   bool isMIMG(uint16_t Opcode) const {
489     return get(Opcode).TSFlags & SIInstrFlags::MIMG;
490   }
491 
492   static bool isGather4(const MachineInstr &MI) {
493     return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
494   }
495 
496   bool isGather4(uint16_t Opcode) const {
497     return get(Opcode).TSFlags & SIInstrFlags::Gather4;
498   }
499 
500   static bool isFLAT(const MachineInstr &MI) {
501     return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
502   }
503 
504   // Is a FLAT encoded instruction which accesses a specific segment,
505   // i.e. global_* or scratch_*.
506   static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
507     auto Flags = MI.getDesc().TSFlags;
508     return (Flags & SIInstrFlags::FLAT) && !(Flags & SIInstrFlags::LGKM_CNT);
509   }
510 
511   // FIXME: Make this more precise
512   static bool isFLATScratch(const MachineInstr &MI) {
513     return isSegmentSpecificFLAT(MI);
514   }
515 
516   // Any FLAT encoded instruction, including global_* and scratch_*.
517   bool isFLAT(uint16_t Opcode) const {
518     return get(Opcode).TSFlags & SIInstrFlags::FLAT;
519   }
520 
521   static bool isEXP(const MachineInstr &MI) {
522     return MI.getDesc().TSFlags & SIInstrFlags::EXP;
523   }
524 
525   bool isEXP(uint16_t Opcode) const {
526     return get(Opcode).TSFlags & SIInstrFlags::EXP;
527   }
528 
529   static bool isWQM(const MachineInstr &MI) {
530     return MI.getDesc().TSFlags & SIInstrFlags::WQM;
531   }
532 
533   bool isWQM(uint16_t Opcode) const {
534     return get(Opcode).TSFlags & SIInstrFlags::WQM;
535   }
536 
537   static bool isDisableWQM(const MachineInstr &MI) {
538     return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
539   }
540 
541   bool isDisableWQM(uint16_t Opcode) const {
542     return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
543   }
544 
545   static bool isVGPRSpill(const MachineInstr &MI) {
546     return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;
547   }
548 
549   bool isVGPRSpill(uint16_t Opcode) const {
550     return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
551   }
552 
553   static bool isSGPRSpill(const MachineInstr &MI) {
554     return MI.getDesc().TSFlags & SIInstrFlags::SGPRSpill;
555   }
556 
557   bool isSGPRSpill(uint16_t Opcode) const {
558     return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
559   }
560 
561   static bool isDPP(const MachineInstr &MI) {
562     return MI.getDesc().TSFlags & SIInstrFlags::DPP;
563   }
564 
565   bool isDPP(uint16_t Opcode) const {
566     return get(Opcode).TSFlags & SIInstrFlags::DPP;
567   }
568 
569   static bool isVOP3P(const MachineInstr &MI) {
570     return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
571   }
572 
573   bool isVOP3P(uint16_t Opcode) const {
574     return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
575   }
576 
577   static bool isVINTRP(const MachineInstr &MI) {
578     return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
579   }
580 
581   bool isVINTRP(uint16_t Opcode) const {
582     return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
583   }
584 
585   static bool isMAI(const MachineInstr &MI) {
586     return MI.getDesc().TSFlags & SIInstrFlags::IsMAI;
587   }
588 
589   bool isMAI(uint16_t Opcode) const {
590     return get(Opcode).TSFlags & SIInstrFlags::IsMAI;
591   }
592 
593   static bool isDOT(const MachineInstr &MI) {
594     return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
595   }
596 
597   bool isDOT(uint16_t Opcode) const {
598     return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
599   }
600 
601   static bool isScalarUnit(const MachineInstr &MI) {
602     return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
603   }
604 
605   static bool usesVM_CNT(const MachineInstr &MI) {
606     return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
607   }
608 
609   static bool usesLGKM_CNT(const MachineInstr &MI) {
610     return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
611   }
612 
613   static bool sopkIsZext(const MachineInstr &MI) {
614     return MI.getDesc().TSFlags & SIInstrFlags::SOPK_ZEXT;
615   }
616 
617   bool sopkIsZext(uint16_t Opcode) const {
618     return get(Opcode).TSFlags & SIInstrFlags::SOPK_ZEXT;
619   }
620 
621   /// \returns true if this is an s_store_dword* instruction. This is more
622   /// specific than than isSMEM && mayStore.
623   static bool isScalarStore(const MachineInstr &MI) {
624     return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
625   }
626 
627   bool isScalarStore(uint16_t Opcode) const {
628     return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
629   }
630 
631   static bool isFixedSize(const MachineInstr &MI) {
632     return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
633   }
634 
635   bool isFixedSize(uint16_t Opcode) const {
636     return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
637   }
638 
639   static bool hasFPClamp(const MachineInstr &MI) {
640     return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
641   }
642 
643   bool hasFPClamp(uint16_t Opcode) const {
644     return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
645   }
646 
647   static bool hasIntClamp(const MachineInstr &MI) {
648     return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
649   }
650 
651   uint64_t getClampMask(const MachineInstr &MI) const {
652     const uint64_t ClampFlags = SIInstrFlags::FPClamp |
653                                 SIInstrFlags::IntClamp |
654                                 SIInstrFlags::ClampLo |
655                                 SIInstrFlags::ClampHi;
656       return MI.getDesc().TSFlags & ClampFlags;
657   }
658 
659   static bool usesFPDPRounding(const MachineInstr &MI) {
660     return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
661   }
662 
663   bool usesFPDPRounding(uint16_t Opcode) const {
664     return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
665   }
666 
667   static bool isFPAtomic(const MachineInstr &MI) {
668     return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
669   }
670 
671   bool isFPAtomic(uint16_t Opcode) const {
672     return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
673   }
674 
675   bool isVGPRCopy(const MachineInstr &MI) const {
676     assert(MI.isCopy());
677     unsigned Dest = MI.getOperand(0).getReg();
678     const MachineFunction &MF = *MI.getParent()->getParent();
679     const MachineRegisterInfo &MRI = MF.getRegInfo();
680     return !RI.isSGPRReg(MRI, Dest);
681   }
682 
683   bool hasVGPRUses(const MachineInstr &MI) const {
684     const MachineFunction &MF = *MI.getParent()->getParent();
685     const MachineRegisterInfo &MRI = MF.getRegInfo();
686     return llvm::any_of(MI.explicit_uses(),
687                         [&MRI, this](const MachineOperand &MO) {
688       return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
689   }
690 
691   /// Whether we must prevent this instruction from executing with EXEC = 0.
692   bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const;
693 
694   /// Returns true if the instruction could potentially depend on the value of
695   /// exec. If false, exec dependencies may safely be ignored.
696   bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
697 
698   bool isInlineConstant(const APInt &Imm) const;
699 
700   bool isInlineConstant(const APFloat &Imm) const {
701     return isInlineConstant(Imm.bitcastToAPInt());
702   }
703 
704   bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
705 
706   bool isInlineConstant(const MachineOperand &MO,
707                         const MCOperandInfo &OpInfo) const {
708     return isInlineConstant(MO, OpInfo.OperandType);
709   }
710 
711   /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
712   /// be an inline immediate.
713   bool isInlineConstant(const MachineInstr &MI,
714                         const MachineOperand &UseMO,
715                         const MachineOperand &DefMO) const {
716     assert(UseMO.getParent() == &MI);
717     int OpIdx = MI.getOperandNo(&UseMO);
718     if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) {
719       return false;
720     }
721 
722     return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]);
723   }
724 
725   /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
726   /// immediate.
727   bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
728     const MachineOperand &MO = MI.getOperand(OpIdx);
729     return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
730   }
731 
732   bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
733                         const MachineOperand &MO) const {
734     if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands)
735       return false;
736 
737     if (MI.isCopy()) {
738       unsigned Size = getOpSize(MI, OpIdx);
739       assert(Size == 8 || Size == 4);
740 
741       uint8_t OpType = (Size == 8) ?
742         AMDGPU::OPERAND_REG_IMM_INT64 : AMDGPU::OPERAND_REG_IMM_INT32;
743       return isInlineConstant(MO, OpType);
744     }
745 
746     return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
747   }
748 
749   bool isInlineConstant(const MachineOperand &MO) const {
750     const MachineInstr *Parent = MO.getParent();
751     return isInlineConstant(*Parent, Parent->getOperandNo(&MO));
752   }
753 
754   bool isLiteralConstant(const MachineOperand &MO,
755                          const MCOperandInfo &OpInfo) const {
756     return MO.isImm() && !isInlineConstant(MO, OpInfo.OperandType);
757   }
758 
759   bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const {
760     const MachineOperand &MO = MI.getOperand(OpIdx);
761     return MO.isImm() && !isInlineConstant(MI, OpIdx);
762   }
763 
764   // Returns true if this operand could potentially require a 32-bit literal
765   // operand, but not necessarily. A FrameIndex for example could resolve to an
766   // inline immediate value that will not require an additional 4-bytes; this
767   // assumes that it will.
768   bool isLiteralConstantLike(const MachineOperand &MO,
769                              const MCOperandInfo &OpInfo) const;
770 
771   bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
772                          const MachineOperand &MO) const;
773 
774   /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
775   /// This function will return false if you pass it a 32-bit instruction.
776   bool hasVALU32BitEncoding(unsigned Opcode) const;
777 
778   /// Returns true if this operand uses the constant bus.
779   bool usesConstantBus(const MachineRegisterInfo &MRI,
780                        const MachineOperand &MO,
781                        const MCOperandInfo &OpInfo) const;
782 
783   /// Return true if this instruction has any modifiers.
784   ///  e.g. src[012]_mod, omod, clamp.
785   bool hasModifiers(unsigned Opcode) const;
786 
787   bool hasModifiersSet(const MachineInstr &MI,
788                        unsigned OpName) const;
789   bool hasAnyModifiersSet(const MachineInstr &MI) const;
790 
791   bool canShrink(const MachineInstr &MI,
792                  const MachineRegisterInfo &MRI) const;
793 
794   MachineInstr *buildShrunkInst(MachineInstr &MI,
795                                 unsigned NewOpcode) const;
796 
797   bool verifyInstruction(const MachineInstr &MI,
798                          StringRef &ErrInfo) const override;
799 
800   unsigned getVALUOp(const MachineInstr &MI) const;
801 
802   /// Return the correct register class for \p OpNo.  For target-specific
803   /// instructions, this will return the register class that has been defined
804   /// in tablegen.  For generic instructions, like REG_SEQUENCE it will return
805   /// the register class of its machine operand.
806   /// to infer the correct register class base on the other operands.
807   const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
808                                            unsigned OpNo) const;
809 
810   /// Return the size in bytes of the operand OpNo on the given
811   // instruction opcode.
812   unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
813     const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
814 
815     if (OpInfo.RegClass == -1) {
816       // If this is an immediate operand, this must be a 32-bit literal.
817       assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
818       return 4;
819     }
820 
821     return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
822   }
823 
824   /// This form should usually be preferred since it handles operands
825   /// with unknown register classes.
826   unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
827     const MachineOperand &MO = MI.getOperand(OpNo);
828     if (MO.isReg()) {
829       if (unsigned SubReg = MO.getSubReg()) {
830         assert(RI.getRegSizeInBits(*RI.getSubClassWithSubReg(
831                                    MI.getParent()->getParent()->getRegInfo().
832                                      getRegClass(MO.getReg()), SubReg)) >= 32 &&
833                "Sub-dword subregs are not supported");
834         return RI.getSubRegIndexLaneMask(SubReg).getNumLanes() * 4;
835       }
836     }
837     return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
838   }
839 
840   /// Legalize the \p OpIndex operand of this instruction by inserting
841   /// a MOV.  For example:
842   /// ADD_I32_e32 VGPR0, 15
843   /// to
844   /// MOV VGPR1, 15
845   /// ADD_I32_e32 VGPR0, VGPR1
846   ///
847   /// If the operand being legalized is a register, then a COPY will be used
848   /// instead of MOV.
849   void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
850 
851   /// Check if \p MO is a legal operand if it was the \p OpIdx Operand
852   /// for \p MI.
853   bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
854                       const MachineOperand *MO = nullptr) const;
855 
856   /// Check if \p MO would be a valid operand for the given operand
857   /// definition \p OpInfo. Note this does not attempt to validate constant bus
858   /// restrictions (e.g. literal constant usage).
859   bool isLegalVSrcOperand(const MachineRegisterInfo &MRI,
860                           const MCOperandInfo &OpInfo,
861                           const MachineOperand &MO) const;
862 
863   /// Check if \p MO (a register operand) is a legal register for the
864   /// given operand description.
865   bool isLegalRegOperand(const MachineRegisterInfo &MRI,
866                          const MCOperandInfo &OpInfo,
867                          const MachineOperand &MO) const;
868 
869   /// Legalize operands in \p MI by either commuting it or inserting a
870   /// copy of src1.
871   void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const;
872 
873   /// Fix operands in \p MI to satisfy constant bus requirements.
874   void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const;
875 
876   /// Copy a value from a VGPR (\p SrcReg) to SGPR.  This function can only
877   /// be used when it is know that the value in SrcReg is same across all
878   /// threads in the wave.
879   /// \returns The SGPR register that \p SrcReg was copied to.
880   unsigned readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI,
881                               MachineRegisterInfo &MRI) const;
882 
883   void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const;
884 
885   void legalizeGenericOperand(MachineBasicBlock &InsertMBB,
886                               MachineBasicBlock::iterator I,
887                               const TargetRegisterClass *DstRC,
888                               MachineOperand &Op, MachineRegisterInfo &MRI,
889                               const DebugLoc &DL) const;
890 
891   /// Legalize all operands in this instruction.  This function may create new
892   /// instructions and control-flow around \p MI.  If present, \p MDT is
893   /// updated.
894   void legalizeOperands(MachineInstr &MI,
895                         MachineDominatorTree *MDT = nullptr) const;
896 
897   /// Replace this instruction's opcode with the equivalent VALU
898   /// opcode.  This function will also move the users of \p MI to the
899   /// VALU if necessary. If present, \p MDT is updated.
900   void moveToVALU(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
901 
902   void insertWaitStates(MachineBasicBlock &MBB,MachineBasicBlock::iterator MI,
903                         int Count) const;
904 
905   void insertNoop(MachineBasicBlock &MBB,
906                   MachineBasicBlock::iterator MI) const override;
907 
908   void insertReturn(MachineBasicBlock &MBB) const;
909   /// Return the number of wait states that result from executing this
910   /// instruction.
911   static unsigned getNumWaitStates(const MachineInstr &MI);
912 
913   /// Returns the operand named \p Op.  If \p MI does not have an
914   /// operand named \c Op, this function returns nullptr.
915   LLVM_READONLY
916   MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
917 
918   LLVM_READONLY
919   const MachineOperand *getNamedOperand(const MachineInstr &MI,
920                                         unsigned OpName) const {
921     return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
922   }
923 
924   /// Get required immediate operand
925   int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
926     int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
927     return MI.getOperand(Idx).getImm();
928   }
929 
930   uint64_t getDefaultRsrcDataFormat() const;
931   uint64_t getScratchRsrcWords23() const;
932 
933   bool isLowLatencyInstruction(const MachineInstr &MI) const;
934   bool isHighLatencyDef(int Opc) const override;
935 
936   /// Return the descriptor of the target-specific machine instruction
937   /// that corresponds to the specified pseudo or native opcode.
938   const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
939     return get(pseudoToMCOpcode(Opcode));
940   }
941 
942   unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
943   unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
944 
945   unsigned isLoadFromStackSlot(const MachineInstr &MI,
946                                int &FrameIndex) const override;
947   unsigned isStoreToStackSlot(const MachineInstr &MI,
948                               int &FrameIndex) const override;
949 
950   unsigned getInstBundleSize(const MachineInstr &MI) const;
951   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
952 
953   bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
954 
955   bool isNonUniformBranchInstr(MachineInstr &Instr) const;
956 
957   void convertNonUniformIfRegion(MachineBasicBlock *IfEntry,
958                                  MachineBasicBlock *IfEnd) const;
959 
960   void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry,
961                                    MachineBasicBlock *LoopEnd) const;
962 
963   std::pair<unsigned, unsigned>
964   decomposeMachineOperandsTargetFlags(unsigned TF) const override;
965 
966   ArrayRef<std::pair<int, const char *>>
967   getSerializableTargetIndices() const override;
968 
969   ArrayRef<std::pair<unsigned, const char *>>
970   getSerializableDirectMachineOperandTargetFlags() const override;
971 
972   ScheduleHazardRecognizer *
973   CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
974                                  const ScheduleDAG *DAG) const override;
975 
976   ScheduleHazardRecognizer *
977   CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
978 
979   bool isBasicBlockPrologue(const MachineInstr &MI) const override;
980 
981   MachineInstr *createPHIDestinationCopy(MachineBasicBlock &MBB,
982                                          MachineBasicBlock::iterator InsPt,
983                                          const DebugLoc &DL, Register Src,
984                                          Register Dst) const override;
985 
986   MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB,
987                                     MachineBasicBlock::iterator InsPt,
988                                     const DebugLoc &DL, Register Src,
989                                     unsigned SrcSubReg,
990                                     Register Dst) const override;
991 
992   bool isWave32() const;
993 
994   /// Return a partially built integer add instruction without carry.
995   /// Caller must add source operands.
996   /// For pre-GFX9 it will generate unused carry destination operand.
997   /// TODO: After GFX9 it should return a no-carry operation.
998   MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
999                                     MachineBasicBlock::iterator I,
1000                                     const DebugLoc &DL,
1001                                     unsigned DestReg) const;
1002 
1003   MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
1004                                     MachineBasicBlock::iterator I,
1005                                     const DebugLoc &DL,
1006                                     Register DestReg,
1007                                     RegScavenger &RS) const;
1008 
1009   static bool isKillTerminator(unsigned Opcode);
1010   const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
1011 
1012   static bool isLegalMUBUFImmOffset(unsigned Imm) {
1013     return isUInt<12>(Imm);
1014   }
1015 
1016   unsigned getNumFlatOffsetBits(unsigned AddrSpace, bool Signed) const;
1017 
1018   /// Returns if \p Offset is legal for the subtarget as the offset to a FLAT
1019   /// encoded instruction. If \p Signed, this is for an instruction that
1020   /// interprets the offset as signed.
1021   bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
1022                          bool Signed) const;
1023 
1024   /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
1025   /// Return -1 if the target-specific opcode for the pseudo instruction does
1026   /// not exist. If Opcode is not a pseudo instruction, this is identity.
1027   int pseudoToMCOpcode(int Opcode) const;
1028 
1029   /// \brief Check if this instruction should only be used by assembler.
1030   /// Return true if this opcode should not be used by codegen.
1031   bool isAsmOnlyOpcode(int MCOp) const;
1032 
1033   const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
1034                                          const TargetRegisterInfo *TRI,
1035                                          const MachineFunction &MF)
1036     const override {
1037     if (OpNum >= TID.getNumOperands())
1038       return nullptr;
1039     return RI.getRegClass(TID.OpInfo[OpNum].RegClass);
1040   }
1041 
1042   void fixImplicitOperands(MachineInstr &MI) const;
1043 
1044   MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
1045                                       ArrayRef<unsigned> Ops,
1046                                       MachineBasicBlock::iterator InsertPt,
1047                                       int FrameIndex,
1048                                       LiveIntervals *LIS = nullptr,
1049                                       VirtRegMap *VRM = nullptr) const override;
1050 
1051   unsigned getInstrLatency(const InstrItineraryData *ItinData,
1052                            const MachineInstr &MI,
1053                            unsigned *PredCost = nullptr) const override;
1054 };
1055 
1056 /// \brief Returns true if a reg:subreg pair P has a TRC class
1057 inline bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P,
1058                          const TargetRegisterClass &TRC,
1059                          MachineRegisterInfo &MRI) {
1060   auto *RC = MRI.getRegClass(P.Reg);
1061   if (!P.SubReg)
1062     return RC == &TRC;
1063   auto *TRI = MRI.getTargetRegisterInfo();
1064   return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg);
1065 }
1066 
1067 /// \brief Create RegSubRegPair from a register MachineOperand
1068 inline
1069 TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O) {
1070   assert(O.isReg());
1071   return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
1072 }
1073 
1074 /// \brief Return the SubReg component from REG_SEQUENCE
1075 TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI,
1076                                                     unsigned SubReg);
1077 
1078 /// \brief Return the defining instruction for a given reg:subreg pair
1079 /// skipping copy like instructions and subreg-manipulation pseudos.
1080 /// Following another subreg of a reg:subreg isn't supported.
1081 MachineInstr *getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P,
1082                                MachineRegisterInfo &MRI);
1083 
1084 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1085 /// DefMI and the use at \p UseMI. Should be run on SSA. Currently does not
1086 /// attempt to track between blocks.
1087 bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
1088                                 Register VReg,
1089                                 const MachineInstr &DefMI,
1090                                 const MachineInstr &UseMI);
1091 
1092 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1093 /// DefMI and all its uses. Should be run on SSA. Currently does not attempt to
1094 /// track between blocks.
1095 bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
1096                                    Register VReg,
1097                                    const MachineInstr &DefMI);
1098 
1099 namespace AMDGPU {
1100 
1101   LLVM_READONLY
1102   int getVOPe64(uint16_t Opcode);
1103 
1104   LLVM_READONLY
1105   int getVOPe32(uint16_t Opcode);
1106 
1107   LLVM_READONLY
1108   int getSDWAOp(uint16_t Opcode);
1109 
1110   LLVM_READONLY
1111   int getDPPOp32(uint16_t Opcode);
1112 
1113   LLVM_READONLY
1114   int getBasicFromSDWAOp(uint16_t Opcode);
1115 
1116   LLVM_READONLY
1117   int getCommuteRev(uint16_t Opcode);
1118 
1119   LLVM_READONLY
1120   int getCommuteOrig(uint16_t Opcode);
1121 
1122   LLVM_READONLY
1123   int getAddr64Inst(uint16_t Opcode);
1124 
1125   /// Check if \p Opcode is an Addr64 opcode.
1126   ///
1127   /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
1128   LLVM_READONLY
1129   int getIfAddr64Inst(uint16_t Opcode);
1130 
1131   LLVM_READONLY
1132   int getMUBUFNoLdsInst(uint16_t Opcode);
1133 
1134   LLVM_READONLY
1135   int getAtomicRetOp(uint16_t Opcode);
1136 
1137   LLVM_READONLY
1138   int getAtomicNoRetOp(uint16_t Opcode);
1139 
1140   LLVM_READONLY
1141   int getSOPKOp(uint16_t Opcode);
1142 
1143   LLVM_READONLY
1144   int getGlobalSaddrOp(uint16_t Opcode);
1145 
1146   LLVM_READONLY
1147   int getVCMPXNoSDstOp(uint16_t Opcode);
1148 
1149   const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
1150   const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19);
1151   const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);
1152   const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
1153 
1154 } // end namespace AMDGPU
1155 
1156 namespace SI {
1157 namespace KernelInputOffsets {
1158 
1159 /// Offsets in bytes from the start of the input buffer
1160 enum Offsets {
1161   NGROUPS_X = 0,
1162   NGROUPS_Y = 4,
1163   NGROUPS_Z = 8,
1164   GLOBAL_SIZE_X = 12,
1165   GLOBAL_SIZE_Y = 16,
1166   GLOBAL_SIZE_Z = 20,
1167   LOCAL_SIZE_X = 24,
1168   LOCAL_SIZE_Y = 28,
1169   LOCAL_SIZE_Z = 32
1170 };
1171 
1172 } // end namespace KernelInputOffsets
1173 } // end namespace SI
1174 
1175 } // end namespace llvm
1176 
1177 #endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
1178