1 //===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIInstrInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
16 
17 #include "AMDGPUMIRFormatter.h"
18 #include "SIRegisterInfo.h"
19 #include "Utils/AMDGPUBaseInfo.h"
20 #include "llvm/ADT/SetVector.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/TargetSchedule.h"
23 
24 #define GET_INSTRINFO_HEADER
25 #include "AMDGPUGenInstrInfo.inc"
26 
27 namespace llvm {
28 
29 class APInt;
30 class GCNSubtarget;
31 class LiveVariables;
32 class MachineDominatorTree;
33 class MachineRegisterInfo;
34 class RegScavenger;
35 class TargetRegisterClass;
36 class ScheduleHazardRecognizer;
37 
38 /// Mark the MMO of a uniform load if there are no potentially clobbering stores
39 /// on any path from the start of an entry function to this load.
40 static const MachineMemOperand::Flags MONoClobber =
41     MachineMemOperand::MOTargetFlag1;
42 
43 class SIInstrInfo final : public AMDGPUGenInstrInfo {
44 private:
45   const SIRegisterInfo RI;
46   const GCNSubtarget &ST;
47   TargetSchedModel SchedModel;
48   mutable std::unique_ptr<AMDGPUMIRFormatter> Formatter;
49 
50   // The inverse predicate should have the negative value.
51   enum BranchPredicate {
52     INVALID_BR = 0,
53     SCC_TRUE = 1,
54     SCC_FALSE = -1,
55     VCCNZ = 2,
56     VCCZ = -2,
57     EXECNZ = -3,
58     EXECZ = 3
59   };
60 
61   using SetVectorType = SmallSetVector<MachineInstr *, 32>;
62 
63   static unsigned getBranchOpcode(BranchPredicate Cond);
64   static BranchPredicate getBranchPredicate(unsigned Opcode);
65 
66 public:
67   unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
68                               MachineRegisterInfo &MRI,
69                               MachineOperand &SuperReg,
70                               const TargetRegisterClass *SuperRC,
71                               unsigned SubIdx,
72                               const TargetRegisterClass *SubRC) const;
73   MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
74                                          MachineRegisterInfo &MRI,
75                                          MachineOperand &SuperReg,
76                                          const TargetRegisterClass *SuperRC,
77                                          unsigned SubIdx,
78                                          const TargetRegisterClass *SubRC) const;
79 private:
80   void swapOperands(MachineInstr &Inst) const;
81 
82   std::pair<bool, MachineBasicBlock *>
83   moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
84                    MachineDominatorTree *MDT = nullptr) const;
85 
86   void lowerSelect(SetVectorType &Worklist, MachineInstr &Inst,
87                    MachineDominatorTree *MDT = nullptr) const;
88 
89   void lowerScalarAbs(SetVectorType &Worklist,
90                       MachineInstr &Inst) const;
91 
92   void lowerScalarXnor(SetVectorType &Worklist,
93                        MachineInstr &Inst) const;
94 
95   void splitScalarNotBinop(SetVectorType &Worklist,
96                            MachineInstr &Inst,
97                            unsigned Opcode) const;
98 
99   void splitScalarBinOpN2(SetVectorType &Worklist,
100                           MachineInstr &Inst,
101                           unsigned Opcode) const;
102 
103   void splitScalar64BitUnaryOp(SetVectorType &Worklist,
104                                MachineInstr &Inst, unsigned Opcode,
105                                bool Swap = false) const;
106 
107   void splitScalar64BitAddSub(SetVectorType &Worklist, MachineInstr &Inst,
108                               MachineDominatorTree *MDT = nullptr) const;
109 
110   void splitScalar64BitBinaryOp(SetVectorType &Worklist, MachineInstr &Inst,
111                                 unsigned Opcode,
112                                 MachineDominatorTree *MDT = nullptr) const;
113 
114   void splitScalar64BitXnor(SetVectorType &Worklist, MachineInstr &Inst,
115                                 MachineDominatorTree *MDT = nullptr) const;
116 
117   void splitScalar64BitBCNT(SetVectorType &Worklist,
118                             MachineInstr &Inst) const;
119   void splitScalar64BitBFE(SetVectorType &Worklist,
120                            MachineInstr &Inst) const;
121   void movePackToVALU(SetVectorType &Worklist,
122                       MachineRegisterInfo &MRI,
123                       MachineInstr &Inst) const;
124 
125   void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
126                                     SetVectorType &Worklist) const;
127 
128   void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
129                                     MachineInstr &SCCDefInst,
130                                     SetVectorType &Worklist,
131                                     Register NewCond = Register()) const;
132   void addSCCDefsToVALUWorklist(MachineOperand &Op,
133                                 SetVectorType &Worklist) const;
134 
135   const TargetRegisterClass *
136   getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
137 
138   bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
139                                     const MachineInstr &MIb) const;
140 
141   Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
142 
143 protected:
144   bool swapSourceModifiers(MachineInstr &MI,
145                            MachineOperand &Src0, unsigned Src0OpName,
146                            MachineOperand &Src1, unsigned Src1OpName) const;
147 
148   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
149                                        unsigned OpIdx0,
150                                        unsigned OpIdx1) const override;
151 
152 public:
153   enum TargetOperandFlags {
154     MO_MASK = 0xf,
155 
156     MO_NONE = 0,
157     // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
158     MO_GOTPCREL = 1,
159     // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
160     MO_GOTPCREL32 = 2,
161     MO_GOTPCREL32_LO = 2,
162     // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
163     MO_GOTPCREL32_HI = 3,
164     // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
165     MO_REL32 = 4,
166     MO_REL32_LO = 4,
167     // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
168     MO_REL32_HI = 5,
169 
170     MO_FAR_BRANCH_OFFSET = 6,
171 
172     MO_ABS32_LO = 8,
173     MO_ABS32_HI = 9,
174   };
175 
176   explicit SIInstrInfo(const GCNSubtarget &ST);
177 
178   const SIRegisterInfo &getRegisterInfo() const {
179     return RI;
180   }
181 
182   const GCNSubtarget &getSubtarget() const {
183     return ST;
184   }
185 
186   bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
187                                          AAResults *AA) const override;
188 
189   bool isIgnorableUse(const MachineOperand &MO) const override;
190 
191   bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
192                                int64_t &Offset1,
193                                int64_t &Offset2) const override;
194 
195   bool getMemOperandsWithOffsetWidth(
196       const MachineInstr &LdSt,
197       SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
198       bool &OffsetIsScalable, unsigned &Width,
199       const TargetRegisterInfo *TRI) const final;
200 
201   bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
202                            ArrayRef<const MachineOperand *> BaseOps2,
203                            unsigned NumLoads, unsigned NumBytes) const override;
204 
205   bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
206                                int64_t Offset1, unsigned NumLoads) const override;
207 
208   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
209                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
210                    bool KillSrc) const override;
211 
212   void materializeImmediate(MachineBasicBlock &MBB,
213                             MachineBasicBlock::iterator MI,
214                             const DebugLoc &DL,
215                             unsigned DestReg,
216                             int64_t Value) const;
217 
218   const TargetRegisterClass *getPreferredSelectRegClass(
219                                unsigned Size) const;
220 
221   Register insertNE(MachineBasicBlock *MBB,
222                     MachineBasicBlock::iterator I, const DebugLoc &DL,
223                     Register SrcReg, int Value) const;
224 
225   Register insertEQ(MachineBasicBlock *MBB,
226                     MachineBasicBlock::iterator I, const DebugLoc &DL,
227                     Register SrcReg, int Value)  const;
228 
229   void storeRegToStackSlot(MachineBasicBlock &MBB,
230                            MachineBasicBlock::iterator MI, Register SrcReg,
231                            bool isKill, int FrameIndex,
232                            const TargetRegisterClass *RC,
233                            const TargetRegisterInfo *TRI) const override;
234 
235   void loadRegFromStackSlot(MachineBasicBlock &MBB,
236                             MachineBasicBlock::iterator MI, Register DestReg,
237                             int FrameIndex, const TargetRegisterClass *RC,
238                             const TargetRegisterInfo *TRI) const override;
239 
240   bool expandPostRAPseudo(MachineInstr &MI) const override;
241 
242   // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
243   // instructions. Returns a pair of generated instructions.
244   // Can split either post-RA with physical registers or pre-RA with
245   // virtual registers. In latter case IR needs to be in SSA form and
246   // and a REG_SEQUENCE is produced to define original register.
247   std::pair<MachineInstr*, MachineInstr*>
248   expandMovDPP64(MachineInstr &MI) const;
249 
250   // Returns an opcode that can be used to move a value to a \p DstRC
251   // register.  If there is no hardware instruction that can store to \p
252   // DstRC, then AMDGPU::COPY is returned.
253   unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
254 
255   const MCInstrDesc &getIndirectRegWriteMovRelPseudo(unsigned VecSize,
256                                                      unsigned EltSize,
257                                                      bool IsSGPR) const;
258 
259   const MCInstrDesc &getIndirectGPRIDXPseudo(unsigned VecSize,
260                                              bool IsIndirectSrc) const;
261   LLVM_READONLY
262   int commuteOpcode(unsigned Opc) const;
263 
264   LLVM_READONLY
265   inline int commuteOpcode(const MachineInstr &MI) const {
266     return commuteOpcode(MI.getOpcode());
267   }
268 
269   bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
270                              unsigned &SrcOpIdx2) const override;
271 
272   bool findCommutedOpIndices(MCInstrDesc Desc, unsigned & SrcOpIdx0,
273    unsigned & SrcOpIdx1) const;
274 
275   bool isBranchOffsetInRange(unsigned BranchOpc,
276                              int64_t BrOffset) const override;
277 
278   MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
279 
280   void insertIndirectBranch(MachineBasicBlock &MBB,
281                             MachineBasicBlock &NewDestBB,
282                             MachineBasicBlock &RestoreBB, const DebugLoc &DL,
283                             int64_t BrOffset, RegScavenger *RS) const override;
284 
285   bool analyzeBranchImpl(MachineBasicBlock &MBB,
286                          MachineBasicBlock::iterator I,
287                          MachineBasicBlock *&TBB,
288                          MachineBasicBlock *&FBB,
289                          SmallVectorImpl<MachineOperand> &Cond,
290                          bool AllowModify) const;
291 
292   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
293                      MachineBasicBlock *&FBB,
294                      SmallVectorImpl<MachineOperand> &Cond,
295                      bool AllowModify = false) const override;
296 
297   unsigned removeBranch(MachineBasicBlock &MBB,
298                         int *BytesRemoved = nullptr) const override;
299 
300   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
301                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
302                         const DebugLoc &DL,
303                         int *BytesAdded = nullptr) const override;
304 
305   bool reverseBranchCondition(
306     SmallVectorImpl<MachineOperand> &Cond) const override;
307 
308   bool canInsertSelect(const MachineBasicBlock &MBB,
309                        ArrayRef<MachineOperand> Cond, Register DstReg,
310                        Register TrueReg, Register FalseReg, int &CondCycles,
311                        int &TrueCycles, int &FalseCycles) const override;
312 
313   void insertSelect(MachineBasicBlock &MBB,
314                     MachineBasicBlock::iterator I, const DebugLoc &DL,
315                     Register DstReg, ArrayRef<MachineOperand> Cond,
316                     Register TrueReg, Register FalseReg) const override;
317 
318   void insertVectorSelect(MachineBasicBlock &MBB,
319                           MachineBasicBlock::iterator I, const DebugLoc &DL,
320                           Register DstReg, ArrayRef<MachineOperand> Cond,
321                           Register TrueReg, Register FalseReg) const;
322 
323   bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
324                       Register &SrcReg2, int64_t &CmpMask,
325                       int64_t &CmpValue) const override;
326 
327   bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
328                             Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
329                             const MachineRegisterInfo *MRI) const override;
330 
331   bool
332   areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
333                                   const MachineInstr &MIb) const override;
334 
335   static bool isFoldableCopy(const MachineInstr &MI);
336 
337   void removeModOperands(MachineInstr &MI) const;
338 
339   bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
340                      MachineRegisterInfo *MRI) const final;
341 
342   unsigned getMachineCSELookAheadLimit() const override { return 500; }
343 
344   MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
345                                       LiveIntervals *LIS) const override;
346 
347   bool isSchedulingBoundary(const MachineInstr &MI,
348                             const MachineBasicBlock *MBB,
349                             const MachineFunction &MF) const override;
350 
351   static bool isSALU(const MachineInstr &MI) {
352     return MI.getDesc().TSFlags & SIInstrFlags::SALU;
353   }
354 
355   bool isSALU(uint16_t Opcode) const {
356     return get(Opcode).TSFlags & SIInstrFlags::SALU;
357   }
358 
359   static bool isVALU(const MachineInstr &MI) {
360     return MI.getDesc().TSFlags & SIInstrFlags::VALU;
361   }
362 
363   bool isVALU(uint16_t Opcode) const {
364     return get(Opcode).TSFlags & SIInstrFlags::VALU;
365   }
366 
367   static bool isVMEM(const MachineInstr &MI) {
368     return isMUBUF(MI) || isMTBUF(MI) || isMIMG(MI);
369   }
370 
371   bool isVMEM(uint16_t Opcode) const {
372     return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode);
373   }
374 
375   static bool isSOP1(const MachineInstr &MI) {
376     return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
377   }
378 
379   bool isSOP1(uint16_t Opcode) const {
380     return get(Opcode).TSFlags & SIInstrFlags::SOP1;
381   }
382 
383   static bool isSOP2(const MachineInstr &MI) {
384     return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
385   }
386 
387   bool isSOP2(uint16_t Opcode) const {
388     return get(Opcode).TSFlags & SIInstrFlags::SOP2;
389   }
390 
391   static bool isSOPC(const MachineInstr &MI) {
392     return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
393   }
394 
395   bool isSOPC(uint16_t Opcode) const {
396     return get(Opcode).TSFlags & SIInstrFlags::SOPC;
397   }
398 
399   static bool isSOPK(const MachineInstr &MI) {
400     return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
401   }
402 
403   bool isSOPK(uint16_t Opcode) const {
404     return get(Opcode).TSFlags & SIInstrFlags::SOPK;
405   }
406 
407   static bool isSOPP(const MachineInstr &MI) {
408     return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
409   }
410 
411   bool isSOPP(uint16_t Opcode) const {
412     return get(Opcode).TSFlags & SIInstrFlags::SOPP;
413   }
414 
415   static bool isPacked(const MachineInstr &MI) {
416     return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
417   }
418 
419   bool isPacked(uint16_t Opcode) const {
420     return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
421   }
422 
423   static bool isVOP1(const MachineInstr &MI) {
424     return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
425   }
426 
427   bool isVOP1(uint16_t Opcode) const {
428     return get(Opcode).TSFlags & SIInstrFlags::VOP1;
429   }
430 
431   static bool isVOP2(const MachineInstr &MI) {
432     return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
433   }
434 
435   bool isVOP2(uint16_t Opcode) const {
436     return get(Opcode).TSFlags & SIInstrFlags::VOP2;
437   }
438 
439   static bool isVOP3(const MachineInstr &MI) {
440     return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
441   }
442 
443   bool isVOP3(uint16_t Opcode) const {
444     return get(Opcode).TSFlags & SIInstrFlags::VOP3;
445   }
446 
447   static bool isSDWA(const MachineInstr &MI) {
448     return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
449   }
450 
451   bool isSDWA(uint16_t Opcode) const {
452     return get(Opcode).TSFlags & SIInstrFlags::SDWA;
453   }
454 
455   static bool isVOPC(const MachineInstr &MI) {
456     return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
457   }
458 
459   bool isVOPC(uint16_t Opcode) const {
460     return get(Opcode).TSFlags & SIInstrFlags::VOPC;
461   }
462 
463   static bool isMUBUF(const MachineInstr &MI) {
464     return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
465   }
466 
467   bool isMUBUF(uint16_t Opcode) const {
468     return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
469   }
470 
471   static bool isMTBUF(const MachineInstr &MI) {
472     return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
473   }
474 
475   bool isMTBUF(uint16_t Opcode) const {
476     return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
477   }
478 
479   static bool isSMRD(const MachineInstr &MI) {
480     return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
481   }
482 
483   bool isSMRD(uint16_t Opcode) const {
484     return get(Opcode).TSFlags & SIInstrFlags::SMRD;
485   }
486 
487   bool isBufferSMRD(const MachineInstr &MI) const;
488 
489   static bool isDS(const MachineInstr &MI) {
490     return MI.getDesc().TSFlags & SIInstrFlags::DS;
491   }
492 
493   bool isDS(uint16_t Opcode) const {
494     return get(Opcode).TSFlags & SIInstrFlags::DS;
495   }
496 
497   bool isAlwaysGDS(uint16_t Opcode) const;
498 
499   static bool isMIMG(const MachineInstr &MI) {
500     return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
501   }
502 
503   bool isMIMG(uint16_t Opcode) const {
504     return get(Opcode).TSFlags & SIInstrFlags::MIMG;
505   }
506 
507   static bool isGather4(const MachineInstr &MI) {
508     return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
509   }
510 
511   bool isGather4(uint16_t Opcode) const {
512     return get(Opcode).TSFlags & SIInstrFlags::Gather4;
513   }
514 
515   static bool isFLAT(const MachineInstr &MI) {
516     return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
517   }
518 
519   // Is a FLAT encoded instruction which accesses a specific segment,
520   // i.e. global_* or scratch_*.
521   static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
522     auto Flags = MI.getDesc().TSFlags;
523     return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch);
524   }
525 
526   bool isSegmentSpecificFLAT(uint16_t Opcode) const {
527     auto Flags = get(Opcode).TSFlags;
528     return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch);
529   }
530 
531   static bool isFLATGlobal(const MachineInstr &MI) {
532     return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal;
533   }
534 
535   bool isFLATGlobal(uint16_t Opcode) const {
536     return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal;
537   }
538 
539   static bool isFLATScratch(const MachineInstr &MI) {
540     return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch;
541   }
542 
543   bool isFLATScratch(uint16_t Opcode) const {
544     return get(Opcode).TSFlags & SIInstrFlags::FlatScratch;
545   }
546 
547   // Any FLAT encoded instruction, including global_* and scratch_*.
548   bool isFLAT(uint16_t Opcode) const {
549     return get(Opcode).TSFlags & SIInstrFlags::FLAT;
550   }
551 
552   static bool isEXP(const MachineInstr &MI) {
553     return MI.getDesc().TSFlags & SIInstrFlags::EXP;
554   }
555 
556   bool isEXP(uint16_t Opcode) const {
557     return get(Opcode).TSFlags & SIInstrFlags::EXP;
558   }
559 
560   static bool isAtomicNoRet(const MachineInstr &MI) {
561     return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet;
562   }
563 
564   bool isAtomicNoRet(uint16_t Opcode) const {
565     return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet;
566   }
567 
568   static bool isAtomicRet(const MachineInstr &MI) {
569     return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet;
570   }
571 
572   bool isAtomicRet(uint16_t Opcode) const {
573     return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet;
574   }
575 
576   static bool isAtomic(const MachineInstr &MI) {
577     return MI.getDesc().TSFlags & (SIInstrFlags::IsAtomicRet |
578                                    SIInstrFlags::IsAtomicNoRet);
579   }
580 
581   bool isAtomic(uint16_t Opcode) const {
582     return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet |
583                                   SIInstrFlags::IsAtomicNoRet);
584   }
585 
586   static bool isWQM(const MachineInstr &MI) {
587     return MI.getDesc().TSFlags & SIInstrFlags::WQM;
588   }
589 
590   bool isWQM(uint16_t Opcode) const {
591     return get(Opcode).TSFlags & SIInstrFlags::WQM;
592   }
593 
594   static bool isDisableWQM(const MachineInstr &MI) {
595     return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
596   }
597 
598   bool isDisableWQM(uint16_t Opcode) const {
599     return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
600   }
601 
602   static bool isVGPRSpill(const MachineInstr &MI) {
603     return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;
604   }
605 
606   bool isVGPRSpill(uint16_t Opcode) const {
607     return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
608   }
609 
610   static bool isSGPRSpill(const MachineInstr &MI) {
611     return MI.getDesc().TSFlags & SIInstrFlags::SGPRSpill;
612   }
613 
614   bool isSGPRSpill(uint16_t Opcode) const {
615     return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
616   }
617 
618   static bool isDPP(const MachineInstr &MI) {
619     return MI.getDesc().TSFlags & SIInstrFlags::DPP;
620   }
621 
622   bool isDPP(uint16_t Opcode) const {
623     return get(Opcode).TSFlags & SIInstrFlags::DPP;
624   }
625 
626   static bool isTRANS(const MachineInstr &MI) {
627     return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
628   }
629 
630   bool isTRANS(uint16_t Opcode) const {
631     return get(Opcode).TSFlags & SIInstrFlags::TRANS;
632   }
633 
634   static bool isVOP3P(const MachineInstr &MI) {
635     return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
636   }
637 
638   bool isVOP3P(uint16_t Opcode) const {
639     return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
640   }
641 
642   static bool isVINTRP(const MachineInstr &MI) {
643     return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
644   }
645 
646   bool isVINTRP(uint16_t Opcode) const {
647     return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
648   }
649 
650   static bool isMAI(const MachineInstr &MI) {
651     return MI.getDesc().TSFlags & SIInstrFlags::IsMAI;
652   }
653 
654   bool isMAI(uint16_t Opcode) const {
655     return get(Opcode).TSFlags & SIInstrFlags::IsMAI;
656   }
657 
658   static bool isDOT(const MachineInstr &MI) {
659     return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
660   }
661 
662   bool isDOT(uint16_t Opcode) const {
663     return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
664   }
665 
666   static bool isLDSDIR(const MachineInstr &MI) {
667     return MI.getDesc().TSFlags & SIInstrFlags::LDSDIR;
668   }
669 
670   bool isLDSDIR(uint16_t Opcode) const {
671     return get(Opcode).TSFlags & SIInstrFlags::LDSDIR;
672   }
673 
674   static bool isVINTERP(const MachineInstr &MI) {
675     return MI.getDesc().TSFlags & SIInstrFlags::VINTERP;
676   }
677 
678   bool isVINTERP(uint16_t Opcode) const {
679     return get(Opcode).TSFlags & SIInstrFlags::VINTERP;
680   }
681 
682   static bool isScalarUnit(const MachineInstr &MI) {
683     return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
684   }
685 
686   static bool usesVM_CNT(const MachineInstr &MI) {
687     return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
688   }
689 
690   static bool usesLGKM_CNT(const MachineInstr &MI) {
691     return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
692   }
693 
694   static bool sopkIsZext(const MachineInstr &MI) {
695     return MI.getDesc().TSFlags & SIInstrFlags::SOPK_ZEXT;
696   }
697 
698   bool sopkIsZext(uint16_t Opcode) const {
699     return get(Opcode).TSFlags & SIInstrFlags::SOPK_ZEXT;
700   }
701 
702   /// \returns true if this is an s_store_dword* instruction. This is more
703   /// specific than than isSMEM && mayStore.
704   static bool isScalarStore(const MachineInstr &MI) {
705     return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
706   }
707 
708   bool isScalarStore(uint16_t Opcode) const {
709     return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
710   }
711 
712   static bool isFixedSize(const MachineInstr &MI) {
713     return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
714   }
715 
716   bool isFixedSize(uint16_t Opcode) const {
717     return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
718   }
719 
720   static bool hasFPClamp(const MachineInstr &MI) {
721     return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
722   }
723 
724   bool hasFPClamp(uint16_t Opcode) const {
725     return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
726   }
727 
728   static bool hasIntClamp(const MachineInstr &MI) {
729     return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
730   }
731 
732   uint64_t getClampMask(const MachineInstr &MI) const {
733     const uint64_t ClampFlags = SIInstrFlags::FPClamp |
734                                 SIInstrFlags::IntClamp |
735                                 SIInstrFlags::ClampLo |
736                                 SIInstrFlags::ClampHi;
737       return MI.getDesc().TSFlags & ClampFlags;
738   }
739 
740   static bool usesFPDPRounding(const MachineInstr &MI) {
741     return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
742   }
743 
744   bool usesFPDPRounding(uint16_t Opcode) const {
745     return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
746   }
747 
748   static bool isFPAtomic(const MachineInstr &MI) {
749     return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
750   }
751 
752   bool isFPAtomic(uint16_t Opcode) const {
753     return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
754   }
755 
756   bool isVGPRCopy(const MachineInstr &MI) const {
757     assert(MI.isCopy());
758     Register Dest = MI.getOperand(0).getReg();
759     const MachineFunction &MF = *MI.getParent()->getParent();
760     const MachineRegisterInfo &MRI = MF.getRegInfo();
761     return !RI.isSGPRReg(MRI, Dest);
762   }
763 
764   bool hasVGPRUses(const MachineInstr &MI) const {
765     const MachineFunction &MF = *MI.getParent()->getParent();
766     const MachineRegisterInfo &MRI = MF.getRegInfo();
767     return llvm::any_of(MI.explicit_uses(),
768                         [&MRI, this](const MachineOperand &MO) {
769       return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
770   }
771 
772   /// Return true if the instruction modifies the mode register.q
773   static bool modifiesModeRegister(const MachineInstr &MI);
774 
775   /// Whether we must prevent this instruction from executing with EXEC = 0.
776   bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const;
777 
778   /// Returns true if the instruction could potentially depend on the value of
779   /// exec. If false, exec dependencies may safely be ignored.
780   bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
781 
782   bool isInlineConstant(const APInt &Imm) const;
783 
784   bool isInlineConstant(const APFloat &Imm) const {
785     return isInlineConstant(Imm.bitcastToAPInt());
786   }
787 
788   bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
789 
790   bool isInlineConstant(const MachineOperand &MO,
791                         const MCOperandInfo &OpInfo) const {
792     return isInlineConstant(MO, OpInfo.OperandType);
793   }
794 
795   /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
796   /// be an inline immediate.
797   bool isInlineConstant(const MachineInstr &MI,
798                         const MachineOperand &UseMO,
799                         const MachineOperand &DefMO) const {
800     assert(UseMO.getParent() == &MI);
801     int OpIdx = MI.getOperandNo(&UseMO);
802     if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) {
803       return false;
804     }
805 
806     return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]);
807   }
808 
809   /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
810   /// immediate.
811   bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
812     const MachineOperand &MO = MI.getOperand(OpIdx);
813     return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
814   }
815 
816   bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
817                         const MachineOperand &MO) const {
818     if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands)
819       return false;
820 
821     if (MI.isCopy()) {
822       unsigned Size = getOpSize(MI, OpIdx);
823       assert(Size == 8 || Size == 4);
824 
825       uint8_t OpType = (Size == 8) ?
826         AMDGPU::OPERAND_REG_IMM_INT64 : AMDGPU::OPERAND_REG_IMM_INT32;
827       return isInlineConstant(MO, OpType);
828     }
829 
830     return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
831   }
832 
833   bool isInlineConstant(const MachineOperand &MO) const {
834     const MachineInstr *Parent = MO.getParent();
835     return isInlineConstant(*Parent, Parent->getOperandNo(&MO));
836   }
837 
838   bool isLiteralConstant(const MachineOperand &MO,
839                          const MCOperandInfo &OpInfo) const {
840     return MO.isImm() && !isInlineConstant(MO, OpInfo.OperandType);
841   }
842 
843   bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const {
844     const MachineOperand &MO = MI.getOperand(OpIdx);
845     return MO.isImm() && !isInlineConstant(MI, OpIdx);
846   }
847 
848   // Returns true if this operand could potentially require a 32-bit literal
849   // operand, but not necessarily. A FrameIndex for example could resolve to an
850   // inline immediate value that will not require an additional 4-bytes; this
851   // assumes that it will.
852   bool isLiteralConstantLike(const MachineOperand &MO,
853                              const MCOperandInfo &OpInfo) const;
854 
855   bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
856                          const MachineOperand &MO) const;
857 
858   /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
859   /// This function will return false if you pass it a 32-bit instruction.
860   bool hasVALU32BitEncoding(unsigned Opcode) const;
861 
862   /// Returns true if this operand uses the constant bus.
863   bool usesConstantBus(const MachineRegisterInfo &MRI,
864                        const MachineOperand &MO,
865                        const MCOperandInfo &OpInfo) const;
866 
867   /// Return true if this instruction has any modifiers.
868   ///  e.g. src[012]_mod, omod, clamp.
869   bool hasModifiers(unsigned Opcode) const;
870 
871   bool hasModifiersSet(const MachineInstr &MI,
872                        unsigned OpName) const;
873   bool hasAnyModifiersSet(const MachineInstr &MI) const;
874 
875   bool canShrink(const MachineInstr &MI,
876                  const MachineRegisterInfo &MRI) const;
877 
878   MachineInstr *buildShrunkInst(MachineInstr &MI,
879                                 unsigned NewOpcode) const;
880 
881   bool verifyInstruction(const MachineInstr &MI,
882                          StringRef &ErrInfo) const override;
883 
884   unsigned getVALUOp(const MachineInstr &MI) const;
885 
886   /// Return the correct register class for \p OpNo.  For target-specific
887   /// instructions, this will return the register class that has been defined
888   /// in tablegen.  For generic instructions, like REG_SEQUENCE it will return
889   /// the register class of its machine operand.
890   /// to infer the correct register class base on the other operands.
891   const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
892                                            unsigned OpNo) const;
893 
894   /// Return the size in bytes of the operand OpNo on the given
895   // instruction opcode.
896   unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
897     const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
898 
899     if (OpInfo.RegClass == -1) {
900       // If this is an immediate operand, this must be a 32-bit literal.
901       assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
902       return 4;
903     }
904 
905     return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
906   }
907 
908   /// This form should usually be preferred since it handles operands
909   /// with unknown register classes.
910   unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
911     const MachineOperand &MO = MI.getOperand(OpNo);
912     if (MO.isReg()) {
913       if (unsigned SubReg = MO.getSubReg()) {
914         return RI.getSubRegIdxSize(SubReg) / 8;
915       }
916     }
917     return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
918   }
919 
920   /// Legalize the \p OpIndex operand of this instruction by inserting
921   /// a MOV.  For example:
922   /// ADD_I32_e32 VGPR0, 15
923   /// to
924   /// MOV VGPR1, 15
925   /// ADD_I32_e32 VGPR0, VGPR1
926   ///
927   /// If the operand being legalized is a register, then a COPY will be used
928   /// instead of MOV.
929   void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
930 
931   /// Check if \p MO is a legal operand if it was the \p OpIdx Operand
932   /// for \p MI.
933   bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
934                       const MachineOperand *MO = nullptr) const;
935 
936   /// Check if \p MO would be a valid operand for the given operand
937   /// definition \p OpInfo. Note this does not attempt to validate constant bus
938   /// restrictions (e.g. literal constant usage).
939   bool isLegalVSrcOperand(const MachineRegisterInfo &MRI,
940                           const MCOperandInfo &OpInfo,
941                           const MachineOperand &MO) const;
942 
943   /// Check if \p MO (a register operand) is a legal register for the
944   /// given operand description.
945   bool isLegalRegOperand(const MachineRegisterInfo &MRI,
946                          const MCOperandInfo &OpInfo,
947                          const MachineOperand &MO) const;
948 
949   /// Legalize operands in \p MI by either commuting it or inserting a
950   /// copy of src1.
951   void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const;
952 
953   /// Fix operands in \p MI to satisfy constant bus requirements.
954   void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const;
955 
956   /// Copy a value from a VGPR (\p SrcReg) to SGPR.  This function can only
957   /// be used when it is know that the value in SrcReg is same across all
958   /// threads in the wave.
959   /// \returns The SGPR register that \p SrcReg was copied to.
960   Register readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI,
961                               MachineRegisterInfo &MRI) const;
962 
963   void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const;
964   void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const;
965 
966   void legalizeGenericOperand(MachineBasicBlock &InsertMBB,
967                               MachineBasicBlock::iterator I,
968                               const TargetRegisterClass *DstRC,
969                               MachineOperand &Op, MachineRegisterInfo &MRI,
970                               const DebugLoc &DL) const;
971 
972   /// Legalize all operands in this instruction.  This function may create new
973   /// instructions and control-flow around \p MI.  If present, \p MDT is
974   /// updated.
975   /// \returns A new basic block that contains \p MI if new blocks were created.
976   MachineBasicBlock *
977   legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
978 
979   /// Change SADDR form of a FLAT \p Inst to its VADDR form if saddr operand
980   /// was moved to VGPR. \returns true if succeeded.
981   bool moveFlatAddrToVGPR(MachineInstr &Inst) const;
982 
983   /// Replace this instruction's opcode with the equivalent VALU
984   /// opcode.  This function will also move the users of \p MI to the
985   /// VALU if necessary. If present, \p MDT is updated.
986   MachineBasicBlock *moveToVALU(MachineInstr &MI,
987                                 MachineDominatorTree *MDT = nullptr) const;
988 
989   void insertNoop(MachineBasicBlock &MBB,
990                   MachineBasicBlock::iterator MI) const override;
991 
992   void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
993                    unsigned Quantity) const override;
994 
995   void insertReturn(MachineBasicBlock &MBB) const;
996   /// Return the number of wait states that result from executing this
997   /// instruction.
998   static unsigned getNumWaitStates(const MachineInstr &MI);
999 
1000   /// Returns the operand named \p Op.  If \p MI does not have an
1001   /// operand named \c Op, this function returns nullptr.
1002   LLVM_READONLY
1003   MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
1004 
1005   LLVM_READONLY
1006   const MachineOperand *getNamedOperand(const MachineInstr &MI,
1007                                         unsigned OpName) const {
1008     return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
1009   }
1010 
1011   /// Get required immediate operand
1012   int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
1013     int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
1014     return MI.getOperand(Idx).getImm();
1015   }
1016 
1017   uint64_t getDefaultRsrcDataFormat() const;
1018   uint64_t getScratchRsrcWords23() const;
1019 
1020   bool isLowLatencyInstruction(const MachineInstr &MI) const;
1021   bool isHighLatencyDef(int Opc) const override;
1022 
1023   /// Return the descriptor of the target-specific machine instruction
1024   /// that corresponds to the specified pseudo or native opcode.
1025   const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
1026     return get(pseudoToMCOpcode(Opcode));
1027   }
1028 
1029   unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1030   unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1031 
1032   unsigned isLoadFromStackSlot(const MachineInstr &MI,
1033                                int &FrameIndex) const override;
1034   unsigned isStoreToStackSlot(const MachineInstr &MI,
1035                               int &FrameIndex) const override;
1036 
1037   unsigned getInstBundleSize(const MachineInstr &MI) const;
1038   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
1039 
1040   bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
1041 
1042   bool isNonUniformBranchInstr(MachineInstr &Instr) const;
1043 
1044   void convertNonUniformIfRegion(MachineBasicBlock *IfEntry,
1045                                  MachineBasicBlock *IfEnd) const;
1046 
1047   void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry,
1048                                    MachineBasicBlock *LoopEnd) const;
1049 
1050   std::pair<unsigned, unsigned>
1051   decomposeMachineOperandsTargetFlags(unsigned TF) const override;
1052 
1053   ArrayRef<std::pair<int, const char *>>
1054   getSerializableTargetIndices() const override;
1055 
1056   ArrayRef<std::pair<unsigned, const char *>>
1057   getSerializableDirectMachineOperandTargetFlags() const override;
1058 
1059   ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
1060   getSerializableMachineMemOperandTargetFlags() const override;
1061 
1062   ScheduleHazardRecognizer *
1063   CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
1064                                  const ScheduleDAG *DAG) const override;
1065 
1066   ScheduleHazardRecognizer *
1067   CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
1068 
1069   ScheduleHazardRecognizer *
1070   CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
1071                                  const ScheduleDAGMI *DAG) const override;
1072 
1073   bool isBasicBlockPrologue(const MachineInstr &MI) const override;
1074 
1075   MachineInstr *createPHIDestinationCopy(MachineBasicBlock &MBB,
1076                                          MachineBasicBlock::iterator InsPt,
1077                                          const DebugLoc &DL, Register Src,
1078                                          Register Dst) const override;
1079 
1080   MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB,
1081                                     MachineBasicBlock::iterator InsPt,
1082                                     const DebugLoc &DL, Register Src,
1083                                     unsigned SrcSubReg,
1084                                     Register Dst) const override;
1085 
1086   bool isWave32() const;
1087 
1088   /// Return a partially built integer add instruction without carry.
1089   /// Caller must add source operands.
1090   /// For pre-GFX9 it will generate unused carry destination operand.
1091   /// TODO: After GFX9 it should return a no-carry operation.
1092   MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
1093                                     MachineBasicBlock::iterator I,
1094                                     const DebugLoc &DL,
1095                                     Register DestReg) const;
1096 
1097   MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
1098                                     MachineBasicBlock::iterator I,
1099                                     const DebugLoc &DL,
1100                                     Register DestReg,
1101                                     RegScavenger &RS) const;
1102 
1103   static bool isKillTerminator(unsigned Opcode);
1104   const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
1105 
1106   static bool isLegalMUBUFImmOffset(unsigned Imm) {
1107     return isUInt<12>(Imm);
1108   }
1109 
1110   /// Returns if \p Offset is legal for the subtarget as the offset to a FLAT
1111   /// encoded instruction. If \p Signed, this is for an instruction that
1112   /// interprets the offset as signed.
1113   bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
1114                          uint64_t FlatVariant) const;
1115 
1116   /// Split \p COffsetVal into {immediate offset field, remainder offset}
1117   /// values.
1118   std::pair<int64_t, int64_t> splitFlatOffset(int64_t COffsetVal,
1119                                               unsigned AddrSpace,
1120                                               uint64_t FlatVariant) const;
1121 
1122   /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
1123   /// Return -1 if the target-specific opcode for the pseudo instruction does
1124   /// not exist. If Opcode is not a pseudo instruction, this is identity.
1125   int pseudoToMCOpcode(int Opcode) const;
1126 
1127   /// \brief Check if this instruction should only be used by assembler.
1128   /// Return true if this opcode should not be used by codegen.
1129   bool isAsmOnlyOpcode(int MCOp) const;
1130 
1131   const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
1132                                          const TargetRegisterInfo *TRI,
1133                                          const MachineFunction &MF)
1134     const override;
1135 
1136   void fixImplicitOperands(MachineInstr &MI) const;
1137 
1138   MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
1139                                       ArrayRef<unsigned> Ops,
1140                                       MachineBasicBlock::iterator InsertPt,
1141                                       int FrameIndex,
1142                                       LiveIntervals *LIS = nullptr,
1143                                       VirtRegMap *VRM = nullptr) const override;
1144 
1145   unsigned getInstrLatency(const InstrItineraryData *ItinData,
1146                            const MachineInstr &MI,
1147                            unsigned *PredCost = nullptr) const override;
1148 
1149   const MIRFormatter *getMIRFormatter() const override {
1150     if (!Formatter.get())
1151       Formatter = std::make_unique<AMDGPUMIRFormatter>();
1152     return Formatter.get();
1153   }
1154 
1155   static unsigned getDSShaderTypeValue(const MachineFunction &MF);
1156 
1157   const TargetSchedModel &getSchedModel() const { return SchedModel; }
1158 
1159   // Enforce operand's \p OpName even alignment if required by target.
1160   // This is used if an operand is a 32 bit register but needs to be aligned
1161   // regardless.
1162   void enforceOperandRCAlignment(MachineInstr &MI, unsigned OpName) const;
1163 };
1164 
1165 /// \brief Returns true if a reg:subreg pair P has a TRC class
1166 inline bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P,
1167                          const TargetRegisterClass &TRC,
1168                          MachineRegisterInfo &MRI) {
1169   auto *RC = MRI.getRegClass(P.Reg);
1170   if (!P.SubReg)
1171     return RC == &TRC;
1172   auto *TRI = MRI.getTargetRegisterInfo();
1173   return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg);
1174 }
1175 
1176 /// \brief Create RegSubRegPair from a register MachineOperand
1177 inline
1178 TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O) {
1179   assert(O.isReg());
1180   return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
1181 }
1182 
1183 /// \brief Return the SubReg component from REG_SEQUENCE
1184 TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI,
1185                                                     unsigned SubReg);
1186 
1187 /// \brief Return the defining instruction for a given reg:subreg pair
1188 /// skipping copy like instructions and subreg-manipulation pseudos.
1189 /// Following another subreg of a reg:subreg isn't supported.
1190 MachineInstr *getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P,
1191                                MachineRegisterInfo &MRI);
1192 
1193 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1194 /// DefMI and the use at \p UseMI. Should be run on SSA. Currently does not
1195 /// attempt to track between blocks.
1196 bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
1197                                 Register VReg,
1198                                 const MachineInstr &DefMI,
1199                                 const MachineInstr &UseMI);
1200 
1201 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1202 /// DefMI and all its uses. Should be run on SSA. Currently does not attempt to
1203 /// track between blocks.
1204 bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
1205                                    Register VReg,
1206                                    const MachineInstr &DefMI);
1207 
1208 namespace AMDGPU {
1209 
1210   LLVM_READONLY
1211   int getVOPe64(uint16_t Opcode);
1212 
1213   LLVM_READONLY
1214   int getVOPe32(uint16_t Opcode);
1215 
1216   LLVM_READONLY
1217   int getSDWAOp(uint16_t Opcode);
1218 
1219   LLVM_READONLY
1220   int getDPPOp32(uint16_t Opcode);
1221 
1222   LLVM_READONLY
1223   int getBasicFromSDWAOp(uint16_t Opcode);
1224 
1225   LLVM_READONLY
1226   int getCommuteRev(uint16_t Opcode);
1227 
1228   LLVM_READONLY
1229   int getCommuteOrig(uint16_t Opcode);
1230 
1231   LLVM_READONLY
1232   int getAddr64Inst(uint16_t Opcode);
1233 
1234   /// Check if \p Opcode is an Addr64 opcode.
1235   ///
1236   /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
1237   LLVM_READONLY
1238   int getIfAddr64Inst(uint16_t Opcode);
1239 
1240   LLVM_READONLY
1241   int getAtomicNoRetOp(uint16_t Opcode);
1242 
1243   LLVM_READONLY
1244   int getSOPKOp(uint16_t Opcode);
1245 
1246   /// \returns SADDR form of a FLAT Global instruction given an \p Opcode
1247   /// of a VADDR form.
1248   LLVM_READONLY
1249   int getGlobalSaddrOp(uint16_t Opcode);
1250 
1251   /// \returns VADDR form of a FLAT Global instruction given an \p Opcode
1252   /// of a SADDR form.
1253   LLVM_READONLY
1254   int getGlobalVaddrOp(uint16_t Opcode);
1255 
1256   LLVM_READONLY
1257   int getVCMPXNoSDstOp(uint16_t Opcode);
1258 
1259   /// \returns ST form with only immediate offset of a FLAT Scratch instruction
1260   /// given an \p Opcode of an SS (SADDR) form.
1261   LLVM_READONLY
1262   int getFlatScratchInstSTfromSS(uint16_t Opcode);
1263 
1264   /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1265   /// of an SVS (SADDR + VADDR) form.
1266   LLVM_READONLY
1267   int getFlatScratchInstSVfromSVS(uint16_t Opcode);
1268 
1269   /// \returns SS (SADDR) form of a FLAT Scratch instruction given an \p Opcode
1270   /// of an SV (VADDR) form.
1271   LLVM_READONLY
1272   int getFlatScratchInstSSfromSV(uint16_t Opcode);
1273 
1274   /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1275   /// of an SS (SADDR) form.
1276   LLVM_READONLY
1277   int getFlatScratchInstSVfromSS(uint16_t Opcode);
1278 
1279   /// \returns earlyclobber version of a MAC MFMA is exists.
1280   LLVM_READONLY
1281   int getMFMAEarlyClobberOp(uint16_t Opcode);
1282 
1283   /// \returns v_cmpx version of a v_cmp instruction.
1284   LLVM_READONLY
1285   int getVCMPXOpFromVCMP(uint16_t Opcode);
1286 
1287   const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
1288   const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19);
1289   const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);
1290   const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
1291 
1292 } // end namespace AMDGPU
1293 
1294 namespace SI {
1295 namespace KernelInputOffsets {
1296 
1297 /// Offsets in bytes from the start of the input buffer
1298 enum Offsets {
1299   NGROUPS_X = 0,
1300   NGROUPS_Y = 4,
1301   NGROUPS_Z = 8,
1302   GLOBAL_SIZE_X = 12,
1303   GLOBAL_SIZE_Y = 16,
1304   GLOBAL_SIZE_Z = 20,
1305   LOCAL_SIZE_X = 24,
1306   LOCAL_SIZE_Y = 28,
1307   LOCAL_SIZE_Z = 32
1308 };
1309 
1310 } // end namespace KernelInputOffsets
1311 } // end namespace SI
1312 
1313 } // end namespace llvm
1314 
1315 #endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
1316