1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief SI Implementation of TargetInstrInfo. 12 // 13 //===----------------------------------------------------------------------===// 14 15 16 #include "SIInstrInfo.h" 17 #include "AMDGPUTargetMachine.h" 18 #include "SIDefines.h" 19 #include "SIMachineFunctionInfo.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/IR/Function.h" 24 #include "llvm/CodeGen/RegisterScavenging.h" 25 #include "llvm/MC/MCInstrDesc.h" 26 #include "llvm/Support/Debug.h" 27 28 using namespace llvm; 29 30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st) 31 : AMDGPUInstrInfo(st), RI() {} 32 33 //===----------------------------------------------------------------------===// 34 // TargetInstrInfo callbacks 35 //===----------------------------------------------------------------------===// 36 37 static unsigned getNumOperandsNoGlue(SDNode *Node) { 38 unsigned N = Node->getNumOperands(); 39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue) 40 --N; 41 return N; 42 } 43 44 static SDValue findChainOperand(SDNode *Load) { 45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1); 46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node"); 47 return LastOp; 48 } 49 50 /// \brief Returns true if both nodes have the same value for the given 51 /// operand \p Op, or if both nodes do not have this operand. 52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) { 53 unsigned Opc0 = N0->getMachineOpcode(); 54 unsigned Opc1 = N1->getMachineOpcode(); 55 56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName); 57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); 58 59 if (Op0Idx == -1 && Op1Idx == -1) 60 return true; 61 62 63 if ((Op0Idx == -1 && Op1Idx != -1) || 64 (Op1Idx == -1 && Op0Idx != -1)) 65 return false; 66 67 // getNamedOperandIdx returns the index for the MachineInstr's operands, 68 // which includes the result as the first operand. We are indexing into the 69 // MachineSDNode's operands, so we need to skip the result operand to get 70 // the real index. 71 --Op0Idx; 72 --Op1Idx; 73 74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx); 75 } 76 77 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, 78 AliasAnalysis *AA) const { 79 // TODO: The generic check fails for VALU instructions that should be 80 // rematerializable due to implicit reads of exec. We really want all of the 81 // generic logic for this except for this. 82 switch (MI->getOpcode()) { 83 case AMDGPU::V_MOV_B32_e32: 84 case AMDGPU::V_MOV_B32_e64: 85 case AMDGPU::V_MOV_B64_PSEUDO: 86 return true; 87 default: 88 return false; 89 } 90 } 91 92 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, 93 int64_t &Offset0, 94 int64_t &Offset1) const { 95 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode()) 96 return false; 97 98 unsigned Opc0 = Load0->getMachineOpcode(); 99 unsigned Opc1 = Load1->getMachineOpcode(); 100 101 // Make sure both are actually loads. 102 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad()) 103 return false; 104 105 if (isDS(Opc0) && isDS(Opc1)) { 106 107 // FIXME: Handle this case: 108 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1)) 109 return false; 110 111 // Check base reg. 112 if (Load0->getOperand(1) != Load1->getOperand(1)) 113 return false; 114 115 // Check chain. 116 if (findChainOperand(Load0) != findChainOperand(Load1)) 117 return false; 118 119 // Skip read2 / write2 variants for simplicity. 120 // TODO: We should report true if the used offsets are adjacent (excluded 121 // st64 versions). 122 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 || 123 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1) 124 return false; 125 126 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue(); 127 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue(); 128 return true; 129 } 130 131 if (isSMRD(Opc0) && isSMRD(Opc1)) { 132 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1)); 133 134 // Check base reg. 135 if (Load0->getOperand(0) != Load1->getOperand(0)) 136 return false; 137 138 const ConstantSDNode *Load0Offset = 139 dyn_cast<ConstantSDNode>(Load0->getOperand(1)); 140 const ConstantSDNode *Load1Offset = 141 dyn_cast<ConstantSDNode>(Load1->getOperand(1)); 142 143 if (!Load0Offset || !Load1Offset) 144 return false; 145 146 // Check chain. 147 if (findChainOperand(Load0) != findChainOperand(Load1)) 148 return false; 149 150 Offset0 = Load0Offset->getZExtValue(); 151 Offset1 = Load1Offset->getZExtValue(); 152 return true; 153 } 154 155 // MUBUF and MTBUF can access the same addresses. 156 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) { 157 158 // MUBUF and MTBUF have vaddr at different indices. 159 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) || 160 findChainOperand(Load0) != findChainOperand(Load1) || 161 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) || 162 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc)) 163 return false; 164 165 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset); 166 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset); 167 168 if (OffIdx0 == -1 || OffIdx1 == -1) 169 return false; 170 171 // getNamedOperandIdx returns the index for MachineInstrs. Since they 172 // inlcude the output in the operand list, but SDNodes don't, we need to 173 // subtract the index by one. 174 --OffIdx0; 175 --OffIdx1; 176 177 SDValue Off0 = Load0->getOperand(OffIdx0); 178 SDValue Off1 = Load1->getOperand(OffIdx1); 179 180 // The offset might be a FrameIndexSDNode. 181 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1)) 182 return false; 183 184 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue(); 185 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue(); 186 return true; 187 } 188 189 return false; 190 } 191 192 static bool isStride64(unsigned Opc) { 193 switch (Opc) { 194 case AMDGPU::DS_READ2ST64_B32: 195 case AMDGPU::DS_READ2ST64_B64: 196 case AMDGPU::DS_WRITE2ST64_B32: 197 case AMDGPU::DS_WRITE2ST64_B64: 198 return true; 199 default: 200 return false; 201 } 202 } 203 204 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg, 205 unsigned &Offset, 206 const TargetRegisterInfo *TRI) const { 207 unsigned Opc = LdSt->getOpcode(); 208 if (isDS(Opc)) { 209 const MachineOperand *OffsetImm = getNamedOperand(*LdSt, 210 AMDGPU::OpName::offset); 211 if (OffsetImm) { 212 // Normal, single offset LDS instruction. 213 const MachineOperand *AddrReg = getNamedOperand(*LdSt, 214 AMDGPU::OpName::addr); 215 216 BaseReg = AddrReg->getReg(); 217 Offset = OffsetImm->getImm(); 218 return true; 219 } 220 221 // The 2 offset instructions use offset0 and offset1 instead. We can treat 222 // these as a load with a single offset if the 2 offsets are consecutive. We 223 // will use this for some partially aligned loads. 224 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt, 225 AMDGPU::OpName::offset0); 226 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt, 227 AMDGPU::OpName::offset1); 228 229 uint8_t Offset0 = Offset0Imm->getImm(); 230 uint8_t Offset1 = Offset1Imm->getImm(); 231 232 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) { 233 // Each of these offsets is in element sized units, so we need to convert 234 // to bytes of the individual reads. 235 236 unsigned EltSize; 237 if (LdSt->mayLoad()) 238 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2; 239 else { 240 assert(LdSt->mayStore()); 241 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0); 242 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize(); 243 } 244 245 if (isStride64(Opc)) 246 EltSize *= 64; 247 248 const MachineOperand *AddrReg = getNamedOperand(*LdSt, 249 AMDGPU::OpName::addr); 250 BaseReg = AddrReg->getReg(); 251 Offset = EltSize * Offset0; 252 return true; 253 } 254 255 return false; 256 } 257 258 if (isMUBUF(Opc) || isMTBUF(Opc)) { 259 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1) 260 return false; 261 262 const MachineOperand *AddrReg = getNamedOperand(*LdSt, 263 AMDGPU::OpName::vaddr); 264 if (!AddrReg) 265 return false; 266 267 const MachineOperand *OffsetImm = getNamedOperand(*LdSt, 268 AMDGPU::OpName::offset); 269 BaseReg = AddrReg->getReg(); 270 Offset = OffsetImm->getImm(); 271 return true; 272 } 273 274 if (isSMRD(Opc)) { 275 const MachineOperand *OffsetImm = getNamedOperand(*LdSt, 276 AMDGPU::OpName::offset); 277 if (!OffsetImm) 278 return false; 279 280 const MachineOperand *SBaseReg = getNamedOperand(*LdSt, 281 AMDGPU::OpName::sbase); 282 BaseReg = SBaseReg->getReg(); 283 Offset = OffsetImm->getImm(); 284 return true; 285 } 286 287 return false; 288 } 289 290 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt, 291 MachineInstr *SecondLdSt, 292 unsigned NumLoads) const { 293 unsigned Opc0 = FirstLdSt->getOpcode(); 294 unsigned Opc1 = SecondLdSt->getOpcode(); 295 296 // TODO: This needs finer tuning 297 if (NumLoads > 4) 298 return false; 299 300 if (isDS(Opc0) && isDS(Opc1)) 301 return true; 302 303 if (isSMRD(Opc0) && isSMRD(Opc1)) 304 return true; 305 306 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) 307 return true; 308 309 return false; 310 } 311 312 void 313 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 314 MachineBasicBlock::iterator MI, DebugLoc DL, 315 unsigned DestReg, unsigned SrcReg, 316 bool KillSrc) const { 317 318 // If we are trying to copy to or from SCC, there is a bug somewhere else in 319 // the backend. While it may be theoretically possible to do this, it should 320 // never be necessary. 321 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC); 322 323 static const int16_t Sub0_15[] = { 324 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 325 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 326 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11, 327 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0 328 }; 329 330 static const int16_t Sub0_7[] = { 331 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 332 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0 333 }; 334 335 static const int16_t Sub0_3[] = { 336 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0 337 }; 338 339 static const int16_t Sub0_2[] = { 340 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0 341 }; 342 343 static const int16_t Sub0_1[] = { 344 AMDGPU::sub0, AMDGPU::sub1, 0 345 }; 346 347 unsigned Opcode; 348 const int16_t *SubIndices; 349 350 if (AMDGPU::SReg_32RegClass.contains(DestReg)) { 351 assert(AMDGPU::SReg_32RegClass.contains(SrcReg)); 352 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg) 353 .addReg(SrcReg, getKillRegState(KillSrc)); 354 return; 355 356 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) { 357 if (DestReg == AMDGPU::VCC) { 358 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) { 359 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC) 360 .addReg(SrcReg, getKillRegState(KillSrc)); 361 } else { 362 // FIXME: Hack until VReg_1 removed. 363 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg)); 364 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32)) 365 .addImm(0) 366 .addReg(SrcReg, getKillRegState(KillSrc)); 367 } 368 369 return; 370 } 371 372 assert(AMDGPU::SReg_64RegClass.contains(SrcReg)); 373 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg) 374 .addReg(SrcReg, getKillRegState(KillSrc)); 375 return; 376 377 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) { 378 assert(AMDGPU::SReg_128RegClass.contains(SrcReg)); 379 Opcode = AMDGPU::S_MOV_B32; 380 SubIndices = Sub0_3; 381 382 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) { 383 assert(AMDGPU::SReg_256RegClass.contains(SrcReg)); 384 Opcode = AMDGPU::S_MOV_B32; 385 SubIndices = Sub0_7; 386 387 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) { 388 assert(AMDGPU::SReg_512RegClass.contains(SrcReg)); 389 Opcode = AMDGPU::S_MOV_B32; 390 SubIndices = Sub0_15; 391 392 } else if (AMDGPU::VGPR_32RegClass.contains(DestReg)) { 393 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) || 394 AMDGPU::SReg_32RegClass.contains(SrcReg)); 395 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) 396 .addReg(SrcReg, getKillRegState(KillSrc)); 397 return; 398 399 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) { 400 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) || 401 AMDGPU::SReg_64RegClass.contains(SrcReg)); 402 Opcode = AMDGPU::V_MOV_B32_e32; 403 SubIndices = Sub0_1; 404 405 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) { 406 assert(AMDGPU::VReg_96RegClass.contains(SrcReg)); 407 Opcode = AMDGPU::V_MOV_B32_e32; 408 SubIndices = Sub0_2; 409 410 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) { 411 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) || 412 AMDGPU::SReg_128RegClass.contains(SrcReg)); 413 Opcode = AMDGPU::V_MOV_B32_e32; 414 SubIndices = Sub0_3; 415 416 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) { 417 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) || 418 AMDGPU::SReg_256RegClass.contains(SrcReg)); 419 Opcode = AMDGPU::V_MOV_B32_e32; 420 SubIndices = Sub0_7; 421 422 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) { 423 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) || 424 AMDGPU::SReg_512RegClass.contains(SrcReg)); 425 Opcode = AMDGPU::V_MOV_B32_e32; 426 SubIndices = Sub0_15; 427 428 } else { 429 llvm_unreachable("Can't copy register!"); 430 } 431 432 while (unsigned SubIdx = *SubIndices++) { 433 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL, 434 get(Opcode), RI.getSubReg(DestReg, SubIdx)); 435 436 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc)); 437 438 if (*SubIndices) 439 Builder.addReg(DestReg, RegState::Define | RegState::Implicit); 440 } 441 } 442 443 int SIInstrInfo::commuteOpcode(const MachineInstr &MI) const { 444 const unsigned Opcode = MI.getOpcode(); 445 446 int NewOpc; 447 448 // Try to map original to commuted opcode 449 NewOpc = AMDGPU::getCommuteRev(Opcode); 450 if (NewOpc != -1) 451 // Check if the commuted (REV) opcode exists on the target. 452 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1; 453 454 // Try to map commuted to original opcode 455 NewOpc = AMDGPU::getCommuteOrig(Opcode); 456 if (NewOpc != -1) 457 // Check if the original (non-REV) opcode exists on the target. 458 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1; 459 460 return Opcode; 461 } 462 463 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const { 464 465 if (DstRC->getSize() == 4) { 466 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; 467 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) { 468 return AMDGPU::S_MOV_B64; 469 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) { 470 return AMDGPU::V_MOV_B64_PSEUDO; 471 } 472 return AMDGPU::COPY; 473 } 474 475 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 476 MachineBasicBlock::iterator MI, 477 unsigned SrcReg, bool isKill, 478 int FrameIndex, 479 const TargetRegisterClass *RC, 480 const TargetRegisterInfo *TRI) const { 481 MachineFunction *MF = MBB.getParent(); 482 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>(); 483 MachineFrameInfo *FrameInfo = MF->getFrameInfo(); 484 DebugLoc DL = MBB.findDebugLoc(MI); 485 int Opcode = -1; 486 487 if (RI.isSGPRClass(RC)) { 488 // We are only allowed to create one new instruction when spilling 489 // registers, so we need to use pseudo instruction for spilling 490 // SGPRs. 491 switch (RC->getSize() * 8) { 492 case 32: Opcode = AMDGPU::SI_SPILL_S32_SAVE; break; 493 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break; 494 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break; 495 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break; 496 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break; 497 } 498 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) { 499 MFI->setHasSpilledVGPRs(); 500 501 switch(RC->getSize() * 8) { 502 case 32: Opcode = AMDGPU::SI_SPILL_V32_SAVE; break; 503 case 64: Opcode = AMDGPU::SI_SPILL_V64_SAVE; break; 504 case 96: Opcode = AMDGPU::SI_SPILL_V96_SAVE; break; 505 case 128: Opcode = AMDGPU::SI_SPILL_V128_SAVE; break; 506 case 256: Opcode = AMDGPU::SI_SPILL_V256_SAVE; break; 507 case 512: Opcode = AMDGPU::SI_SPILL_V512_SAVE; break; 508 } 509 } 510 511 if (Opcode != -1) { 512 MachinePointerInfo PtrInfo 513 = MachinePointerInfo::getFixedStack(*MF, FrameIndex); 514 unsigned Size = FrameInfo->getObjectSize(FrameIndex); 515 unsigned Align = FrameInfo->getObjectAlignment(FrameIndex); 516 MachineMemOperand *MMO 517 = MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore, 518 Size, Align); 519 520 FrameInfo->setObjectAlignment(FrameIndex, 4); 521 BuildMI(MBB, MI, DL, get(Opcode)) 522 .addReg(SrcReg) 523 .addFrameIndex(FrameIndex) 524 // Place-holder registers, these will be filled in by 525 // SIPrepareScratchRegs. 526 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef) 527 .addReg(AMDGPU::SGPR0, RegState::Undef) 528 .addMemOperand(MMO); 529 } else { 530 LLVMContext &Ctx = MF->getFunction()->getContext(); 531 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to" 532 " spill register"); 533 BuildMI(MBB, MI, DL, get(AMDGPU::KILL)) 534 .addReg(SrcReg); 535 } 536 } 537 538 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 539 MachineBasicBlock::iterator MI, 540 unsigned DestReg, int FrameIndex, 541 const TargetRegisterClass *RC, 542 const TargetRegisterInfo *TRI) const { 543 MachineFunction *MF = MBB.getParent(); 544 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>(); 545 MachineFrameInfo *FrameInfo = MF->getFrameInfo(); 546 DebugLoc DL = MBB.findDebugLoc(MI); 547 int Opcode = -1; 548 549 if (RI.isSGPRClass(RC)){ 550 switch(RC->getSize() * 8) { 551 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break; 552 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break; 553 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break; 554 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break; 555 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break; 556 } 557 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) { 558 switch(RC->getSize() * 8) { 559 case 32: Opcode = AMDGPU::SI_SPILL_V32_RESTORE; break; 560 case 64: Opcode = AMDGPU::SI_SPILL_V64_RESTORE; break; 561 case 96: Opcode = AMDGPU::SI_SPILL_V96_RESTORE; break; 562 case 128: Opcode = AMDGPU::SI_SPILL_V128_RESTORE; break; 563 case 256: Opcode = AMDGPU::SI_SPILL_V256_RESTORE; break; 564 case 512: Opcode = AMDGPU::SI_SPILL_V512_RESTORE; break; 565 } 566 } 567 568 if (Opcode != -1) { 569 unsigned Align = 4; 570 FrameInfo->setObjectAlignment(FrameIndex, Align); 571 unsigned Size = FrameInfo->getObjectSize(FrameIndex); 572 573 MachinePointerInfo PtrInfo 574 = MachinePointerInfo::getFixedStack(*MF, FrameIndex); 575 MachineMemOperand *MMO = MF->getMachineMemOperand( 576 PtrInfo, MachineMemOperand::MOLoad, Size, Align); 577 578 BuildMI(MBB, MI, DL, get(Opcode), DestReg) 579 .addFrameIndex(FrameIndex) 580 // Place-holder registers, these will be filled in by 581 // SIPrepareScratchRegs. 582 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef) 583 .addReg(AMDGPU::SGPR0, RegState::Undef) 584 .addMemOperand(MMO); 585 } else { 586 LLVMContext &Ctx = MF->getFunction()->getContext(); 587 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to" 588 " restore register"); 589 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg); 590 } 591 } 592 593 /// \param @Offset Offset in bytes of the FrameIndex being spilled 594 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB, 595 MachineBasicBlock::iterator MI, 596 RegScavenger *RS, unsigned TmpReg, 597 unsigned FrameOffset, 598 unsigned Size) const { 599 MachineFunction *MF = MBB.getParent(); 600 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>(); 601 const AMDGPUSubtarget &ST = MF->getSubtarget<AMDGPUSubtarget>(); 602 const SIRegisterInfo *TRI = 603 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo()); 604 DebugLoc DL = MBB.findDebugLoc(MI); 605 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF); 606 unsigned WavefrontSize = ST.getWavefrontSize(); 607 608 unsigned TIDReg = MFI->getTIDReg(); 609 if (!MFI->hasCalculatedTID()) { 610 MachineBasicBlock &Entry = MBB.getParent()->front(); 611 MachineBasicBlock::iterator Insert = Entry.front(); 612 DebugLoc DL = Insert->getDebugLoc(); 613 614 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass); 615 if (TIDReg == AMDGPU::NoRegister) 616 return TIDReg; 617 618 619 if (MFI->getShaderType() == ShaderType::COMPUTE && 620 WorkGroupSize > WavefrontSize) { 621 622 unsigned TIDIGXReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_X); 623 unsigned TIDIGYReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Y); 624 unsigned TIDIGZReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Z); 625 unsigned InputPtrReg = 626 TRI->getPreloadedValue(*MF, SIRegisterInfo::INPUT_PTR); 627 for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) { 628 if (!Entry.isLiveIn(Reg)) 629 Entry.addLiveIn(Reg); 630 } 631 632 RS->enterBasicBlock(&Entry); 633 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0); 634 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0); 635 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0) 636 .addReg(InputPtrReg) 637 .addImm(SI::KernelInputOffsets::NGROUPS_Z); 638 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1) 639 .addReg(InputPtrReg) 640 .addImm(SI::KernelInputOffsets::NGROUPS_Y); 641 642 // NGROUPS.X * NGROUPS.Y 643 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1) 644 .addReg(STmp1) 645 .addReg(STmp0); 646 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X 647 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg) 648 .addReg(STmp1) 649 .addReg(TIDIGXReg); 650 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X) 651 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg) 652 .addReg(STmp0) 653 .addReg(TIDIGYReg) 654 .addReg(TIDReg); 655 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z 656 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg) 657 .addReg(TIDReg) 658 .addReg(TIDIGZReg); 659 } else { 660 // Get the wave id 661 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64), 662 TIDReg) 663 .addImm(-1) 664 .addImm(0); 665 666 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64), 667 TIDReg) 668 .addImm(-1) 669 .addReg(TIDReg); 670 } 671 672 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32), 673 TIDReg) 674 .addImm(2) 675 .addReg(TIDReg); 676 MFI->setTIDReg(TIDReg); 677 } 678 679 // Add FrameIndex to LDS offset 680 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize); 681 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg) 682 .addImm(LDSOffset) 683 .addReg(TIDReg); 684 685 return TmpReg; 686 } 687 688 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI, 689 int Count) const { 690 while (Count > 0) { 691 int Arg; 692 if (Count >= 8) 693 Arg = 7; 694 else 695 Arg = Count - 1; 696 Count -= 8; 697 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP)) 698 .addImm(Arg); 699 } 700 } 701 702 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 703 MachineBasicBlock &MBB = *MI->getParent(); 704 DebugLoc DL = MBB.findDebugLoc(MI); 705 switch (MI->getOpcode()) { 706 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI); 707 708 case AMDGPU::SI_CONSTDATA_PTR: { 709 unsigned Reg = MI->getOperand(0).getReg(); 710 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0); 711 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1); 712 713 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg); 714 715 // Add 32-bit offset from this instruction to the start of the constant data. 716 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo) 717 .addReg(RegLo) 718 .addTargetIndex(AMDGPU::TI_CONSTDATA_START) 719 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit); 720 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi) 721 .addReg(RegHi) 722 .addImm(0) 723 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit) 724 .addReg(AMDGPU::SCC, RegState::Implicit); 725 MI->eraseFromParent(); 726 break; 727 } 728 case AMDGPU::SGPR_USE: 729 // This is just a placeholder for register allocation. 730 MI->eraseFromParent(); 731 break; 732 733 case AMDGPU::V_MOV_B64_PSEUDO: { 734 unsigned Dst = MI->getOperand(0).getReg(); 735 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0); 736 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1); 737 738 const MachineOperand &SrcOp = MI->getOperand(1); 739 // FIXME: Will this work for 64-bit floating point immediates? 740 assert(!SrcOp.isFPImm()); 741 if (SrcOp.isImm()) { 742 APInt Imm(64, SrcOp.getImm()); 743 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) 744 .addImm(Imm.getLoBits(32).getZExtValue()) 745 .addReg(Dst, RegState::Implicit); 746 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) 747 .addImm(Imm.getHiBits(32).getZExtValue()) 748 .addReg(Dst, RegState::Implicit); 749 } else { 750 assert(SrcOp.isReg()); 751 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) 752 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) 753 .addReg(Dst, RegState::Implicit); 754 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) 755 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1)) 756 .addReg(Dst, RegState::Implicit); 757 } 758 MI->eraseFromParent(); 759 break; 760 } 761 762 case AMDGPU::V_CNDMASK_B64_PSEUDO: { 763 unsigned Dst = MI->getOperand(0).getReg(); 764 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0); 765 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1); 766 unsigned Src0 = MI->getOperand(1).getReg(); 767 unsigned Src1 = MI->getOperand(2).getReg(); 768 const MachineOperand &SrcCond = MI->getOperand(3); 769 770 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstLo) 771 .addReg(RI.getSubReg(Src0, AMDGPU::sub0)) 772 .addReg(RI.getSubReg(Src1, AMDGPU::sub0)) 773 .addOperand(SrcCond); 774 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstHi) 775 .addReg(RI.getSubReg(Src0, AMDGPU::sub1)) 776 .addReg(RI.getSubReg(Src1, AMDGPU::sub1)) 777 .addOperand(SrcCond); 778 MI->eraseFromParent(); 779 break; 780 } 781 } 782 return true; 783 } 784 785 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI, 786 bool NewMI) const { 787 788 if (MI->getNumOperands() < 3) 789 return nullptr; 790 791 int CommutedOpcode = commuteOpcode(*MI); 792 if (CommutedOpcode == -1) 793 return nullptr; 794 795 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), 796 AMDGPU::OpName::src0); 797 assert(Src0Idx != -1 && "Should always have src0 operand"); 798 799 MachineOperand &Src0 = MI->getOperand(Src0Idx); 800 if (!Src0.isReg()) 801 return nullptr; 802 803 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), 804 AMDGPU::OpName::src1); 805 if (Src1Idx == -1) 806 return nullptr; 807 808 MachineOperand &Src1 = MI->getOperand(Src1Idx); 809 810 // Make sure it's legal to commute operands for VOP2. 811 if (isVOP2(MI->getOpcode()) && 812 (!isOperandLegal(MI, Src0Idx, &Src1) || 813 !isOperandLegal(MI, Src1Idx, &Src0))) { 814 return nullptr; 815 } 816 817 if (!Src1.isReg()) { 818 // Allow commuting instructions with Imm operands. 819 if (NewMI || !Src1.isImm() || 820 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) { 821 return nullptr; 822 } 823 824 // Be sure to copy the source modifiers to the right place. 825 if (MachineOperand *Src0Mods 826 = getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) { 827 MachineOperand *Src1Mods 828 = getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers); 829 830 int Src0ModsVal = Src0Mods->getImm(); 831 if (!Src1Mods && Src0ModsVal != 0) 832 return nullptr; 833 834 // XXX - This assert might be a lie. It might be useful to have a neg 835 // modifier with 0.0. 836 int Src1ModsVal = Src1Mods->getImm(); 837 assert((Src1ModsVal == 0) && "Not expecting modifiers with immediates"); 838 839 Src1Mods->setImm(Src0ModsVal); 840 Src0Mods->setImm(Src1ModsVal); 841 } 842 843 unsigned Reg = Src0.getReg(); 844 unsigned SubReg = Src0.getSubReg(); 845 if (Src1.isImm()) 846 Src0.ChangeToImmediate(Src1.getImm()); 847 else 848 llvm_unreachable("Should only have immediates"); 849 850 Src1.ChangeToRegister(Reg, false); 851 Src1.setSubReg(SubReg); 852 } else { 853 MI = TargetInstrInfo::commuteInstruction(MI, NewMI); 854 } 855 856 if (MI) 857 MI->setDesc(get(CommutedOpcode)); 858 859 return MI; 860 } 861 862 // This needs to be implemented because the source modifiers may be inserted 863 // between the true commutable operands, and the base 864 // TargetInstrInfo::commuteInstruction uses it. 865 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI, 866 unsigned &SrcOpIdx1, 867 unsigned &SrcOpIdx2) const { 868 const MCInstrDesc &MCID = MI->getDesc(); 869 if (!MCID.isCommutable()) 870 return false; 871 872 unsigned Opc = MI->getOpcode(); 873 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); 874 if (Src0Idx == -1) 875 return false; 876 877 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on 878 // immediate. 879 if (!MI->getOperand(Src0Idx).isReg()) 880 return false; 881 882 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1); 883 if (Src1Idx == -1) 884 return false; 885 886 if (!MI->getOperand(Src1Idx).isReg()) 887 return false; 888 889 // If any source modifiers are set, the generic instruction commuting won't 890 // understand how to copy the source modifiers. 891 if (hasModifiersSet(*MI, AMDGPU::OpName::src0_modifiers) || 892 hasModifiersSet(*MI, AMDGPU::OpName::src1_modifiers)) 893 return false; 894 895 SrcOpIdx1 = Src0Idx; 896 SrcOpIdx2 = Src1Idx; 897 return true; 898 } 899 900 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB, 901 MachineBasicBlock::iterator I, 902 unsigned DstReg, 903 unsigned SrcReg) const { 904 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32), 905 DstReg) .addReg(SrcReg); 906 } 907 908 bool SIInstrInfo::isMov(unsigned Opcode) const { 909 switch(Opcode) { 910 default: return false; 911 case AMDGPU::S_MOV_B32: 912 case AMDGPU::S_MOV_B64: 913 case AMDGPU::V_MOV_B32_e32: 914 case AMDGPU::V_MOV_B32_e64: 915 return true; 916 } 917 } 918 919 static void removeModOperands(MachineInstr &MI) { 920 unsigned Opc = MI.getOpcode(); 921 int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc, 922 AMDGPU::OpName::src0_modifiers); 923 int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc, 924 AMDGPU::OpName::src1_modifiers); 925 int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc, 926 AMDGPU::OpName::src2_modifiers); 927 928 MI.RemoveOperand(Src2ModIdx); 929 MI.RemoveOperand(Src1ModIdx); 930 MI.RemoveOperand(Src0ModIdx); 931 } 932 933 bool SIInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 934 unsigned Reg, MachineRegisterInfo *MRI) const { 935 if (!MRI->hasOneNonDBGUse(Reg)) 936 return false; 937 938 unsigned Opc = UseMI->getOpcode(); 939 if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64) { 940 // Don't fold if we are using source modifiers. The new VOP2 instructions 941 // don't have them. 942 if (hasModifiersSet(*UseMI, AMDGPU::OpName::src0_modifiers) || 943 hasModifiersSet(*UseMI, AMDGPU::OpName::src1_modifiers) || 944 hasModifiersSet(*UseMI, AMDGPU::OpName::src2_modifiers)) { 945 return false; 946 } 947 948 MachineOperand *Src0 = getNamedOperand(*UseMI, AMDGPU::OpName::src0); 949 MachineOperand *Src1 = getNamedOperand(*UseMI, AMDGPU::OpName::src1); 950 MachineOperand *Src2 = getNamedOperand(*UseMI, AMDGPU::OpName::src2); 951 952 // Multiplied part is the constant: Use v_madmk_f32 953 // We should only expect these to be on src0 due to canonicalizations. 954 if (Src0->isReg() && Src0->getReg() == Reg) { 955 if (!Src1->isReg() || 956 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))) 957 return false; 958 959 if (!Src2->isReg() || 960 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))) 961 return false; 962 963 // We need to do some weird looking operand shuffling since the madmk 964 // operands are out of the normal expected order with the multiplied 965 // constant as the last operand. 966 // 967 // v_mad_f32 src0, src1, src2 -> v_madmk_f32 src0 * src2K + src1 968 // src0 -> src2 K 969 // src1 -> src0 970 // src2 -> src1 971 972 const int64_t Imm = DefMI->getOperand(1).getImm(); 973 974 // FIXME: This would be a lot easier if we could return a new instruction 975 // instead of having to modify in place. 976 977 // Remove these first since they are at the end. 978 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc, 979 AMDGPU::OpName::omod)); 980 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc, 981 AMDGPU::OpName::clamp)); 982 983 unsigned Src1Reg = Src1->getReg(); 984 unsigned Src1SubReg = Src1->getSubReg(); 985 unsigned Src2Reg = Src2->getReg(); 986 unsigned Src2SubReg = Src2->getSubReg(); 987 Src0->setReg(Src1Reg); 988 Src0->setSubReg(Src1SubReg); 989 Src0->setIsKill(Src1->isKill()); 990 991 Src1->setReg(Src2Reg); 992 Src1->setSubReg(Src2SubReg); 993 Src1->setIsKill(Src2->isKill()); 994 995 if (Opc == AMDGPU::V_MAC_F32_e64) { 996 UseMI->untieRegOperand( 997 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)); 998 } 999 1000 Src2->ChangeToImmediate(Imm); 1001 1002 removeModOperands(*UseMI); 1003 UseMI->setDesc(get(AMDGPU::V_MADMK_F32)); 1004 1005 bool DeleteDef = MRI->hasOneNonDBGUse(Reg); 1006 if (DeleteDef) 1007 DefMI->eraseFromParent(); 1008 1009 return true; 1010 } 1011 1012 // Added part is the constant: Use v_madak_f32 1013 if (Src2->isReg() && Src2->getReg() == Reg) { 1014 // Not allowed to use constant bus for another operand. 1015 // We can however allow an inline immediate as src0. 1016 if (!Src0->isImm() && 1017 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))) 1018 return false; 1019 1020 if (!Src1->isReg() || 1021 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))) 1022 return false; 1023 1024 const int64_t Imm = DefMI->getOperand(1).getImm(); 1025 1026 // FIXME: This would be a lot easier if we could return a new instruction 1027 // instead of having to modify in place. 1028 1029 // Remove these first since they are at the end. 1030 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc, 1031 AMDGPU::OpName::omod)); 1032 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc, 1033 AMDGPU::OpName::clamp)); 1034 1035 if (Opc == AMDGPU::V_MAC_F32_e64) { 1036 UseMI->untieRegOperand( 1037 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)); 1038 } 1039 1040 // ChangingToImmediate adds Src2 back to the instruction. 1041 Src2->ChangeToImmediate(Imm); 1042 1043 // These come before src2. 1044 removeModOperands(*UseMI); 1045 UseMI->setDesc(get(AMDGPU::V_MADAK_F32)); 1046 1047 bool DeleteDef = MRI->hasOneNonDBGUse(Reg); 1048 if (DeleteDef) 1049 DefMI->eraseFromParent(); 1050 1051 return true; 1052 } 1053 } 1054 1055 return false; 1056 } 1057 1058 static bool offsetsDoNotOverlap(int WidthA, int OffsetA, 1059 int WidthB, int OffsetB) { 1060 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB; 1061 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA; 1062 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB; 1063 return LowOffset + LowWidth <= HighOffset; 1064 } 1065 1066 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa, 1067 MachineInstr *MIb) const { 1068 unsigned BaseReg0, Offset0; 1069 unsigned BaseReg1, Offset1; 1070 1071 if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) && 1072 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) { 1073 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() && 1074 "read2 / write2 not expected here yet"); 1075 unsigned Width0 = (*MIa->memoperands_begin())->getSize(); 1076 unsigned Width1 = (*MIb->memoperands_begin())->getSize(); 1077 if (BaseReg0 == BaseReg1 && 1078 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) { 1079 return true; 1080 } 1081 } 1082 1083 return false; 1084 } 1085 1086 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa, 1087 MachineInstr *MIb, 1088 AliasAnalysis *AA) const { 1089 unsigned Opc0 = MIa->getOpcode(); 1090 unsigned Opc1 = MIb->getOpcode(); 1091 1092 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) && 1093 "MIa must load from or modify a memory location"); 1094 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) && 1095 "MIb must load from or modify a memory location"); 1096 1097 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects()) 1098 return false; 1099 1100 // XXX - Can we relax this between address spaces? 1101 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef()) 1102 return false; 1103 1104 // TODO: Should we check the address space from the MachineMemOperand? That 1105 // would allow us to distinguish objects we know don't alias based on the 1106 // underlying address space, even if it was lowered to a different one, 1107 // e.g. private accesses lowered to use MUBUF instructions on a scratch 1108 // buffer. 1109 if (isDS(Opc0)) { 1110 if (isDS(Opc1)) 1111 return checkInstOffsetsDoNotOverlap(MIa, MIb); 1112 1113 return !isFLAT(Opc1); 1114 } 1115 1116 if (isMUBUF(Opc0) || isMTBUF(Opc0)) { 1117 if (isMUBUF(Opc1) || isMTBUF(Opc1)) 1118 return checkInstOffsetsDoNotOverlap(MIa, MIb); 1119 1120 return !isFLAT(Opc1) && !isSMRD(Opc1); 1121 } 1122 1123 if (isSMRD(Opc0)) { 1124 if (isSMRD(Opc1)) 1125 return checkInstOffsetsDoNotOverlap(MIa, MIb); 1126 1127 return !isFLAT(Opc1) && !isMUBUF(Opc0) && !isMTBUF(Opc0); 1128 } 1129 1130 if (isFLAT(Opc0)) { 1131 if (isFLAT(Opc1)) 1132 return checkInstOffsetsDoNotOverlap(MIa, MIb); 1133 1134 return false; 1135 } 1136 1137 return false; 1138 } 1139 1140 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB, 1141 MachineBasicBlock::iterator &MI, 1142 LiveVariables *LV) const { 1143 1144 switch (MI->getOpcode()) { 1145 default: return nullptr; 1146 case AMDGPU::V_MAC_F32_e64: break; 1147 case AMDGPU::V_MAC_F32_e32: { 1148 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0); 1149 if (Src0->isImm() && !isInlineConstant(*Src0, 4)) 1150 return nullptr; 1151 break; 1152 } 1153 } 1154 1155 const MachineOperand *Dst = getNamedOperand(*MI, AMDGPU::OpName::dst); 1156 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0); 1157 const MachineOperand *Src1 = getNamedOperand(*MI, AMDGPU::OpName::src1); 1158 const MachineOperand *Src2 = getNamedOperand(*MI, AMDGPU::OpName::src2); 1159 1160 return BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_MAD_F32)) 1161 .addOperand(*Dst) 1162 .addImm(0) // Src0 mods 1163 .addOperand(*Src0) 1164 .addImm(0) // Src1 mods 1165 .addOperand(*Src1) 1166 .addImm(0) // Src mods 1167 .addOperand(*Src2) 1168 .addImm(0) // clamp 1169 .addImm(0); // omod 1170 } 1171 1172 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const { 1173 int64_t SVal = Imm.getSExtValue(); 1174 if (SVal >= -16 && SVal <= 64) 1175 return true; 1176 1177 if (Imm.getBitWidth() == 64) { 1178 uint64_t Val = Imm.getZExtValue(); 1179 return (DoubleToBits(0.0) == Val) || 1180 (DoubleToBits(1.0) == Val) || 1181 (DoubleToBits(-1.0) == Val) || 1182 (DoubleToBits(0.5) == Val) || 1183 (DoubleToBits(-0.5) == Val) || 1184 (DoubleToBits(2.0) == Val) || 1185 (DoubleToBits(-2.0) == Val) || 1186 (DoubleToBits(4.0) == Val) || 1187 (DoubleToBits(-4.0) == Val); 1188 } 1189 1190 // The actual type of the operand does not seem to matter as long 1191 // as the bits match one of the inline immediate values. For example: 1192 // 1193 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal, 1194 // so it is a legal inline immediate. 1195 // 1196 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in 1197 // floating-point, so it is a legal inline immediate. 1198 uint32_t Val = Imm.getZExtValue(); 1199 1200 return (FloatToBits(0.0f) == Val) || 1201 (FloatToBits(1.0f) == Val) || 1202 (FloatToBits(-1.0f) == Val) || 1203 (FloatToBits(0.5f) == Val) || 1204 (FloatToBits(-0.5f) == Val) || 1205 (FloatToBits(2.0f) == Val) || 1206 (FloatToBits(-2.0f) == Val) || 1207 (FloatToBits(4.0f) == Val) || 1208 (FloatToBits(-4.0f) == Val); 1209 } 1210 1211 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO, 1212 unsigned OpSize) const { 1213 if (MO.isImm()) { 1214 // MachineOperand provides no way to tell the true operand size, since it 1215 // only records a 64-bit value. We need to know the size to determine if a 1216 // 32-bit floating point immediate bit pattern is legal for an integer 1217 // immediate. It would be for any 32-bit integer operand, but would not be 1218 // for a 64-bit one. 1219 1220 unsigned BitSize = 8 * OpSize; 1221 return isInlineConstant(APInt(BitSize, MO.getImm(), true)); 1222 } 1223 1224 return false; 1225 } 1226 1227 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO, 1228 unsigned OpSize) const { 1229 return MO.isImm() && !isInlineConstant(MO, OpSize); 1230 } 1231 1232 static bool compareMachineOp(const MachineOperand &Op0, 1233 const MachineOperand &Op1) { 1234 if (Op0.getType() != Op1.getType()) 1235 return false; 1236 1237 switch (Op0.getType()) { 1238 case MachineOperand::MO_Register: 1239 return Op0.getReg() == Op1.getReg(); 1240 case MachineOperand::MO_Immediate: 1241 return Op0.getImm() == Op1.getImm(); 1242 default: 1243 llvm_unreachable("Didn't expect to be comparing these operand types"); 1244 } 1245 } 1246 1247 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo, 1248 const MachineOperand &MO) const { 1249 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo]; 1250 1251 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI()); 1252 1253 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE) 1254 return true; 1255 1256 if (OpInfo.RegClass < 0) 1257 return false; 1258 1259 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize(); 1260 if (isLiteralConstant(MO, OpSize)) 1261 return RI.opCanUseLiteralConstant(OpInfo.OperandType); 1262 1263 return RI.opCanUseInlineConstant(OpInfo.OperandType); 1264 } 1265 1266 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const { 1267 int Op32 = AMDGPU::getVOPe32(Opcode); 1268 if (Op32 == -1) 1269 return false; 1270 1271 return pseudoToMCOpcode(Op32) != -1; 1272 } 1273 1274 bool SIInstrInfo::hasModifiers(unsigned Opcode) const { 1275 // The src0_modifier operand is present on all instructions 1276 // that have modifiers. 1277 1278 return AMDGPU::getNamedOperandIdx(Opcode, 1279 AMDGPU::OpName::src0_modifiers) != -1; 1280 } 1281 1282 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI, 1283 unsigned OpName) const { 1284 const MachineOperand *Mods = getNamedOperand(MI, OpName); 1285 return Mods && Mods->getImm(); 1286 } 1287 1288 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI, 1289 const MachineOperand &MO, 1290 unsigned OpSize) const { 1291 // Literal constants use the constant bus. 1292 if (isLiteralConstant(MO, OpSize)) 1293 return true; 1294 1295 if (!MO.isReg() || !MO.isUse()) 1296 return false; 1297 1298 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) 1299 return RI.isSGPRClass(MRI.getRegClass(MO.getReg())); 1300 1301 // FLAT_SCR is just an SGPR pair. 1302 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR)) 1303 return true; 1304 1305 // EXEC register uses the constant bus. 1306 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC) 1307 return true; 1308 1309 // SGPRs use the constant bus 1310 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC || 1311 (!MO.isImplicit() && 1312 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) || 1313 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) { 1314 return true; 1315 } 1316 1317 return false; 1318 } 1319 1320 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI, 1321 StringRef &ErrInfo) const { 1322 uint16_t Opcode = MI->getOpcode(); 1323 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 1324 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); 1325 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); 1326 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2); 1327 1328 // Make sure the number of operands is correct. 1329 const MCInstrDesc &Desc = get(Opcode); 1330 if (!Desc.isVariadic() && 1331 Desc.getNumOperands() != MI->getNumExplicitOperands()) { 1332 ErrInfo = "Instruction has wrong number of operands."; 1333 return false; 1334 } 1335 1336 // Make sure the register classes are correct 1337 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) { 1338 if (MI->getOperand(i).isFPImm()) { 1339 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast " 1340 "all fp values to integers."; 1341 return false; 1342 } 1343 1344 int RegClass = Desc.OpInfo[i].RegClass; 1345 1346 switch (Desc.OpInfo[i].OperandType) { 1347 case MCOI::OPERAND_REGISTER: 1348 if (MI->getOperand(i).isImm()) { 1349 ErrInfo = "Illegal immediate value for operand."; 1350 return false; 1351 } 1352 break; 1353 case AMDGPU::OPERAND_REG_IMM32: 1354 break; 1355 case AMDGPU::OPERAND_REG_INLINE_C: 1356 if (isLiteralConstant(MI->getOperand(i), 1357 RI.getRegClass(RegClass)->getSize())) { 1358 ErrInfo = "Illegal immediate value for operand."; 1359 return false; 1360 } 1361 break; 1362 case MCOI::OPERAND_IMMEDIATE: 1363 // Check if this operand is an immediate. 1364 // FrameIndex operands will be replaced by immediates, so they are 1365 // allowed. 1366 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFI()) { 1367 ErrInfo = "Expected immediate, but got non-immediate"; 1368 return false; 1369 } 1370 // Fall-through 1371 default: 1372 continue; 1373 } 1374 1375 if (!MI->getOperand(i).isReg()) 1376 continue; 1377 1378 if (RegClass != -1) { 1379 unsigned Reg = MI->getOperand(i).getReg(); 1380 if (TargetRegisterInfo::isVirtualRegister(Reg)) 1381 continue; 1382 1383 const TargetRegisterClass *RC = RI.getRegClass(RegClass); 1384 if (!RC->contains(Reg)) { 1385 ErrInfo = "Operand has incorrect register class."; 1386 return false; 1387 } 1388 } 1389 } 1390 1391 1392 // Verify VOP* 1393 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) { 1394 // Only look at the true operands. Only a real operand can use the constant 1395 // bus, and we don't want to check pseudo-operands like the source modifier 1396 // flags. 1397 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx }; 1398 1399 unsigned ConstantBusCount = 0; 1400 unsigned SGPRUsed = AMDGPU::NoRegister; 1401 for (int OpIdx : OpIndices) { 1402 if (OpIdx == -1) 1403 break; 1404 const MachineOperand &MO = MI->getOperand(OpIdx); 1405 if (usesConstantBus(MRI, MO, getOpSize(Opcode, OpIdx))) { 1406 if (MO.isReg()) { 1407 if (MO.getReg() != SGPRUsed) 1408 ++ConstantBusCount; 1409 SGPRUsed = MO.getReg(); 1410 } else { 1411 ++ConstantBusCount; 1412 } 1413 } 1414 } 1415 if (ConstantBusCount > 1) { 1416 ErrInfo = "VOP* instruction uses the constant bus more than once"; 1417 return false; 1418 } 1419 } 1420 1421 // Verify misc. restrictions on specific instructions. 1422 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 || 1423 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) { 1424 const MachineOperand &Src0 = MI->getOperand(Src0Idx); 1425 const MachineOperand &Src1 = MI->getOperand(Src1Idx); 1426 const MachineOperand &Src2 = MI->getOperand(Src2Idx); 1427 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) { 1428 if (!compareMachineOp(Src0, Src1) && 1429 !compareMachineOp(Src0, Src2)) { 1430 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2"; 1431 return false; 1432 } 1433 } 1434 } 1435 1436 return true; 1437 } 1438 1439 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) { 1440 switch (MI.getOpcode()) { 1441 default: return AMDGPU::INSTRUCTION_LIST_END; 1442 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE; 1443 case AMDGPU::COPY: return AMDGPU::COPY; 1444 case AMDGPU::PHI: return AMDGPU::PHI; 1445 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG; 1446 case AMDGPU::S_MOV_B32: 1447 return MI.getOperand(1).isReg() ? 1448 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32; 1449 case AMDGPU::S_ADD_I32: 1450 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32; 1451 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32; 1452 case AMDGPU::S_SUB_I32: 1453 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32; 1454 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32; 1455 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32; 1456 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32; 1457 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32; 1458 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32; 1459 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32; 1460 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32; 1461 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32; 1462 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32; 1463 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32; 1464 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64; 1465 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32; 1466 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64; 1467 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32; 1468 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64; 1469 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32; 1470 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32; 1471 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32; 1472 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32; 1473 case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64; 1474 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32; 1475 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32; 1476 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32; 1477 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32; 1478 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32; 1479 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32; 1480 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32; 1481 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32; 1482 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32; 1483 case AMDGPU::S_LOAD_DWORD_IMM: 1484 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64; 1485 case AMDGPU::S_LOAD_DWORDX2_IMM: 1486 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64; 1487 case AMDGPU::S_LOAD_DWORDX4_IMM: 1488 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64; 1489 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64; 1490 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32; 1491 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32; 1492 case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64; 1493 } 1494 } 1495 1496 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const { 1497 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END; 1498 } 1499 1500 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI, 1501 unsigned OpNo) const { 1502 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); 1503 const MCInstrDesc &Desc = get(MI.getOpcode()); 1504 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() || 1505 Desc.OpInfo[OpNo].RegClass == -1) { 1506 unsigned Reg = MI.getOperand(OpNo).getReg(); 1507 1508 if (TargetRegisterInfo::isVirtualRegister(Reg)) 1509 return MRI.getRegClass(Reg); 1510 return RI.getPhysRegClass(Reg); 1511 } 1512 1513 unsigned RCID = Desc.OpInfo[OpNo].RegClass; 1514 return RI.getRegClass(RCID); 1515 } 1516 1517 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const { 1518 switch (MI.getOpcode()) { 1519 case AMDGPU::COPY: 1520 case AMDGPU::REG_SEQUENCE: 1521 case AMDGPU::PHI: 1522 case AMDGPU::INSERT_SUBREG: 1523 return RI.hasVGPRs(getOpRegClass(MI, 0)); 1524 default: 1525 return RI.hasVGPRs(getOpRegClass(MI, OpNo)); 1526 } 1527 } 1528 1529 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const { 1530 MachineBasicBlock::iterator I = MI; 1531 MachineBasicBlock *MBB = MI->getParent(); 1532 MachineOperand &MO = MI->getOperand(OpIdx); 1533 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 1534 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass; 1535 const TargetRegisterClass *RC = RI.getRegClass(RCID); 1536 unsigned Opcode = AMDGPU::V_MOV_B32_e32; 1537 if (MO.isReg()) 1538 Opcode = AMDGPU::COPY; 1539 else if (RI.isSGPRClass(RC)) 1540 Opcode = AMDGPU::S_MOV_B32; 1541 1542 1543 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC); 1544 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC)) 1545 VRC = &AMDGPU::VReg_64RegClass; 1546 else 1547 VRC = &AMDGPU::VGPR_32RegClass; 1548 1549 unsigned Reg = MRI.createVirtualRegister(VRC); 1550 DebugLoc DL = MBB->findDebugLoc(I); 1551 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg) 1552 .addOperand(MO); 1553 MO.ChangeToRegister(Reg, false); 1554 } 1555 1556 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI, 1557 MachineRegisterInfo &MRI, 1558 MachineOperand &SuperReg, 1559 const TargetRegisterClass *SuperRC, 1560 unsigned SubIdx, 1561 const TargetRegisterClass *SubRC) 1562 const { 1563 assert(SuperReg.isReg()); 1564 1565 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC); 1566 unsigned SubReg = MRI.createVirtualRegister(SubRC); 1567 1568 // Just in case the super register is itself a sub-register, copy it to a new 1569 // value so we don't need to worry about merging its subreg index with the 1570 // SubIdx passed to this function. The register coalescer should be able to 1571 // eliminate this extra copy. 1572 MachineBasicBlock *MBB = MI->getParent(); 1573 DebugLoc DL = MI->getDebugLoc(); 1574 1575 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg) 1576 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg()); 1577 1578 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg) 1579 .addReg(NewSuperReg, 0, SubIdx); 1580 1581 return SubReg; 1582 } 1583 1584 MachineOperand SIInstrInfo::buildExtractSubRegOrImm( 1585 MachineBasicBlock::iterator MII, 1586 MachineRegisterInfo &MRI, 1587 MachineOperand &Op, 1588 const TargetRegisterClass *SuperRC, 1589 unsigned SubIdx, 1590 const TargetRegisterClass *SubRC) const { 1591 if (Op.isImm()) { 1592 // XXX - Is there a better way to do this? 1593 if (SubIdx == AMDGPU::sub0) 1594 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF); 1595 if (SubIdx == AMDGPU::sub1) 1596 return MachineOperand::CreateImm(Op.getImm() >> 32); 1597 1598 llvm_unreachable("Unhandled register index for immediate"); 1599 } 1600 1601 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, 1602 SubIdx, SubRC); 1603 return MachineOperand::CreateReg(SubReg, false); 1604 } 1605 1606 // Change the order of operands from (0, 1, 2) to (0, 2, 1) 1607 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const { 1608 assert(Inst->getNumExplicitOperands() == 3); 1609 MachineOperand Op1 = Inst->getOperand(1); 1610 Inst->RemoveOperand(1); 1611 Inst->addOperand(Op1); 1612 } 1613 1614 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx, 1615 const MachineOperand *MO) const { 1616 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 1617 const MCInstrDesc &InstDesc = get(MI->getOpcode()); 1618 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx]; 1619 const TargetRegisterClass *DefinedRC = 1620 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr; 1621 if (!MO) 1622 MO = &MI->getOperand(OpIdx); 1623 1624 if (isVALU(InstDesc.Opcode) && 1625 usesConstantBus(MRI, *MO, DefinedRC->getSize())) { 1626 unsigned SGPRUsed = 1627 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister; 1628 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1629 if (i == OpIdx) 1630 continue; 1631 const MachineOperand &Op = MI->getOperand(i); 1632 if (Op.isReg() && Op.getReg() != SGPRUsed && 1633 usesConstantBus(MRI, Op, getOpSize(*MI, i))) { 1634 return false; 1635 } 1636 } 1637 } 1638 1639 if (MO->isReg()) { 1640 assert(DefinedRC); 1641 const TargetRegisterClass *RC = 1642 TargetRegisterInfo::isVirtualRegister(MO->getReg()) ? 1643 MRI.getRegClass(MO->getReg()) : 1644 RI.getPhysRegClass(MO->getReg()); 1645 1646 // In order to be legal, the common sub-class must be equal to the 1647 // class of the current operand. For example: 1648 // 1649 // v_mov_b32 s0 ; Operand defined as vsrc_32 1650 // ; RI.getCommonSubClass(s0,vsrc_32) = sgpr ; LEGAL 1651 // 1652 // s_sendmsg 0, s0 ; Operand defined as m0reg 1653 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL 1654 1655 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC; 1656 } 1657 1658 1659 // Handle non-register types that are treated like immediates. 1660 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI()); 1661 1662 if (!DefinedRC) { 1663 // This operand expects an immediate. 1664 return true; 1665 } 1666 1667 return isImmOperandLegal(MI, OpIdx, *MO); 1668 } 1669 1670 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const { 1671 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 1672 1673 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), 1674 AMDGPU::OpName::src0); 1675 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), 1676 AMDGPU::OpName::src1); 1677 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), 1678 AMDGPU::OpName::src2); 1679 1680 // Legalize VOP2 1681 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) { 1682 // Legalize src0 1683 if (!isOperandLegal(MI, Src0Idx)) 1684 legalizeOpWithMove(MI, Src0Idx); 1685 1686 // Legalize src1 1687 if (isOperandLegal(MI, Src1Idx)) 1688 return; 1689 1690 // Usually src0 of VOP2 instructions allow more types of inputs 1691 // than src1, so try to commute the instruction to decrease our 1692 // chances of having to insert a MOV instruction to legalize src1. 1693 if (MI->isCommutable()) { 1694 if (commuteInstruction(MI)) 1695 // If we are successful in commuting, then we know MI is legal, so 1696 // we are done. 1697 return; 1698 } 1699 1700 legalizeOpWithMove(MI, Src1Idx); 1701 return; 1702 } 1703 1704 // XXX - Do any VOP3 instructions read VCC? 1705 // Legalize VOP3 1706 if (isVOP3(MI->getOpcode())) { 1707 int VOP3Idx[3] = { Src0Idx, Src1Idx, Src2Idx }; 1708 1709 // Find the one SGPR operand we are allowed to use. 1710 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx); 1711 1712 for (unsigned i = 0; i < 3; ++i) { 1713 int Idx = VOP3Idx[i]; 1714 if (Idx == -1) 1715 break; 1716 MachineOperand &MO = MI->getOperand(Idx); 1717 1718 if (MO.isReg()) { 1719 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg()))) 1720 continue; // VGPRs are legal 1721 1722 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction"); 1723 1724 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) { 1725 SGPRReg = MO.getReg(); 1726 // We can use one SGPR in each VOP3 instruction. 1727 continue; 1728 } 1729 } else if (!isLiteralConstant(MO, getOpSize(MI->getOpcode(), Idx))) { 1730 // If it is not a register and not a literal constant, then it must be 1731 // an inline constant which is always legal. 1732 continue; 1733 } 1734 // If we make it this far, then the operand is not legal and we must 1735 // legalize it. 1736 legalizeOpWithMove(MI, Idx); 1737 } 1738 } 1739 1740 // Legalize REG_SEQUENCE and PHI 1741 // The register class of the operands much be the same type as the register 1742 // class of the output. 1743 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE || 1744 MI->getOpcode() == AMDGPU::PHI) { 1745 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr; 1746 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) { 1747 if (!MI->getOperand(i).isReg() || 1748 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) 1749 continue; 1750 const TargetRegisterClass *OpRC = 1751 MRI.getRegClass(MI->getOperand(i).getReg()); 1752 if (RI.hasVGPRs(OpRC)) { 1753 VRC = OpRC; 1754 } else { 1755 SRC = OpRC; 1756 } 1757 } 1758 1759 // If any of the operands are VGPR registers, then they all most be 1760 // otherwise we will create illegal VGPR->SGPR copies when legalizing 1761 // them. 1762 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) { 1763 if (!VRC) { 1764 assert(SRC); 1765 VRC = RI.getEquivalentVGPRClass(SRC); 1766 } 1767 RC = VRC; 1768 } else { 1769 RC = SRC; 1770 } 1771 1772 // Update all the operands so they have the same type. 1773 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) { 1774 if (!MI->getOperand(i).isReg() || 1775 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) 1776 continue; 1777 unsigned DstReg = MRI.createVirtualRegister(RC); 1778 MachineBasicBlock *InsertBB; 1779 MachineBasicBlock::iterator Insert; 1780 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) { 1781 InsertBB = MI->getParent(); 1782 Insert = MI; 1783 } else { 1784 // MI is a PHI instruction. 1785 InsertBB = MI->getOperand(i + 1).getMBB(); 1786 Insert = InsertBB->getFirstTerminator(); 1787 } 1788 BuildMI(*InsertBB, Insert, MI->getDebugLoc(), 1789 get(AMDGPU::COPY), DstReg) 1790 .addOperand(MI->getOperand(i)); 1791 MI->getOperand(i).setReg(DstReg); 1792 } 1793 } 1794 1795 // Legalize INSERT_SUBREG 1796 // src0 must have the same register class as dst 1797 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) { 1798 unsigned Dst = MI->getOperand(0).getReg(); 1799 unsigned Src0 = MI->getOperand(1).getReg(); 1800 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); 1801 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0); 1802 if (DstRC != Src0RC) { 1803 MachineBasicBlock &MBB = *MI->getParent(); 1804 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC); 1805 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0) 1806 .addReg(Src0); 1807 MI->getOperand(1).setReg(NewSrc0); 1808 } 1809 return; 1810 } 1811 1812 // Legalize MUBUF* instructions 1813 // FIXME: If we start using the non-addr64 instructions for compute, we 1814 // may need to legalize them here. 1815 int SRsrcIdx = 1816 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc); 1817 if (SRsrcIdx != -1) { 1818 // We have an MUBUF instruction 1819 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx); 1820 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass; 1821 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()), 1822 RI.getRegClass(SRsrcRC))) { 1823 // The operands are legal. 1824 // FIXME: We may need to legalize operands besided srsrc. 1825 return; 1826 } 1827 1828 MachineBasicBlock &MBB = *MI->getParent(); 1829 1830 // Extract the ptr from the resource descriptor. 1831 unsigned SRsrcPtr = buildExtractSubReg(MI, MRI, *SRsrc, 1832 &AMDGPU::VReg_128RegClass, AMDGPU::sub0_sub1, &AMDGPU::VReg_64RegClass); 1833 1834 // Create an empty resource descriptor 1835 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass); 1836 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); 1837 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); 1838 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass); 1839 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat(); 1840 1841 // Zero64 = 0 1842 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64), 1843 Zero64) 1844 .addImm(0); 1845 1846 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0} 1847 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), 1848 SRsrcFormatLo) 1849 .addImm(RsrcDataFormat & 0xFFFFFFFF); 1850 1851 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32} 1852 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), 1853 SRsrcFormatHi) 1854 .addImm(RsrcDataFormat >> 32); 1855 1856 // NewSRsrc = {Zero64, SRsrcFormat} 1857 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewSRsrc) 1858 .addReg(Zero64) 1859 .addImm(AMDGPU::sub0_sub1) 1860 .addReg(SRsrcFormatLo) 1861 .addImm(AMDGPU::sub2) 1862 .addReg(SRsrcFormatHi) 1863 .addImm(AMDGPU::sub3); 1864 1865 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr); 1866 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); 1867 if (VAddr) { 1868 // This is already an ADDR64 instruction so we need to add the pointer 1869 // extracted from the resource descriptor to the current value of VAddr. 1870 unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 1871 unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 1872 1873 // NewVaddrLo = SRsrcPtr:sub0 + VAddr:sub0 1874 DebugLoc DL = MI->getDebugLoc(); 1875 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), NewVAddrLo) 1876 .addReg(SRsrcPtr, 0, AMDGPU::sub0) 1877 .addReg(VAddr->getReg(), 0, AMDGPU::sub0); 1878 1879 // NewVaddrHi = SRsrcPtr:sub1 + VAddr:sub1 1880 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e32), NewVAddrHi) 1881 .addReg(SRsrcPtr, 0, AMDGPU::sub1) 1882 .addReg(VAddr->getReg(), 0, AMDGPU::sub1); 1883 1884 // NewVaddr = {NewVaddrHi, NewVaddrLo} 1885 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr) 1886 .addReg(NewVAddrLo) 1887 .addImm(AMDGPU::sub0) 1888 .addReg(NewVAddrHi) 1889 .addImm(AMDGPU::sub1); 1890 } else { 1891 // This instructions is the _OFFSET variant, so we need to convert it to 1892 // ADDR64. 1893 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata); 1894 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset); 1895 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset); 1896 1897 // Create the new instruction. 1898 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode()); 1899 MachineInstr *Addr64 = 1900 BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode)) 1901 .addOperand(*VData) 1902 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr. 1903 // This will be replaced later 1904 // with the new value of vaddr. 1905 .addOperand(*SRsrc) 1906 .addOperand(*SOffset) 1907 .addOperand(*Offset) 1908 .addImm(0) // glc 1909 .addImm(0) // slc 1910 .addImm(0) // tfe 1911 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 1912 1913 MI->removeFromParent(); 1914 MI = Addr64; 1915 1916 // NewVaddr = {NewVaddrHi, NewVaddrLo} 1917 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr) 1918 .addReg(SRsrcPtr, 0, AMDGPU::sub0) 1919 .addImm(AMDGPU::sub0) 1920 .addReg(SRsrcPtr, 0, AMDGPU::sub1) 1921 .addImm(AMDGPU::sub1); 1922 1923 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr); 1924 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc); 1925 } 1926 1927 // Update the instruction to use NewVaddr 1928 VAddr->setReg(NewVAddr); 1929 // Update the instruction to use NewSRsrc 1930 SRsrc->setReg(NewSRsrc); 1931 } 1932 } 1933 1934 void SIInstrInfo::splitSMRD(MachineInstr *MI, 1935 const TargetRegisterClass *HalfRC, 1936 unsigned HalfImmOp, unsigned HalfSGPROp, 1937 MachineInstr *&Lo, MachineInstr *&Hi) const { 1938 1939 DebugLoc DL = MI->getDebugLoc(); 1940 MachineBasicBlock *MBB = MI->getParent(); 1941 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 1942 unsigned RegLo = MRI.createVirtualRegister(HalfRC); 1943 unsigned RegHi = MRI.createVirtualRegister(HalfRC); 1944 unsigned HalfSize = HalfRC->getSize(); 1945 const MachineOperand *OffOp = 1946 getNamedOperand(*MI, AMDGPU::OpName::offset); 1947 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase); 1948 1949 // The SMRD has an 8-bit offset in dwords on SI and a 20-bit offset in bytes 1950 // on VI. 1951 1952 bool IsKill = SBase->isKill(); 1953 if (OffOp) { 1954 bool isVI = 1955 MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() >= 1956 AMDGPUSubtarget::VOLCANIC_ISLANDS; 1957 unsigned OffScale = isVI ? 1 : 4; 1958 // Handle the _IMM variant 1959 unsigned LoOffset = OffOp->getImm() * OffScale; 1960 unsigned HiOffset = LoOffset + HalfSize; 1961 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo) 1962 // Use addReg instead of addOperand 1963 // to make sure kill flag is cleared. 1964 .addReg(SBase->getReg(), 0, SBase->getSubReg()) 1965 .addImm(LoOffset / OffScale); 1966 1967 if (!isUInt<20>(HiOffset) || (!isVI && !isUInt<8>(HiOffset / OffScale))) { 1968 unsigned OffsetSGPR = 1969 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); 1970 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR) 1971 .addImm(HiOffset); // The offset in register is in bytes. 1972 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi) 1973 .addReg(SBase->getReg(), getKillRegState(IsKill), 1974 SBase->getSubReg()) 1975 .addReg(OffsetSGPR); 1976 } else { 1977 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi) 1978 .addReg(SBase->getReg(), getKillRegState(IsKill), 1979 SBase->getSubReg()) 1980 .addImm(HiOffset / OffScale); 1981 } 1982 } else { 1983 // Handle the _SGPR variant 1984 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff); 1985 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo) 1986 .addReg(SBase->getReg(), 0, SBase->getSubReg()) 1987 .addOperand(*SOff); 1988 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); 1989 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR) 1990 .addOperand(*SOff) 1991 .addImm(HalfSize); 1992 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp)) 1993 .addReg(SBase->getReg(), getKillRegState(IsKill), 1994 SBase->getSubReg()) 1995 .addReg(OffsetSGPR); 1996 } 1997 1998 unsigned SubLo, SubHi; 1999 switch (HalfSize) { 2000 case 4: 2001 SubLo = AMDGPU::sub0; 2002 SubHi = AMDGPU::sub1; 2003 break; 2004 case 8: 2005 SubLo = AMDGPU::sub0_sub1; 2006 SubHi = AMDGPU::sub2_sub3; 2007 break; 2008 case 16: 2009 SubLo = AMDGPU::sub0_sub1_sub2_sub3; 2010 SubHi = AMDGPU::sub4_sub5_sub6_sub7; 2011 break; 2012 case 32: 2013 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7; 2014 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15; 2015 break; 2016 default: 2017 llvm_unreachable("Unhandled HalfSize"); 2018 } 2019 2020 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE)) 2021 .addOperand(MI->getOperand(0)) 2022 .addReg(RegLo) 2023 .addImm(SubLo) 2024 .addReg(RegHi) 2025 .addImm(SubHi); 2026 } 2027 2028 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const { 2029 MachineBasicBlock *MBB = MI->getParent(); 2030 int DstIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst); 2031 assert(DstIdx != -1); 2032 unsigned DstRCID = get(MI->getOpcode()).OpInfo[DstIdx].RegClass; 2033 switch(RI.getRegClass(DstRCID)->getSize()) { 2034 case 4: 2035 case 8: 2036 case 16: { 2037 unsigned NewOpcode = getVALUOp(*MI); 2038 unsigned RegOffset; 2039 unsigned ImmOffset; 2040 2041 if (MI->getOperand(2).isReg()) { 2042 RegOffset = MI->getOperand(2).getReg(); 2043 ImmOffset = 0; 2044 } else { 2045 assert(MI->getOperand(2).isImm()); 2046 // SMRD instructions take a dword offsets on SI and byte offset on VI 2047 // and MUBUF instructions always take a byte offset. 2048 ImmOffset = MI->getOperand(2).getImm(); 2049 if (MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() <= 2050 AMDGPUSubtarget::SEA_ISLANDS) 2051 ImmOffset <<= 2; 2052 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); 2053 2054 if (isUInt<12>(ImmOffset)) { 2055 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), 2056 RegOffset) 2057 .addImm(0); 2058 } else { 2059 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), 2060 RegOffset) 2061 .addImm(ImmOffset); 2062 ImmOffset = 0; 2063 } 2064 } 2065 2066 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass); 2067 unsigned DWord0 = RegOffset; 2068 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); 2069 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); 2070 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); 2071 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat(); 2072 2073 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1) 2074 .addImm(0); 2075 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2) 2076 .addImm(RsrcDataFormat & 0xFFFFFFFF); 2077 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3) 2078 .addImm(RsrcDataFormat >> 32); 2079 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc) 2080 .addReg(DWord0) 2081 .addImm(AMDGPU::sub0) 2082 .addReg(DWord1) 2083 .addImm(AMDGPU::sub1) 2084 .addReg(DWord2) 2085 .addImm(AMDGPU::sub2) 2086 .addReg(DWord3) 2087 .addImm(AMDGPU::sub3); 2088 MI->setDesc(get(NewOpcode)); 2089 if (MI->getOperand(2).isReg()) { 2090 MI->getOperand(2).setReg(SRsrc); 2091 } else { 2092 MI->getOperand(2).ChangeToRegister(SRsrc, false); 2093 } 2094 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); 2095 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset)); 2096 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // glc 2097 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // slc 2098 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // tfe 2099 2100 const TargetRegisterClass *NewDstRC = 2101 RI.getRegClass(get(NewOpcode).OpInfo[0].RegClass); 2102 2103 unsigned DstReg = MI->getOperand(0).getReg(); 2104 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC); 2105 MRI.replaceRegWith(DstReg, NewDstReg); 2106 break; 2107 } 2108 case 32: { 2109 MachineInstr *Lo, *Hi; 2110 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM, 2111 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi); 2112 MI->eraseFromParent(); 2113 moveSMRDToVALU(Lo, MRI); 2114 moveSMRDToVALU(Hi, MRI); 2115 break; 2116 } 2117 2118 case 64: { 2119 MachineInstr *Lo, *Hi; 2120 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM, 2121 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi); 2122 MI->eraseFromParent(); 2123 moveSMRDToVALU(Lo, MRI); 2124 moveSMRDToVALU(Hi, MRI); 2125 break; 2126 } 2127 } 2128 } 2129 2130 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const { 2131 SmallVector<MachineInstr *, 128> Worklist; 2132 Worklist.push_back(&TopInst); 2133 2134 while (!Worklist.empty()) { 2135 MachineInstr *Inst = Worklist.pop_back_val(); 2136 MachineBasicBlock *MBB = Inst->getParent(); 2137 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 2138 2139 unsigned Opcode = Inst->getOpcode(); 2140 unsigned NewOpcode = getVALUOp(*Inst); 2141 2142 // Handle some special cases 2143 switch (Opcode) { 2144 default: 2145 if (isSMRD(Inst->getOpcode())) { 2146 moveSMRDToVALU(Inst, MRI); 2147 } 2148 break; 2149 case AMDGPU::S_AND_B64: 2150 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_AND_B32_e64); 2151 Inst->eraseFromParent(); 2152 continue; 2153 2154 case AMDGPU::S_OR_B64: 2155 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_OR_B32_e64); 2156 Inst->eraseFromParent(); 2157 continue; 2158 2159 case AMDGPU::S_XOR_B64: 2160 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_XOR_B32_e64); 2161 Inst->eraseFromParent(); 2162 continue; 2163 2164 case AMDGPU::S_NOT_B64: 2165 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::V_NOT_B32_e32); 2166 Inst->eraseFromParent(); 2167 continue; 2168 2169 case AMDGPU::S_BCNT1_I32_B64: 2170 splitScalar64BitBCNT(Worklist, Inst); 2171 Inst->eraseFromParent(); 2172 continue; 2173 2174 case AMDGPU::S_BFE_I64: { 2175 splitScalar64BitBFE(Worklist, Inst); 2176 Inst->eraseFromParent(); 2177 continue; 2178 } 2179 2180 case AMDGPU::S_LSHL_B32: 2181 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { 2182 NewOpcode = AMDGPU::V_LSHLREV_B32_e64; 2183 swapOperands(Inst); 2184 } 2185 break; 2186 case AMDGPU::S_ASHR_I32: 2187 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { 2188 NewOpcode = AMDGPU::V_ASHRREV_I32_e64; 2189 swapOperands(Inst); 2190 } 2191 break; 2192 case AMDGPU::S_LSHR_B32: 2193 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { 2194 NewOpcode = AMDGPU::V_LSHRREV_B32_e64; 2195 swapOperands(Inst); 2196 } 2197 break; 2198 case AMDGPU::S_LSHL_B64: 2199 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { 2200 NewOpcode = AMDGPU::V_LSHLREV_B64; 2201 swapOperands(Inst); 2202 } 2203 break; 2204 case AMDGPU::S_ASHR_I64: 2205 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { 2206 NewOpcode = AMDGPU::V_ASHRREV_I64; 2207 swapOperands(Inst); 2208 } 2209 break; 2210 case AMDGPU::S_LSHR_B64: 2211 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { 2212 NewOpcode = AMDGPU::V_LSHRREV_B64; 2213 swapOperands(Inst); 2214 } 2215 break; 2216 2217 case AMDGPU::S_BFE_U64: 2218 case AMDGPU::S_BFM_B64: 2219 llvm_unreachable("Moving this op to VALU not implemented"); 2220 } 2221 2222 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) { 2223 // We cannot move this instruction to the VALU, so we should try to 2224 // legalize its operands instead. 2225 legalizeOperands(Inst); 2226 continue; 2227 } 2228 2229 // Use the new VALU Opcode. 2230 const MCInstrDesc &NewDesc = get(NewOpcode); 2231 Inst->setDesc(NewDesc); 2232 2233 // Remove any references to SCC. Vector instructions can't read from it, and 2234 // We're just about to add the implicit use / defs of VCC, and we don't want 2235 // both. 2236 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) { 2237 MachineOperand &Op = Inst->getOperand(i); 2238 if (Op.isReg() && Op.getReg() == AMDGPU::SCC) 2239 Inst->RemoveOperand(i); 2240 } 2241 2242 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) { 2243 // We are converting these to a BFE, so we need to add the missing 2244 // operands for the size and offset. 2245 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16; 2246 Inst->addOperand(MachineOperand::CreateImm(0)); 2247 Inst->addOperand(MachineOperand::CreateImm(Size)); 2248 2249 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) { 2250 // The VALU version adds the second operand to the result, so insert an 2251 // extra 0 operand. 2252 Inst->addOperand(MachineOperand::CreateImm(0)); 2253 } 2254 2255 Inst->addImplicitDefUseOperands(*Inst->getParent()->getParent()); 2256 2257 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) { 2258 const MachineOperand &OffsetWidthOp = Inst->getOperand(2); 2259 // If we need to move this to VGPRs, we need to unpack the second operand 2260 // back into the 2 separate ones for bit offset and width. 2261 assert(OffsetWidthOp.isImm() && 2262 "Scalar BFE is only implemented for constant width and offset"); 2263 uint32_t Imm = OffsetWidthOp.getImm(); 2264 2265 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0]. 2266 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16]. 2267 Inst->RemoveOperand(2); // Remove old immediate. 2268 Inst->addOperand(MachineOperand::CreateImm(Offset)); 2269 Inst->addOperand(MachineOperand::CreateImm(BitWidth)); 2270 } 2271 2272 // Update the destination register class. 2273 2274 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0); 2275 2276 switch (Opcode) { 2277 // For target instructions, getOpRegClass just returns the virtual 2278 // register class associated with the operand, so we need to find an 2279 // equivalent VGPR register class in order to move the instruction to the 2280 // VALU. 2281 case AMDGPU::COPY: 2282 case AMDGPU::PHI: 2283 case AMDGPU::REG_SEQUENCE: 2284 case AMDGPU::INSERT_SUBREG: 2285 if (RI.hasVGPRs(NewDstRC)) 2286 continue; 2287 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC); 2288 if (!NewDstRC) 2289 continue; 2290 break; 2291 default: 2292 break; 2293 } 2294 2295 unsigned DstReg = Inst->getOperand(0).getReg(); 2296 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC); 2297 MRI.replaceRegWith(DstReg, NewDstReg); 2298 2299 // Legalize the operands 2300 legalizeOperands(Inst); 2301 2302 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist); 2303 } 2304 } 2305 2306 //===----------------------------------------------------------------------===// 2307 // Indirect addressing callbacks 2308 //===----------------------------------------------------------------------===// 2309 2310 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex, 2311 unsigned Channel) const { 2312 assert(Channel == 0); 2313 return RegIndex; 2314 } 2315 2316 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const { 2317 return &AMDGPU::VGPR_32RegClass; 2318 } 2319 2320 void SIInstrInfo::splitScalar64BitUnaryOp( 2321 SmallVectorImpl<MachineInstr *> &Worklist, 2322 MachineInstr *Inst, 2323 unsigned Opcode) const { 2324 MachineBasicBlock &MBB = *Inst->getParent(); 2325 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2326 2327 MachineOperand &Dest = Inst->getOperand(0); 2328 MachineOperand &Src0 = Inst->getOperand(1); 2329 DebugLoc DL = Inst->getDebugLoc(); 2330 2331 MachineBasicBlock::iterator MII = Inst; 2332 2333 const MCInstrDesc &InstDesc = get(Opcode); 2334 const TargetRegisterClass *Src0RC = Src0.isReg() ? 2335 MRI.getRegClass(Src0.getReg()) : 2336 &AMDGPU::SGPR_32RegClass; 2337 2338 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); 2339 2340 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, 2341 AMDGPU::sub0, Src0SubRC); 2342 2343 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); 2344 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); 2345 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); 2346 2347 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC); 2348 BuildMI(MBB, MII, DL, InstDesc, DestSub0) 2349 .addOperand(SrcReg0Sub0); 2350 2351 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, 2352 AMDGPU::sub1, Src0SubRC); 2353 2354 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC); 2355 BuildMI(MBB, MII, DL, InstDesc, DestSub1) 2356 .addOperand(SrcReg0Sub1); 2357 2358 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC); 2359 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg) 2360 .addReg(DestSub0) 2361 .addImm(AMDGPU::sub0) 2362 .addReg(DestSub1) 2363 .addImm(AMDGPU::sub1); 2364 2365 MRI.replaceRegWith(Dest.getReg(), FullDestReg); 2366 2367 // We don't need to legalizeOperands here because for a single operand, src0 2368 // will support any kind of input. 2369 2370 // Move all users of this moved value. 2371 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist); 2372 } 2373 2374 void SIInstrInfo::splitScalar64BitBinaryOp( 2375 SmallVectorImpl<MachineInstr *> &Worklist, 2376 MachineInstr *Inst, 2377 unsigned Opcode) const { 2378 MachineBasicBlock &MBB = *Inst->getParent(); 2379 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2380 2381 MachineOperand &Dest = Inst->getOperand(0); 2382 MachineOperand &Src0 = Inst->getOperand(1); 2383 MachineOperand &Src1 = Inst->getOperand(2); 2384 DebugLoc DL = Inst->getDebugLoc(); 2385 2386 MachineBasicBlock::iterator MII = Inst; 2387 2388 const MCInstrDesc &InstDesc = get(Opcode); 2389 const TargetRegisterClass *Src0RC = Src0.isReg() ? 2390 MRI.getRegClass(Src0.getReg()) : 2391 &AMDGPU::SGPR_32RegClass; 2392 2393 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); 2394 const TargetRegisterClass *Src1RC = Src1.isReg() ? 2395 MRI.getRegClass(Src1.getReg()) : 2396 &AMDGPU::SGPR_32RegClass; 2397 2398 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); 2399 2400 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, 2401 AMDGPU::sub0, Src0SubRC); 2402 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, 2403 AMDGPU::sub0, Src1SubRC); 2404 2405 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); 2406 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); 2407 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); 2408 2409 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC); 2410 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0) 2411 .addOperand(SrcReg0Sub0) 2412 .addOperand(SrcReg1Sub0); 2413 2414 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, 2415 AMDGPU::sub1, Src0SubRC); 2416 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, 2417 AMDGPU::sub1, Src1SubRC); 2418 2419 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC); 2420 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1) 2421 .addOperand(SrcReg0Sub1) 2422 .addOperand(SrcReg1Sub1); 2423 2424 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC); 2425 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg) 2426 .addReg(DestSub0) 2427 .addImm(AMDGPU::sub0) 2428 .addReg(DestSub1) 2429 .addImm(AMDGPU::sub1); 2430 2431 MRI.replaceRegWith(Dest.getReg(), FullDestReg); 2432 2433 // Try to legalize the operands in case we need to swap the order to keep it 2434 // valid. 2435 legalizeOperands(LoHalf); 2436 legalizeOperands(HiHalf); 2437 2438 // Move all users of this moved vlaue. 2439 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist); 2440 } 2441 2442 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist, 2443 MachineInstr *Inst) const { 2444 MachineBasicBlock &MBB = *Inst->getParent(); 2445 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2446 2447 MachineBasicBlock::iterator MII = Inst; 2448 DebugLoc DL = Inst->getDebugLoc(); 2449 2450 MachineOperand &Dest = Inst->getOperand(0); 2451 MachineOperand &Src = Inst->getOperand(1); 2452 2453 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64); 2454 const TargetRegisterClass *SrcRC = Src.isReg() ? 2455 MRI.getRegClass(Src.getReg()) : 2456 &AMDGPU::SGPR_32RegClass; 2457 2458 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 2459 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 2460 2461 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0); 2462 2463 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC, 2464 AMDGPU::sub0, SrcSubRC); 2465 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC, 2466 AMDGPU::sub1, SrcSubRC); 2467 2468 BuildMI(MBB, MII, DL, InstDesc, MidReg) 2469 .addOperand(SrcRegSub0) 2470 .addImm(0); 2471 2472 BuildMI(MBB, MII, DL, InstDesc, ResultReg) 2473 .addOperand(SrcRegSub1) 2474 .addReg(MidReg); 2475 2476 MRI.replaceRegWith(Dest.getReg(), ResultReg); 2477 2478 // We don't need to legalize operands here. src0 for etiher instruction can be 2479 // an SGPR, and the second input is unused or determined here. 2480 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); 2481 } 2482 2483 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist, 2484 MachineInstr *Inst) const { 2485 MachineBasicBlock &MBB = *Inst->getParent(); 2486 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2487 MachineBasicBlock::iterator MII = Inst; 2488 DebugLoc DL = Inst->getDebugLoc(); 2489 2490 MachineOperand &Dest = Inst->getOperand(0); 2491 uint32_t Imm = Inst->getOperand(2).getImm(); 2492 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0]. 2493 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16]. 2494 2495 (void) Offset; 2496 2497 // Only sext_inreg cases handled. 2498 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 && 2499 BitWidth <= 32 && 2500 Offset == 0 && 2501 "Not implemented"); 2502 2503 if (BitWidth < 32) { 2504 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 2505 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 2506 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); 2507 2508 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo) 2509 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0) 2510 .addImm(0) 2511 .addImm(BitWidth); 2512 2513 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi) 2514 .addImm(31) 2515 .addReg(MidRegLo); 2516 2517 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg) 2518 .addReg(MidRegLo) 2519 .addImm(AMDGPU::sub0) 2520 .addReg(MidRegHi) 2521 .addImm(AMDGPU::sub1); 2522 2523 MRI.replaceRegWith(Dest.getReg(), ResultReg); 2524 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); 2525 return; 2526 } 2527 2528 MachineOperand &Src = Inst->getOperand(1); 2529 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 2530 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); 2531 2532 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg) 2533 .addImm(31) 2534 .addReg(Src.getReg(), 0, AMDGPU::sub0); 2535 2536 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg) 2537 .addReg(Src.getReg(), 0, AMDGPU::sub0) 2538 .addImm(AMDGPU::sub0) 2539 .addReg(TmpReg) 2540 .addImm(AMDGPU::sub1); 2541 2542 MRI.replaceRegWith(Dest.getReg(), ResultReg); 2543 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); 2544 } 2545 2546 void SIInstrInfo::addUsersToMoveToVALUWorklist( 2547 unsigned DstReg, 2548 MachineRegisterInfo &MRI, 2549 SmallVectorImpl<MachineInstr *> &Worklist) const { 2550 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg), 2551 E = MRI.use_end(); I != E; ++I) { 2552 MachineInstr &UseMI = *I->getParent(); 2553 if (!canReadVGPR(UseMI, I.getOperandNo())) { 2554 Worklist.push_back(&UseMI); 2555 } 2556 } 2557 } 2558 2559 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI, 2560 int OpIndices[3]) const { 2561 const MCInstrDesc &Desc = get(MI->getOpcode()); 2562 2563 // Find the one SGPR operand we are allowed to use. 2564 unsigned SGPRReg = AMDGPU::NoRegister; 2565 2566 // First we need to consider the instruction's operand requirements before 2567 // legalizing. Some operands are required to be SGPRs, such as implicit uses 2568 // of VCC, but we are still bound by the constant bus requirement to only use 2569 // one. 2570 // 2571 // If the operand's class is an SGPR, we can never move it. 2572 2573 for (const MachineOperand &MO : MI->implicit_operands()) { 2574 // We only care about reads. 2575 if (MO.isDef()) 2576 continue; 2577 2578 if (MO.getReg() == AMDGPU::VCC) 2579 return AMDGPU::VCC; 2580 2581 if (MO.getReg() == AMDGPU::FLAT_SCR) 2582 return AMDGPU::FLAT_SCR; 2583 } 2584 2585 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister }; 2586 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 2587 2588 for (unsigned i = 0; i < 3; ++i) { 2589 int Idx = OpIndices[i]; 2590 if (Idx == -1) 2591 break; 2592 2593 const MachineOperand &MO = MI->getOperand(Idx); 2594 if (RI.isSGPRClassID(Desc.OpInfo[Idx].RegClass)) 2595 SGPRReg = MO.getReg(); 2596 2597 if (MO.isReg() && RI.isSGPRClass(MRI.getRegClass(MO.getReg()))) 2598 UsedSGPRs[i] = MO.getReg(); 2599 } 2600 2601 if (SGPRReg != AMDGPU::NoRegister) 2602 return SGPRReg; 2603 2604 // We don't have a required SGPR operand, so we have a bit more freedom in 2605 // selecting operands to move. 2606 2607 // Try to select the most used SGPR. If an SGPR is equal to one of the 2608 // others, we choose that. 2609 // 2610 // e.g. 2611 // V_FMA_F32 v0, s0, s0, s0 -> No moves 2612 // V_FMA_F32 v0, s0, s1, s0 -> Move s1 2613 2614 if (UsedSGPRs[0] != AMDGPU::NoRegister) { 2615 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2]) 2616 SGPRReg = UsedSGPRs[0]; 2617 } 2618 2619 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) { 2620 if (UsedSGPRs[1] == UsedSGPRs[2]) 2621 SGPRReg = UsedSGPRs[1]; 2622 } 2623 2624 return SGPRReg; 2625 } 2626 2627 MachineInstrBuilder SIInstrInfo::buildIndirectWrite( 2628 MachineBasicBlock *MBB, 2629 MachineBasicBlock::iterator I, 2630 unsigned ValueReg, 2631 unsigned Address, unsigned OffsetReg) const { 2632 const DebugLoc &DL = MBB->findDebugLoc(I); 2633 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister( 2634 getIndirectIndexBegin(*MBB->getParent())); 2635 2636 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1)) 2637 .addReg(IndirectBaseReg, RegState::Define) 2638 .addOperand(I->getOperand(0)) 2639 .addReg(IndirectBaseReg) 2640 .addReg(OffsetReg) 2641 .addImm(0) 2642 .addReg(ValueReg); 2643 } 2644 2645 MachineInstrBuilder SIInstrInfo::buildIndirectRead( 2646 MachineBasicBlock *MBB, 2647 MachineBasicBlock::iterator I, 2648 unsigned ValueReg, 2649 unsigned Address, unsigned OffsetReg) const { 2650 const DebugLoc &DL = MBB->findDebugLoc(I); 2651 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister( 2652 getIndirectIndexBegin(*MBB->getParent())); 2653 2654 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC)) 2655 .addOperand(I->getOperand(0)) 2656 .addOperand(I->getOperand(1)) 2657 .addReg(IndirectBaseReg) 2658 .addReg(OffsetReg) 2659 .addImm(0); 2660 2661 } 2662 2663 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved, 2664 const MachineFunction &MF) const { 2665 int End = getIndirectIndexEnd(MF); 2666 int Begin = getIndirectIndexBegin(MF); 2667 2668 if (End == -1) 2669 return; 2670 2671 2672 for (int Index = Begin; Index <= End; ++Index) 2673 Reserved.set(AMDGPU::VGPR_32RegClass.getRegister(Index)); 2674 2675 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index) 2676 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index)); 2677 2678 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index) 2679 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index)); 2680 2681 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index) 2682 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index)); 2683 2684 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index) 2685 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index)); 2686 2687 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index) 2688 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index)); 2689 } 2690 2691 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI, 2692 unsigned OperandName) const { 2693 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName); 2694 if (Idx == -1) 2695 return nullptr; 2696 2697 return &MI.getOperand(Idx); 2698 } 2699 2700 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const { 2701 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT; 2702 if (ST.isAmdHsaOS()) { 2703 RsrcDataFormat |= (1ULL << 56); 2704 2705 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) 2706 // Set MTYPE = 2 2707 RsrcDataFormat |= (2ULL << 59); 2708 } 2709 2710 return RsrcDataFormat; 2711 } 2712