1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief SI Implementation of TargetInstrInfo. 12 // 13 //===----------------------------------------------------------------------===// 14 15 16 #include "SIInstrInfo.h" 17 #include "AMDGPUTargetMachine.h" 18 #include "SIDefines.h" 19 #include "SIMachineFunctionInfo.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/IR/Function.h" 24 #include "llvm/CodeGen/RegisterScavenging.h" 25 #include "llvm/MC/MCInstrDesc.h" 26 #include "llvm/Support/Debug.h" 27 28 using namespace llvm; 29 30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st) 31 : AMDGPUInstrInfo(st), RI() {} 32 33 //===----------------------------------------------------------------------===// 34 // TargetInstrInfo callbacks 35 //===----------------------------------------------------------------------===// 36 37 static unsigned getNumOperandsNoGlue(SDNode *Node) { 38 unsigned N = Node->getNumOperands(); 39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue) 40 --N; 41 return N; 42 } 43 44 static SDValue findChainOperand(SDNode *Load) { 45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1); 46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node"); 47 return LastOp; 48 } 49 50 /// \brief Returns true if both nodes have the same value for the given 51 /// operand \p Op, or if both nodes do not have this operand. 52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) { 53 unsigned Opc0 = N0->getMachineOpcode(); 54 unsigned Opc1 = N1->getMachineOpcode(); 55 56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName); 57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); 58 59 if (Op0Idx == -1 && Op1Idx == -1) 60 return true; 61 62 63 if ((Op0Idx == -1 && Op1Idx != -1) || 64 (Op1Idx == -1 && Op0Idx != -1)) 65 return false; 66 67 // getNamedOperandIdx returns the index for the MachineInstr's operands, 68 // which includes the result as the first operand. We are indexing into the 69 // MachineSDNode's operands, so we need to skip the result operand to get 70 // the real index. 71 --Op0Idx; 72 --Op1Idx; 73 74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx); 75 } 76 77 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, 78 AliasAnalysis *AA) const { 79 // TODO: The generic check fails for VALU instructions that should be 80 // rematerializable due to implicit reads of exec. We really want all of the 81 // generic logic for this except for this. 82 switch (MI->getOpcode()) { 83 case AMDGPU::V_MOV_B32_e32: 84 case AMDGPU::V_MOV_B32_e64: 85 case AMDGPU::V_MOV_B64_PSEUDO: 86 return true; 87 default: 88 return false; 89 } 90 } 91 92 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, 93 int64_t &Offset0, 94 int64_t &Offset1) const { 95 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode()) 96 return false; 97 98 unsigned Opc0 = Load0->getMachineOpcode(); 99 unsigned Opc1 = Load1->getMachineOpcode(); 100 101 // Make sure both are actually loads. 102 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad()) 103 return false; 104 105 if (isDS(Opc0) && isDS(Opc1)) { 106 107 // FIXME: Handle this case: 108 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1)) 109 return false; 110 111 // Check base reg. 112 if (Load0->getOperand(1) != Load1->getOperand(1)) 113 return false; 114 115 // Check chain. 116 if (findChainOperand(Load0) != findChainOperand(Load1)) 117 return false; 118 119 // Skip read2 / write2 variants for simplicity. 120 // TODO: We should report true if the used offsets are adjacent (excluded 121 // st64 versions). 122 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 || 123 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1) 124 return false; 125 126 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue(); 127 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue(); 128 return true; 129 } 130 131 if (isSMRD(Opc0) && isSMRD(Opc1)) { 132 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1)); 133 134 // Check base reg. 135 if (Load0->getOperand(0) != Load1->getOperand(0)) 136 return false; 137 138 const ConstantSDNode *Load0Offset = 139 dyn_cast<ConstantSDNode>(Load0->getOperand(1)); 140 const ConstantSDNode *Load1Offset = 141 dyn_cast<ConstantSDNode>(Load1->getOperand(1)); 142 143 if (!Load0Offset || !Load1Offset) 144 return false; 145 146 // Check chain. 147 if (findChainOperand(Load0) != findChainOperand(Load1)) 148 return false; 149 150 Offset0 = Load0Offset->getZExtValue(); 151 Offset1 = Load1Offset->getZExtValue(); 152 return true; 153 } 154 155 // MUBUF and MTBUF can access the same addresses. 156 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) { 157 158 // MUBUF and MTBUF have vaddr at different indices. 159 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) || 160 findChainOperand(Load0) != findChainOperand(Load1) || 161 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) || 162 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc)) 163 return false; 164 165 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset); 166 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset); 167 168 if (OffIdx0 == -1 || OffIdx1 == -1) 169 return false; 170 171 // getNamedOperandIdx returns the index for MachineInstrs. Since they 172 // inlcude the output in the operand list, but SDNodes don't, we need to 173 // subtract the index by one. 174 --OffIdx0; 175 --OffIdx1; 176 177 SDValue Off0 = Load0->getOperand(OffIdx0); 178 SDValue Off1 = Load1->getOperand(OffIdx1); 179 180 // The offset might be a FrameIndexSDNode. 181 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1)) 182 return false; 183 184 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue(); 185 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue(); 186 return true; 187 } 188 189 return false; 190 } 191 192 static bool isStride64(unsigned Opc) { 193 switch (Opc) { 194 case AMDGPU::DS_READ2ST64_B32: 195 case AMDGPU::DS_READ2ST64_B64: 196 case AMDGPU::DS_WRITE2ST64_B32: 197 case AMDGPU::DS_WRITE2ST64_B64: 198 return true; 199 default: 200 return false; 201 } 202 } 203 204 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg, 205 unsigned &Offset, 206 const TargetRegisterInfo *TRI) const { 207 unsigned Opc = LdSt->getOpcode(); 208 209 if (isDS(*LdSt)) { 210 const MachineOperand *OffsetImm = getNamedOperand(*LdSt, 211 AMDGPU::OpName::offset); 212 if (OffsetImm) { 213 // Normal, single offset LDS instruction. 214 const MachineOperand *AddrReg = getNamedOperand(*LdSt, 215 AMDGPU::OpName::addr); 216 217 BaseReg = AddrReg->getReg(); 218 Offset = OffsetImm->getImm(); 219 return true; 220 } 221 222 // The 2 offset instructions use offset0 and offset1 instead. We can treat 223 // these as a load with a single offset if the 2 offsets are consecutive. We 224 // will use this for some partially aligned loads. 225 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt, 226 AMDGPU::OpName::offset0); 227 // DS_PERMUTE does not have Offset0Imm (and Offset1Imm). 228 if (!Offset0Imm) 229 return false; 230 231 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt, 232 AMDGPU::OpName::offset1); 233 234 uint8_t Offset0 = Offset0Imm->getImm(); 235 uint8_t Offset1 = Offset1Imm->getImm(); 236 237 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) { 238 // Each of these offsets is in element sized units, so we need to convert 239 // to bytes of the individual reads. 240 241 unsigned EltSize; 242 if (LdSt->mayLoad()) 243 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2; 244 else { 245 assert(LdSt->mayStore()); 246 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0); 247 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize(); 248 } 249 250 if (isStride64(Opc)) 251 EltSize *= 64; 252 253 const MachineOperand *AddrReg = getNamedOperand(*LdSt, 254 AMDGPU::OpName::addr); 255 BaseReg = AddrReg->getReg(); 256 Offset = EltSize * Offset0; 257 return true; 258 } 259 260 return false; 261 } 262 263 if (isMUBUF(*LdSt) || isMTBUF(*LdSt)) { 264 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1) 265 return false; 266 267 const MachineOperand *AddrReg = getNamedOperand(*LdSt, 268 AMDGPU::OpName::vaddr); 269 if (!AddrReg) 270 return false; 271 272 const MachineOperand *OffsetImm = getNamedOperand(*LdSt, 273 AMDGPU::OpName::offset); 274 BaseReg = AddrReg->getReg(); 275 Offset = OffsetImm->getImm(); 276 return true; 277 } 278 279 if (isSMRD(*LdSt)) { 280 const MachineOperand *OffsetImm = getNamedOperand(*LdSt, 281 AMDGPU::OpName::offset); 282 if (!OffsetImm) 283 return false; 284 285 const MachineOperand *SBaseReg = getNamedOperand(*LdSt, 286 AMDGPU::OpName::sbase); 287 BaseReg = SBaseReg->getReg(); 288 Offset = OffsetImm->getImm(); 289 return true; 290 } 291 292 return false; 293 } 294 295 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt, 296 MachineInstr *SecondLdSt, 297 unsigned NumLoads) const { 298 // TODO: This needs finer tuning 299 if (NumLoads > 4) 300 return false; 301 302 if (isDS(*FirstLdSt) && isDS(*SecondLdSt)) 303 return true; 304 305 if (isSMRD(*FirstLdSt) && isSMRD(*SecondLdSt)) 306 return true; 307 308 return (isMUBUF(*FirstLdSt) || isMTBUF(*FirstLdSt)) && 309 (isMUBUF(*SecondLdSt) || isMTBUF(*SecondLdSt)); 310 } 311 312 void 313 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 314 MachineBasicBlock::iterator MI, DebugLoc DL, 315 unsigned DestReg, unsigned SrcReg, 316 bool KillSrc) const { 317 318 // If we are trying to copy to or from SCC, there is a bug somewhere else in 319 // the backend. While it may be theoretically possible to do this, it should 320 // never be necessary. 321 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC); 322 323 static const int16_t Sub0_15[] = { 324 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 325 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 326 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11, 327 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 328 }; 329 330 static const int16_t Sub0_15_64[] = { 331 AMDGPU::sub0_sub1, AMDGPU::sub2_sub3, 332 AMDGPU::sub4_sub5, AMDGPU::sub6_sub7, 333 AMDGPU::sub8_sub9, AMDGPU::sub10_sub11, 334 AMDGPU::sub12_sub13, AMDGPU::sub14_sub15, 335 }; 336 337 static const int16_t Sub0_7[] = { 338 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 339 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 340 }; 341 342 static const int16_t Sub0_7_64[] = { 343 AMDGPU::sub0_sub1, AMDGPU::sub2_sub3, 344 AMDGPU::sub4_sub5, AMDGPU::sub6_sub7, 345 }; 346 347 static const int16_t Sub0_3[] = { 348 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 349 }; 350 351 static const int16_t Sub0_3_64[] = { 352 AMDGPU::sub0_sub1, AMDGPU::sub2_sub3, 353 }; 354 355 static const int16_t Sub0_2[] = { 356 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 357 }; 358 359 static const int16_t Sub0_1[] = { 360 AMDGPU::sub0, AMDGPU::sub1, 361 }; 362 363 unsigned Opcode; 364 ArrayRef<int16_t> SubIndices; 365 bool Forward; 366 367 if (AMDGPU::SReg_32RegClass.contains(DestReg)) { 368 assert(AMDGPU::SReg_32RegClass.contains(SrcReg)); 369 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg) 370 .addReg(SrcReg, getKillRegState(KillSrc)); 371 return; 372 373 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) { 374 if (DestReg == AMDGPU::VCC) { 375 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) { 376 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC) 377 .addReg(SrcReg, getKillRegState(KillSrc)); 378 } else { 379 // FIXME: Hack until VReg_1 removed. 380 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg)); 381 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32)) 382 .addImm(0) 383 .addReg(SrcReg, getKillRegState(KillSrc)); 384 } 385 386 return; 387 } 388 389 assert(AMDGPU::SReg_64RegClass.contains(SrcReg)); 390 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg) 391 .addReg(SrcReg, getKillRegState(KillSrc)); 392 return; 393 394 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) { 395 assert(AMDGPU::SReg_128RegClass.contains(SrcReg)); 396 Opcode = AMDGPU::S_MOV_B64; 397 SubIndices = Sub0_3_64; 398 399 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) { 400 assert(AMDGPU::SReg_256RegClass.contains(SrcReg)); 401 Opcode = AMDGPU::S_MOV_B64; 402 SubIndices = Sub0_7_64; 403 404 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) { 405 assert(AMDGPU::SReg_512RegClass.contains(SrcReg)); 406 Opcode = AMDGPU::S_MOV_B64; 407 SubIndices = Sub0_15_64; 408 409 } else if (AMDGPU::VGPR_32RegClass.contains(DestReg)) { 410 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) || 411 AMDGPU::SReg_32RegClass.contains(SrcReg)); 412 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) 413 .addReg(SrcReg, getKillRegState(KillSrc)); 414 return; 415 416 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) { 417 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) || 418 AMDGPU::SReg_64RegClass.contains(SrcReg)); 419 Opcode = AMDGPU::V_MOV_B32_e32; 420 SubIndices = Sub0_1; 421 422 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) { 423 assert(AMDGPU::VReg_96RegClass.contains(SrcReg)); 424 Opcode = AMDGPU::V_MOV_B32_e32; 425 SubIndices = Sub0_2; 426 427 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) { 428 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) || 429 AMDGPU::SReg_128RegClass.contains(SrcReg)); 430 Opcode = AMDGPU::V_MOV_B32_e32; 431 SubIndices = Sub0_3; 432 433 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) { 434 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) || 435 AMDGPU::SReg_256RegClass.contains(SrcReg)); 436 Opcode = AMDGPU::V_MOV_B32_e32; 437 SubIndices = Sub0_7; 438 439 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) { 440 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) || 441 AMDGPU::SReg_512RegClass.contains(SrcReg)); 442 Opcode = AMDGPU::V_MOV_B32_e32; 443 SubIndices = Sub0_15; 444 445 } else { 446 llvm_unreachable("Can't copy register!"); 447 } 448 449 if (RI.getHWRegIndex(DestReg) <= RI.getHWRegIndex(SrcReg)) 450 Forward = true; 451 else 452 Forward = false; 453 454 for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) { 455 unsigned SubIdx; 456 if (Forward) 457 SubIdx = SubIndices[Idx]; 458 else 459 SubIdx = SubIndices[SubIndices.size() - Idx - 1]; 460 461 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL, 462 get(Opcode), RI.getSubReg(DestReg, SubIdx)); 463 464 Builder.addReg(RI.getSubReg(SrcReg, SubIdx)); 465 466 if (Idx == SubIndices.size() - 1) 467 Builder.addReg(SrcReg, RegState::Kill | RegState::Implicit); 468 469 if (Idx == 0) 470 Builder.addReg(DestReg, RegState::Define | RegState::Implicit); 471 } 472 } 473 474 int SIInstrInfo::commuteOpcode(const MachineInstr &MI) const { 475 const unsigned Opcode = MI.getOpcode(); 476 477 int NewOpc; 478 479 // Try to map original to commuted opcode 480 NewOpc = AMDGPU::getCommuteRev(Opcode); 481 if (NewOpc != -1) 482 // Check if the commuted (REV) opcode exists on the target. 483 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1; 484 485 // Try to map commuted to original opcode 486 NewOpc = AMDGPU::getCommuteOrig(Opcode); 487 if (NewOpc != -1) 488 // Check if the original (non-REV) opcode exists on the target. 489 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1; 490 491 return Opcode; 492 } 493 494 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const { 495 496 if (DstRC->getSize() == 4) { 497 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; 498 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) { 499 return AMDGPU::S_MOV_B64; 500 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) { 501 return AMDGPU::V_MOV_B64_PSEUDO; 502 } 503 return AMDGPU::COPY; 504 } 505 506 static unsigned getSGPRSpillSaveOpcode(unsigned Size) { 507 switch (Size) { 508 case 4: 509 return AMDGPU::SI_SPILL_S32_SAVE; 510 case 8: 511 return AMDGPU::SI_SPILL_S64_SAVE; 512 case 16: 513 return AMDGPU::SI_SPILL_S128_SAVE; 514 case 32: 515 return AMDGPU::SI_SPILL_S256_SAVE; 516 case 64: 517 return AMDGPU::SI_SPILL_S512_SAVE; 518 default: 519 llvm_unreachable("unknown register size"); 520 } 521 } 522 523 static unsigned getVGPRSpillSaveOpcode(unsigned Size) { 524 switch (Size) { 525 case 4: 526 return AMDGPU::SI_SPILL_V32_SAVE; 527 case 8: 528 return AMDGPU::SI_SPILL_V64_SAVE; 529 case 16: 530 return AMDGPU::SI_SPILL_V128_SAVE; 531 case 32: 532 return AMDGPU::SI_SPILL_V256_SAVE; 533 case 64: 534 return AMDGPU::SI_SPILL_V512_SAVE; 535 default: 536 llvm_unreachable("unknown register size"); 537 } 538 } 539 540 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 541 MachineBasicBlock::iterator MI, 542 unsigned SrcReg, bool isKill, 543 int FrameIndex, 544 const TargetRegisterClass *RC, 545 const TargetRegisterInfo *TRI) const { 546 MachineFunction *MF = MBB.getParent(); 547 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>(); 548 MachineFrameInfo *FrameInfo = MF->getFrameInfo(); 549 DebugLoc DL = MBB.findDebugLoc(MI); 550 551 unsigned Size = FrameInfo->getObjectSize(FrameIndex); 552 unsigned Align = FrameInfo->getObjectAlignment(FrameIndex); 553 MachinePointerInfo PtrInfo 554 = MachinePointerInfo::getFixedStack(*MF, FrameIndex); 555 MachineMemOperand *MMO 556 = MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore, 557 Size, Align); 558 559 if (RI.isSGPRClass(RC)) { 560 MFI->setHasSpilledSGPRs(); 561 562 // We are only allowed to create one new instruction when spilling 563 // registers, so we need to use pseudo instruction for spilling 564 // SGPRs. 565 unsigned Opcode = getSGPRSpillSaveOpcode(RC->getSize()); 566 BuildMI(MBB, MI, DL, get(Opcode)) 567 .addReg(SrcReg) // src 568 .addFrameIndex(FrameIndex) // frame_idx 569 .addMemOperand(MMO); 570 571 return; 572 } 573 574 if (!ST.isVGPRSpillingEnabled(MFI)) { 575 LLVMContext &Ctx = MF->getFunction()->getContext(); 576 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to" 577 " spill register"); 578 BuildMI(MBB, MI, DL, get(AMDGPU::KILL)) 579 .addReg(SrcReg); 580 581 return; 582 } 583 584 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected"); 585 586 unsigned Opcode = getVGPRSpillSaveOpcode(RC->getSize()); 587 MFI->setHasSpilledVGPRs(); 588 BuildMI(MBB, MI, DL, get(Opcode)) 589 .addReg(SrcReg) // src 590 .addFrameIndex(FrameIndex) // frame_idx 591 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc 592 .addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset 593 .addMemOperand(MMO); 594 } 595 596 static unsigned getSGPRSpillRestoreOpcode(unsigned Size) { 597 switch (Size) { 598 case 4: 599 return AMDGPU::SI_SPILL_S32_RESTORE; 600 case 8: 601 return AMDGPU::SI_SPILL_S64_RESTORE; 602 case 16: 603 return AMDGPU::SI_SPILL_S128_RESTORE; 604 case 32: 605 return AMDGPU::SI_SPILL_S256_RESTORE; 606 case 64: 607 return AMDGPU::SI_SPILL_S512_RESTORE; 608 default: 609 llvm_unreachable("unknown register size"); 610 } 611 } 612 613 static unsigned getVGPRSpillRestoreOpcode(unsigned Size) { 614 switch (Size) { 615 case 4: 616 return AMDGPU::SI_SPILL_V32_RESTORE; 617 case 8: 618 return AMDGPU::SI_SPILL_V64_RESTORE; 619 case 16: 620 return AMDGPU::SI_SPILL_V128_RESTORE; 621 case 32: 622 return AMDGPU::SI_SPILL_V256_RESTORE; 623 case 64: 624 return AMDGPU::SI_SPILL_V512_RESTORE; 625 default: 626 llvm_unreachable("unknown register size"); 627 } 628 } 629 630 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 631 MachineBasicBlock::iterator MI, 632 unsigned DestReg, int FrameIndex, 633 const TargetRegisterClass *RC, 634 const TargetRegisterInfo *TRI) const { 635 MachineFunction *MF = MBB.getParent(); 636 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>(); 637 MachineFrameInfo *FrameInfo = MF->getFrameInfo(); 638 DebugLoc DL = MBB.findDebugLoc(MI); 639 unsigned Align = FrameInfo->getObjectAlignment(FrameIndex); 640 unsigned Size = FrameInfo->getObjectSize(FrameIndex); 641 642 MachinePointerInfo PtrInfo 643 = MachinePointerInfo::getFixedStack(*MF, FrameIndex); 644 645 MachineMemOperand *MMO = MF->getMachineMemOperand( 646 PtrInfo, MachineMemOperand::MOLoad, Size, Align); 647 648 if (RI.isSGPRClass(RC)) { 649 // FIXME: Maybe this should not include a memoperand because it will be 650 // lowered to non-memory instructions. 651 unsigned Opcode = getSGPRSpillRestoreOpcode(RC->getSize()); 652 BuildMI(MBB, MI, DL, get(Opcode), DestReg) 653 .addFrameIndex(FrameIndex) // frame_idx 654 .addMemOperand(MMO); 655 656 return; 657 } 658 659 if (!ST.isVGPRSpillingEnabled(MFI)) { 660 LLVMContext &Ctx = MF->getFunction()->getContext(); 661 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to" 662 " restore register"); 663 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg); 664 665 return; 666 } 667 668 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected"); 669 670 unsigned Opcode = getVGPRSpillRestoreOpcode(RC->getSize()); 671 BuildMI(MBB, MI, DL, get(Opcode), DestReg) 672 .addFrameIndex(FrameIndex) // frame_idx 673 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc 674 .addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset 675 .addMemOperand(MMO); 676 } 677 678 /// \param @Offset Offset in bytes of the FrameIndex being spilled 679 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB, 680 MachineBasicBlock::iterator MI, 681 RegScavenger *RS, unsigned TmpReg, 682 unsigned FrameOffset, 683 unsigned Size) const { 684 MachineFunction *MF = MBB.getParent(); 685 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>(); 686 const AMDGPUSubtarget &ST = MF->getSubtarget<AMDGPUSubtarget>(); 687 const SIRegisterInfo *TRI = 688 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo()); 689 DebugLoc DL = MBB.findDebugLoc(MI); 690 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF); 691 unsigned WavefrontSize = ST.getWavefrontSize(); 692 693 unsigned TIDReg = MFI->getTIDReg(); 694 if (!MFI->hasCalculatedTID()) { 695 MachineBasicBlock &Entry = MBB.getParent()->front(); 696 MachineBasicBlock::iterator Insert = Entry.front(); 697 DebugLoc DL = Insert->getDebugLoc(); 698 699 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass); 700 if (TIDReg == AMDGPU::NoRegister) 701 return TIDReg; 702 703 704 if (MFI->getShaderType() == ShaderType::COMPUTE && 705 WorkGroupSize > WavefrontSize) { 706 707 unsigned TIDIGXReg 708 = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_X); 709 unsigned TIDIGYReg 710 = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_Y); 711 unsigned TIDIGZReg 712 = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_Z); 713 unsigned InputPtrReg = 714 TRI->getPreloadedValue(*MF, SIRegisterInfo::KERNARG_SEGMENT_PTR); 715 for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) { 716 if (!Entry.isLiveIn(Reg)) 717 Entry.addLiveIn(Reg); 718 } 719 720 RS->enterBasicBlock(&Entry); 721 // FIXME: Can we scavenge an SReg_64 and access the subregs? 722 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0); 723 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0); 724 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0) 725 .addReg(InputPtrReg) 726 .addImm(SI::KernelInputOffsets::NGROUPS_Z); 727 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1) 728 .addReg(InputPtrReg) 729 .addImm(SI::KernelInputOffsets::NGROUPS_Y); 730 731 // NGROUPS.X * NGROUPS.Y 732 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1) 733 .addReg(STmp1) 734 .addReg(STmp0); 735 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X 736 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg) 737 .addReg(STmp1) 738 .addReg(TIDIGXReg); 739 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X) 740 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg) 741 .addReg(STmp0) 742 .addReg(TIDIGYReg) 743 .addReg(TIDReg); 744 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z 745 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg) 746 .addReg(TIDReg) 747 .addReg(TIDIGZReg); 748 } else { 749 // Get the wave id 750 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64), 751 TIDReg) 752 .addImm(-1) 753 .addImm(0); 754 755 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64), 756 TIDReg) 757 .addImm(-1) 758 .addReg(TIDReg); 759 } 760 761 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32), 762 TIDReg) 763 .addImm(2) 764 .addReg(TIDReg); 765 MFI->setTIDReg(TIDReg); 766 } 767 768 // Add FrameIndex to LDS offset 769 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize); 770 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg) 771 .addImm(LDSOffset) 772 .addReg(TIDReg); 773 774 return TmpReg; 775 } 776 777 void SIInstrInfo::insertWaitStates(MachineBasicBlock::iterator MI, 778 int Count) const { 779 while (Count > 0) { 780 int Arg; 781 if (Count >= 8) 782 Arg = 7; 783 else 784 Arg = Count - 1; 785 Count -= 8; 786 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP)) 787 .addImm(Arg); 788 } 789 } 790 791 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 792 MachineBasicBlock &MBB = *MI->getParent(); 793 DebugLoc DL = MBB.findDebugLoc(MI); 794 switch (MI->getOpcode()) { 795 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI); 796 797 case AMDGPU::SGPR_USE: 798 // This is just a placeholder for register allocation. 799 MI->eraseFromParent(); 800 break; 801 802 case AMDGPU::V_MOV_B64_PSEUDO: { 803 unsigned Dst = MI->getOperand(0).getReg(); 804 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0); 805 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1); 806 807 const MachineOperand &SrcOp = MI->getOperand(1); 808 // FIXME: Will this work for 64-bit floating point immediates? 809 assert(!SrcOp.isFPImm()); 810 if (SrcOp.isImm()) { 811 APInt Imm(64, SrcOp.getImm()); 812 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) 813 .addImm(Imm.getLoBits(32).getZExtValue()) 814 .addReg(Dst, RegState::Implicit); 815 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) 816 .addImm(Imm.getHiBits(32).getZExtValue()) 817 .addReg(Dst, RegState::Implicit); 818 } else { 819 assert(SrcOp.isReg()); 820 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) 821 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) 822 .addReg(Dst, RegState::Implicit); 823 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) 824 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1)) 825 .addReg(Dst, RegState::Implicit); 826 } 827 MI->eraseFromParent(); 828 break; 829 } 830 831 case AMDGPU::V_CNDMASK_B64_PSEUDO: { 832 unsigned Dst = MI->getOperand(0).getReg(); 833 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0); 834 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1); 835 unsigned Src0 = MI->getOperand(1).getReg(); 836 unsigned Src1 = MI->getOperand(2).getReg(); 837 const MachineOperand &SrcCond = MI->getOperand(3); 838 839 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstLo) 840 .addReg(RI.getSubReg(Src0, AMDGPU::sub0)) 841 .addReg(RI.getSubReg(Src1, AMDGPU::sub0)) 842 .addOperand(SrcCond); 843 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstHi) 844 .addReg(RI.getSubReg(Src0, AMDGPU::sub1)) 845 .addReg(RI.getSubReg(Src1, AMDGPU::sub1)) 846 .addOperand(SrcCond); 847 MI->eraseFromParent(); 848 break; 849 } 850 851 case AMDGPU::SI_CONSTDATA_PTR: { 852 const SIRegisterInfo *TRI = 853 static_cast<const SIRegisterInfo *>(ST.getRegisterInfo()); 854 MachineFunction &MF = *MBB.getParent(); 855 unsigned Reg = MI->getOperand(0).getReg(); 856 unsigned RegLo = TRI->getSubReg(Reg, AMDGPU::sub0); 857 unsigned RegHi = TRI->getSubReg(Reg, AMDGPU::sub1); 858 859 // Create a bundle so these instructions won't be re-ordered by the 860 // post-RA scheduler. 861 MIBundleBuilder Bundler(MBB, MI); 862 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_GETPC_B64), Reg)); 863 864 // Add 32-bit offset from this instruction to the start of the 865 // constant data. 866 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo) 867 .addReg(RegLo) 868 .addOperand(MI->getOperand(1))); 869 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi) 870 .addReg(RegHi) 871 .addImm(0)); 872 873 llvm::finalizeBundle(MBB, Bundler.begin()); 874 875 MI->eraseFromParent(); 876 break; 877 } 878 } 879 return true; 880 } 881 882 /// Commutes the operands in the given instruction. 883 /// The commutable operands are specified by their indices OpIdx0 and OpIdx1. 884 /// 885 /// Do not call this method for a non-commutable instruction or for 886 /// non-commutable pair of operand indices OpIdx0 and OpIdx1. 887 /// Even though the instruction is commutable, the method may still 888 /// fail to commute the operands, null pointer is returned in such cases. 889 MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr *MI, 890 bool NewMI, 891 unsigned OpIdx0, 892 unsigned OpIdx1) const { 893 int CommutedOpcode = commuteOpcode(*MI); 894 if (CommutedOpcode == -1) 895 return nullptr; 896 897 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), 898 AMDGPU::OpName::src0); 899 MachineOperand &Src0 = MI->getOperand(Src0Idx); 900 if (!Src0.isReg()) 901 return nullptr; 902 903 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), 904 AMDGPU::OpName::src1); 905 906 if ((OpIdx0 != static_cast<unsigned>(Src0Idx) || 907 OpIdx1 != static_cast<unsigned>(Src1Idx)) && 908 (OpIdx0 != static_cast<unsigned>(Src1Idx) || 909 OpIdx1 != static_cast<unsigned>(Src0Idx))) 910 return nullptr; 911 912 MachineOperand &Src1 = MI->getOperand(Src1Idx); 913 914 915 if (isVOP2(*MI)) { 916 const MCInstrDesc &InstrDesc = MI->getDesc(); 917 // For VOP2 instructions, any operand type is valid to use for src0. Make 918 // sure we can use the src1 as src0. 919 // 920 // We could be stricter here and only allow commuting if there is a reason 921 // to do so. i.e. if both operands are VGPRs there is no real benefit, 922 // although MachineCSE attempts to find matches by commuting. 923 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 924 if (!isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0)) 925 return nullptr; 926 } 927 928 if (!Src1.isReg()) { 929 // Allow commuting instructions with Imm operands. 930 if (NewMI || !Src1.isImm() || 931 (!isVOP2(*MI) && !isVOP3(*MI))) { 932 return nullptr; 933 } 934 // Be sure to copy the source modifiers to the right place. 935 if (MachineOperand *Src0Mods 936 = getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) { 937 MachineOperand *Src1Mods 938 = getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers); 939 940 int Src0ModsVal = Src0Mods->getImm(); 941 if (!Src1Mods && Src0ModsVal != 0) 942 return nullptr; 943 944 // XXX - This assert might be a lie. It might be useful to have a neg 945 // modifier with 0.0. 946 int Src1ModsVal = Src1Mods->getImm(); 947 assert((Src1ModsVal == 0) && "Not expecting modifiers with immediates"); 948 949 Src1Mods->setImm(Src0ModsVal); 950 Src0Mods->setImm(Src1ModsVal); 951 } 952 953 unsigned Reg = Src0.getReg(); 954 unsigned SubReg = Src0.getSubReg(); 955 if (Src1.isImm()) 956 Src0.ChangeToImmediate(Src1.getImm()); 957 else 958 llvm_unreachable("Should only have immediates"); 959 960 Src1.ChangeToRegister(Reg, false); 961 Src1.setSubReg(SubReg); 962 } else { 963 MI = TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx0, OpIdx1); 964 } 965 966 if (MI) 967 MI->setDesc(get(CommutedOpcode)); 968 969 return MI; 970 } 971 972 // This needs to be implemented because the source modifiers may be inserted 973 // between the true commutable operands, and the base 974 // TargetInstrInfo::commuteInstruction uses it. 975 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI, 976 unsigned &SrcOpIdx0, 977 unsigned &SrcOpIdx1) const { 978 const MCInstrDesc &MCID = MI->getDesc(); 979 if (!MCID.isCommutable()) 980 return false; 981 982 unsigned Opc = MI->getOpcode(); 983 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); 984 if (Src0Idx == -1) 985 return false; 986 987 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on 988 // immediate. Also, immediate src0 operand is not handled in 989 // SIInstrInfo::commuteInstruction(); 990 if (!MI->getOperand(Src0Idx).isReg()) 991 return false; 992 993 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1); 994 if (Src1Idx == -1) 995 return false; 996 997 MachineOperand &Src1 = MI->getOperand(Src1Idx); 998 if (Src1.isImm()) { 999 // SIInstrInfo::commuteInstruction() does support commuting the immediate 1000 // operand src1 in 2 and 3 operand instructions. 1001 if (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode())) 1002 return false; 1003 } else if (Src1.isReg()) { 1004 // If any source modifiers are set, the generic instruction commuting won't 1005 // understand how to copy the source modifiers. 1006 if (hasModifiersSet(*MI, AMDGPU::OpName::src0_modifiers) || 1007 hasModifiersSet(*MI, AMDGPU::OpName::src1_modifiers)) 1008 return false; 1009 } else 1010 return false; 1011 1012 return fixCommutedOpIndices(SrcOpIdx0, SrcOpIdx1, Src0Idx, Src1Idx); 1013 } 1014 1015 static void removeModOperands(MachineInstr &MI) { 1016 unsigned Opc = MI.getOpcode(); 1017 int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc, 1018 AMDGPU::OpName::src0_modifiers); 1019 int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc, 1020 AMDGPU::OpName::src1_modifiers); 1021 int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc, 1022 AMDGPU::OpName::src2_modifiers); 1023 1024 MI.RemoveOperand(Src2ModIdx); 1025 MI.RemoveOperand(Src1ModIdx); 1026 MI.RemoveOperand(Src0ModIdx); 1027 } 1028 1029 bool SIInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 1030 unsigned Reg, MachineRegisterInfo *MRI) const { 1031 if (!MRI->hasOneNonDBGUse(Reg)) 1032 return false; 1033 1034 unsigned Opc = UseMI->getOpcode(); 1035 if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64) { 1036 // Don't fold if we are using source modifiers. The new VOP2 instructions 1037 // don't have them. 1038 if (hasModifiersSet(*UseMI, AMDGPU::OpName::src0_modifiers) || 1039 hasModifiersSet(*UseMI, AMDGPU::OpName::src1_modifiers) || 1040 hasModifiersSet(*UseMI, AMDGPU::OpName::src2_modifiers)) { 1041 return false; 1042 } 1043 1044 MachineOperand *Src0 = getNamedOperand(*UseMI, AMDGPU::OpName::src0); 1045 MachineOperand *Src1 = getNamedOperand(*UseMI, AMDGPU::OpName::src1); 1046 MachineOperand *Src2 = getNamedOperand(*UseMI, AMDGPU::OpName::src2); 1047 1048 // Multiplied part is the constant: Use v_madmk_f32 1049 // We should only expect these to be on src0 due to canonicalizations. 1050 if (Src0->isReg() && Src0->getReg() == Reg) { 1051 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))) 1052 return false; 1053 1054 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))) 1055 return false; 1056 1057 // We need to do some weird looking operand shuffling since the madmk 1058 // operands are out of the normal expected order with the multiplied 1059 // constant as the last operand. 1060 // 1061 // v_mad_f32 src0, src1, src2 -> v_madmk_f32 src0 * src2K + src1 1062 // src0 -> src2 K 1063 // src1 -> src0 1064 // src2 -> src1 1065 1066 const int64_t Imm = DefMI->getOperand(1).getImm(); 1067 1068 // FIXME: This would be a lot easier if we could return a new instruction 1069 // instead of having to modify in place. 1070 1071 // Remove these first since they are at the end. 1072 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc, 1073 AMDGPU::OpName::omod)); 1074 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc, 1075 AMDGPU::OpName::clamp)); 1076 1077 unsigned Src1Reg = Src1->getReg(); 1078 unsigned Src1SubReg = Src1->getSubReg(); 1079 unsigned Src2Reg = Src2->getReg(); 1080 unsigned Src2SubReg = Src2->getSubReg(); 1081 Src0->setReg(Src1Reg); 1082 Src0->setSubReg(Src1SubReg); 1083 Src0->setIsKill(Src1->isKill()); 1084 1085 Src1->setReg(Src2Reg); 1086 Src1->setSubReg(Src2SubReg); 1087 Src1->setIsKill(Src2->isKill()); 1088 1089 if (Opc == AMDGPU::V_MAC_F32_e64) { 1090 UseMI->untieRegOperand( 1091 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)); 1092 } 1093 1094 Src2->ChangeToImmediate(Imm); 1095 1096 removeModOperands(*UseMI); 1097 UseMI->setDesc(get(AMDGPU::V_MADMK_F32)); 1098 1099 bool DeleteDef = MRI->hasOneNonDBGUse(Reg); 1100 if (DeleteDef) 1101 DefMI->eraseFromParent(); 1102 1103 return true; 1104 } 1105 1106 // Added part is the constant: Use v_madak_f32 1107 if (Src2->isReg() && Src2->getReg() == Reg) { 1108 // Not allowed to use constant bus for another operand. 1109 // We can however allow an inline immediate as src0. 1110 if (!Src0->isImm() && 1111 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))) 1112 return false; 1113 1114 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))) 1115 return false; 1116 1117 const int64_t Imm = DefMI->getOperand(1).getImm(); 1118 1119 // FIXME: This would be a lot easier if we could return a new instruction 1120 // instead of having to modify in place. 1121 1122 // Remove these first since they are at the end. 1123 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc, 1124 AMDGPU::OpName::omod)); 1125 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc, 1126 AMDGPU::OpName::clamp)); 1127 1128 if (Opc == AMDGPU::V_MAC_F32_e64) { 1129 UseMI->untieRegOperand( 1130 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)); 1131 } 1132 1133 // ChangingToImmediate adds Src2 back to the instruction. 1134 Src2->ChangeToImmediate(Imm); 1135 1136 // These come before src2. 1137 removeModOperands(*UseMI); 1138 UseMI->setDesc(get(AMDGPU::V_MADAK_F32)); 1139 1140 bool DeleteDef = MRI->hasOneNonDBGUse(Reg); 1141 if (DeleteDef) 1142 DefMI->eraseFromParent(); 1143 1144 return true; 1145 } 1146 } 1147 1148 return false; 1149 } 1150 1151 static bool offsetsDoNotOverlap(int WidthA, int OffsetA, 1152 int WidthB, int OffsetB) { 1153 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB; 1154 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA; 1155 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB; 1156 return LowOffset + LowWidth <= HighOffset; 1157 } 1158 1159 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa, 1160 MachineInstr *MIb) const { 1161 unsigned BaseReg0, Offset0; 1162 unsigned BaseReg1, Offset1; 1163 1164 if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) && 1165 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) { 1166 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() && 1167 "read2 / write2 not expected here yet"); 1168 unsigned Width0 = (*MIa->memoperands_begin())->getSize(); 1169 unsigned Width1 = (*MIb->memoperands_begin())->getSize(); 1170 if (BaseReg0 == BaseReg1 && 1171 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) { 1172 return true; 1173 } 1174 } 1175 1176 return false; 1177 } 1178 1179 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa, 1180 MachineInstr *MIb, 1181 AliasAnalysis *AA) const { 1182 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) && 1183 "MIa must load from or modify a memory location"); 1184 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) && 1185 "MIb must load from or modify a memory location"); 1186 1187 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects()) 1188 return false; 1189 1190 // XXX - Can we relax this between address spaces? 1191 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef()) 1192 return false; 1193 1194 // TODO: Should we check the address space from the MachineMemOperand? That 1195 // would allow us to distinguish objects we know don't alias based on the 1196 // underlying address space, even if it was lowered to a different one, 1197 // e.g. private accesses lowered to use MUBUF instructions on a scratch 1198 // buffer. 1199 if (isDS(*MIa)) { 1200 if (isDS(*MIb)) 1201 return checkInstOffsetsDoNotOverlap(MIa, MIb); 1202 1203 return !isFLAT(*MIb); 1204 } 1205 1206 if (isMUBUF(*MIa) || isMTBUF(*MIa)) { 1207 if (isMUBUF(*MIb) || isMTBUF(*MIb)) 1208 return checkInstOffsetsDoNotOverlap(MIa, MIb); 1209 1210 return !isFLAT(*MIb) && !isSMRD(*MIb); 1211 } 1212 1213 if (isSMRD(*MIa)) { 1214 if (isSMRD(*MIb)) 1215 return checkInstOffsetsDoNotOverlap(MIa, MIb); 1216 1217 return !isFLAT(*MIb) && !isMUBUF(*MIa) && !isMTBUF(*MIa); 1218 } 1219 1220 if (isFLAT(*MIa)) { 1221 if (isFLAT(*MIb)) 1222 return checkInstOffsetsDoNotOverlap(MIa, MIb); 1223 1224 return false; 1225 } 1226 1227 return false; 1228 } 1229 1230 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB, 1231 MachineBasicBlock::iterator &MI, 1232 LiveVariables *LV) const { 1233 1234 switch (MI->getOpcode()) { 1235 default: return nullptr; 1236 case AMDGPU::V_MAC_F32_e64: break; 1237 case AMDGPU::V_MAC_F32_e32: { 1238 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0); 1239 if (Src0->isImm() && !isInlineConstant(*Src0, 4)) 1240 return nullptr; 1241 break; 1242 } 1243 } 1244 1245 const MachineOperand *Dst = getNamedOperand(*MI, AMDGPU::OpName::vdst); 1246 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0); 1247 const MachineOperand *Src1 = getNamedOperand(*MI, AMDGPU::OpName::src1); 1248 const MachineOperand *Src2 = getNamedOperand(*MI, AMDGPU::OpName::src2); 1249 1250 return BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_MAD_F32)) 1251 .addOperand(*Dst) 1252 .addImm(0) // Src0 mods 1253 .addOperand(*Src0) 1254 .addImm(0) // Src1 mods 1255 .addOperand(*Src1) 1256 .addImm(0) // Src mods 1257 .addOperand(*Src2) 1258 .addImm(0) // clamp 1259 .addImm(0); // omod 1260 } 1261 1262 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const { 1263 int64_t SVal = Imm.getSExtValue(); 1264 if (SVal >= -16 && SVal <= 64) 1265 return true; 1266 1267 if (Imm.getBitWidth() == 64) { 1268 uint64_t Val = Imm.getZExtValue(); 1269 return (DoubleToBits(0.0) == Val) || 1270 (DoubleToBits(1.0) == Val) || 1271 (DoubleToBits(-1.0) == Val) || 1272 (DoubleToBits(0.5) == Val) || 1273 (DoubleToBits(-0.5) == Val) || 1274 (DoubleToBits(2.0) == Val) || 1275 (DoubleToBits(-2.0) == Val) || 1276 (DoubleToBits(4.0) == Val) || 1277 (DoubleToBits(-4.0) == Val); 1278 } 1279 1280 // The actual type of the operand does not seem to matter as long 1281 // as the bits match one of the inline immediate values. For example: 1282 // 1283 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal, 1284 // so it is a legal inline immediate. 1285 // 1286 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in 1287 // floating-point, so it is a legal inline immediate. 1288 uint32_t Val = Imm.getZExtValue(); 1289 1290 return (FloatToBits(0.0f) == Val) || 1291 (FloatToBits(1.0f) == Val) || 1292 (FloatToBits(-1.0f) == Val) || 1293 (FloatToBits(0.5f) == Val) || 1294 (FloatToBits(-0.5f) == Val) || 1295 (FloatToBits(2.0f) == Val) || 1296 (FloatToBits(-2.0f) == Val) || 1297 (FloatToBits(4.0f) == Val) || 1298 (FloatToBits(-4.0f) == Val); 1299 } 1300 1301 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO, 1302 unsigned OpSize) const { 1303 if (MO.isImm()) { 1304 // MachineOperand provides no way to tell the true operand size, since it 1305 // only records a 64-bit value. We need to know the size to determine if a 1306 // 32-bit floating point immediate bit pattern is legal for an integer 1307 // immediate. It would be for any 32-bit integer operand, but would not be 1308 // for a 64-bit one. 1309 1310 unsigned BitSize = 8 * OpSize; 1311 return isInlineConstant(APInt(BitSize, MO.getImm(), true)); 1312 } 1313 1314 return false; 1315 } 1316 1317 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO, 1318 unsigned OpSize) const { 1319 return MO.isImm() && !isInlineConstant(MO, OpSize); 1320 } 1321 1322 static bool compareMachineOp(const MachineOperand &Op0, 1323 const MachineOperand &Op1) { 1324 if (Op0.getType() != Op1.getType()) 1325 return false; 1326 1327 switch (Op0.getType()) { 1328 case MachineOperand::MO_Register: 1329 return Op0.getReg() == Op1.getReg(); 1330 case MachineOperand::MO_Immediate: 1331 return Op0.getImm() == Op1.getImm(); 1332 default: 1333 llvm_unreachable("Didn't expect to be comparing these operand types"); 1334 } 1335 } 1336 1337 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo, 1338 const MachineOperand &MO) const { 1339 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo]; 1340 1341 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI()); 1342 1343 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE) 1344 return true; 1345 1346 if (OpInfo.RegClass < 0) 1347 return false; 1348 1349 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize(); 1350 if (isLiteralConstant(MO, OpSize)) 1351 return RI.opCanUseLiteralConstant(OpInfo.OperandType); 1352 1353 return RI.opCanUseInlineConstant(OpInfo.OperandType); 1354 } 1355 1356 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const { 1357 int Op32 = AMDGPU::getVOPe32(Opcode); 1358 if (Op32 == -1) 1359 return false; 1360 1361 return pseudoToMCOpcode(Op32) != -1; 1362 } 1363 1364 bool SIInstrInfo::hasModifiers(unsigned Opcode) const { 1365 // The src0_modifier operand is present on all instructions 1366 // that have modifiers. 1367 1368 return AMDGPU::getNamedOperandIdx(Opcode, 1369 AMDGPU::OpName::src0_modifiers) != -1; 1370 } 1371 1372 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI, 1373 unsigned OpName) const { 1374 const MachineOperand *Mods = getNamedOperand(MI, OpName); 1375 return Mods && Mods->getImm(); 1376 } 1377 1378 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI, 1379 const MachineOperand &MO, 1380 unsigned OpSize) const { 1381 // Literal constants use the constant bus. 1382 if (isLiteralConstant(MO, OpSize)) 1383 return true; 1384 1385 if (!MO.isReg() || !MO.isUse()) 1386 return false; 1387 1388 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) 1389 return RI.isSGPRClass(MRI.getRegClass(MO.getReg())); 1390 1391 // FLAT_SCR is just an SGPR pair. 1392 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR)) 1393 return true; 1394 1395 // EXEC register uses the constant bus. 1396 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC) 1397 return true; 1398 1399 // SGPRs use the constant bus 1400 return (MO.getReg() == AMDGPU::VCC || MO.getReg() == AMDGPU::M0 || 1401 (!MO.isImplicit() && 1402 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) || 1403 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))); 1404 } 1405 1406 static unsigned findImplicitSGPRRead(const MachineInstr &MI) { 1407 for (const MachineOperand &MO : MI.implicit_operands()) { 1408 // We only care about reads. 1409 if (MO.isDef()) 1410 continue; 1411 1412 switch (MO.getReg()) { 1413 case AMDGPU::VCC: 1414 case AMDGPU::M0: 1415 case AMDGPU::FLAT_SCR: 1416 return MO.getReg(); 1417 1418 default: 1419 break; 1420 } 1421 } 1422 1423 return AMDGPU::NoRegister; 1424 } 1425 1426 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI, 1427 StringRef &ErrInfo) const { 1428 uint16_t Opcode = MI->getOpcode(); 1429 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 1430 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); 1431 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); 1432 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2); 1433 1434 // Make sure we don't have SCC live-ins to basic blocks. moveToVALU assumes 1435 // all SCC users are in the same blocks as their defs. 1436 const MachineBasicBlock *MBB = MI->getParent(); 1437 if (MI == &MBB->front()) { 1438 if (MBB->isLiveIn(AMDGPU::SCC)) { 1439 ErrInfo = "scc register cannot be live across blocks."; 1440 return false; 1441 } 1442 } 1443 1444 // Make sure the number of operands is correct. 1445 const MCInstrDesc &Desc = get(Opcode); 1446 if (!Desc.isVariadic() && 1447 Desc.getNumOperands() != MI->getNumExplicitOperands()) { 1448 ErrInfo = "Instruction has wrong number of operands."; 1449 return false; 1450 } 1451 1452 // Make sure the register classes are correct. 1453 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) { 1454 if (MI->getOperand(i).isFPImm()) { 1455 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast " 1456 "all fp values to integers."; 1457 return false; 1458 } 1459 1460 int RegClass = Desc.OpInfo[i].RegClass; 1461 1462 switch (Desc.OpInfo[i].OperandType) { 1463 case MCOI::OPERAND_REGISTER: 1464 if (MI->getOperand(i).isImm()) { 1465 ErrInfo = "Illegal immediate value for operand."; 1466 return false; 1467 } 1468 break; 1469 case AMDGPU::OPERAND_REG_IMM32: 1470 break; 1471 case AMDGPU::OPERAND_REG_INLINE_C: 1472 if (isLiteralConstant(MI->getOperand(i), 1473 RI.getRegClass(RegClass)->getSize())) { 1474 ErrInfo = "Illegal immediate value for operand."; 1475 return false; 1476 } 1477 break; 1478 case MCOI::OPERAND_IMMEDIATE: 1479 // Check if this operand is an immediate. 1480 // FrameIndex operands will be replaced by immediates, so they are 1481 // allowed. 1482 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFI()) { 1483 ErrInfo = "Expected immediate, but got non-immediate"; 1484 return false; 1485 } 1486 // Fall-through 1487 default: 1488 continue; 1489 } 1490 1491 if (!MI->getOperand(i).isReg()) 1492 continue; 1493 1494 if (RegClass != -1) { 1495 unsigned Reg = MI->getOperand(i).getReg(); 1496 if (TargetRegisterInfo::isVirtualRegister(Reg)) 1497 continue; 1498 1499 const TargetRegisterClass *RC = RI.getRegClass(RegClass); 1500 if (!RC->contains(Reg)) { 1501 ErrInfo = "Operand has incorrect register class."; 1502 return false; 1503 } 1504 } 1505 } 1506 1507 1508 // Verify VOP* 1509 if (isVOP1(*MI) || isVOP2(*MI) || isVOP3(*MI) || isVOPC(*MI)) { 1510 // Only look at the true operands. Only a real operand can use the constant 1511 // bus, and we don't want to check pseudo-operands like the source modifier 1512 // flags. 1513 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx }; 1514 1515 unsigned ConstantBusCount = 0; 1516 unsigned SGPRUsed = findImplicitSGPRRead(*MI); 1517 if (SGPRUsed != AMDGPU::NoRegister) 1518 ++ConstantBusCount; 1519 1520 for (int OpIdx : OpIndices) { 1521 if (OpIdx == -1) 1522 break; 1523 const MachineOperand &MO = MI->getOperand(OpIdx); 1524 if (usesConstantBus(MRI, MO, getOpSize(Opcode, OpIdx))) { 1525 if (MO.isReg()) { 1526 if (MO.getReg() != SGPRUsed) 1527 ++ConstantBusCount; 1528 SGPRUsed = MO.getReg(); 1529 } else { 1530 ++ConstantBusCount; 1531 } 1532 } 1533 } 1534 if (ConstantBusCount > 1) { 1535 ErrInfo = "VOP* instruction uses the constant bus more than once"; 1536 return false; 1537 } 1538 } 1539 1540 // Verify misc. restrictions on specific instructions. 1541 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 || 1542 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) { 1543 const MachineOperand &Src0 = MI->getOperand(Src0Idx); 1544 const MachineOperand &Src1 = MI->getOperand(Src1Idx); 1545 const MachineOperand &Src2 = MI->getOperand(Src2Idx); 1546 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) { 1547 if (!compareMachineOp(Src0, Src1) && 1548 !compareMachineOp(Src0, Src2)) { 1549 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2"; 1550 return false; 1551 } 1552 } 1553 } 1554 1555 // Make sure we aren't losing exec uses in the td files. This mostly requires 1556 // being careful when using let Uses to try to add other use registers. 1557 if (!isGenericOpcode(Opcode) && !isSALU(Opcode) && !isSMRD(Opcode)) { 1558 const MachineOperand *Exec = MI->findRegisterUseOperand(AMDGPU::EXEC); 1559 if (!Exec || !Exec->isImplicit()) { 1560 ErrInfo = "VALU instruction does not implicitly read exec mask"; 1561 return false; 1562 } 1563 } 1564 1565 return true; 1566 } 1567 1568 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) { 1569 switch (MI.getOpcode()) { 1570 default: return AMDGPU::INSTRUCTION_LIST_END; 1571 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE; 1572 case AMDGPU::COPY: return AMDGPU::COPY; 1573 case AMDGPU::PHI: return AMDGPU::PHI; 1574 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG; 1575 case AMDGPU::S_MOV_B32: 1576 return MI.getOperand(1).isReg() ? 1577 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32; 1578 case AMDGPU::S_ADD_I32: 1579 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32; 1580 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32; 1581 case AMDGPU::S_SUB_I32: 1582 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32; 1583 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32; 1584 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32; 1585 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32; 1586 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32; 1587 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32; 1588 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32; 1589 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32; 1590 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32; 1591 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32; 1592 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32; 1593 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64; 1594 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32; 1595 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64; 1596 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32; 1597 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64; 1598 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32; 1599 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32; 1600 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32; 1601 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32; 1602 case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64; 1603 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32; 1604 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32; 1605 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32; 1606 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32; 1607 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32; 1608 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32; 1609 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32; 1610 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32; 1611 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32; 1612 case AMDGPU::S_CMP_EQ_U32: return AMDGPU::V_CMP_EQ_U32_e32; 1613 case AMDGPU::S_CMP_LG_U32: return AMDGPU::V_CMP_NE_U32_e32; 1614 case AMDGPU::S_CMP_GT_U32: return AMDGPU::V_CMP_GT_U32_e32; 1615 case AMDGPU::S_CMP_GE_U32: return AMDGPU::V_CMP_GE_U32_e32; 1616 case AMDGPU::S_CMP_LT_U32: return AMDGPU::V_CMP_LT_U32_e32; 1617 case AMDGPU::S_CMP_LE_U32: return AMDGPU::V_CMP_LE_U32_e32; 1618 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64; 1619 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32; 1620 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32; 1621 case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64; 1622 case AMDGPU::S_CBRANCH_SCC0: return AMDGPU::S_CBRANCH_VCCZ; 1623 case AMDGPU::S_CBRANCH_SCC1: return AMDGPU::S_CBRANCH_VCCNZ; 1624 } 1625 } 1626 1627 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const { 1628 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END; 1629 } 1630 1631 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI, 1632 unsigned OpNo) const { 1633 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); 1634 const MCInstrDesc &Desc = get(MI.getOpcode()); 1635 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() || 1636 Desc.OpInfo[OpNo].RegClass == -1) { 1637 unsigned Reg = MI.getOperand(OpNo).getReg(); 1638 1639 if (TargetRegisterInfo::isVirtualRegister(Reg)) 1640 return MRI.getRegClass(Reg); 1641 return RI.getPhysRegClass(Reg); 1642 } 1643 1644 unsigned RCID = Desc.OpInfo[OpNo].RegClass; 1645 return RI.getRegClass(RCID); 1646 } 1647 1648 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const { 1649 switch (MI.getOpcode()) { 1650 case AMDGPU::COPY: 1651 case AMDGPU::REG_SEQUENCE: 1652 case AMDGPU::PHI: 1653 case AMDGPU::INSERT_SUBREG: 1654 return RI.hasVGPRs(getOpRegClass(MI, 0)); 1655 default: 1656 return RI.hasVGPRs(getOpRegClass(MI, OpNo)); 1657 } 1658 } 1659 1660 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const { 1661 MachineBasicBlock::iterator I = MI; 1662 MachineBasicBlock *MBB = MI->getParent(); 1663 MachineOperand &MO = MI->getOperand(OpIdx); 1664 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 1665 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass; 1666 const TargetRegisterClass *RC = RI.getRegClass(RCID); 1667 unsigned Opcode = AMDGPU::V_MOV_B32_e32; 1668 if (MO.isReg()) 1669 Opcode = AMDGPU::COPY; 1670 else if (RI.isSGPRClass(RC)) 1671 Opcode = AMDGPU::S_MOV_B32; 1672 1673 1674 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC); 1675 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC)) 1676 VRC = &AMDGPU::VReg_64RegClass; 1677 else 1678 VRC = &AMDGPU::VGPR_32RegClass; 1679 1680 unsigned Reg = MRI.createVirtualRegister(VRC); 1681 DebugLoc DL = MBB->findDebugLoc(I); 1682 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg) 1683 .addOperand(MO); 1684 MO.ChangeToRegister(Reg, false); 1685 } 1686 1687 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI, 1688 MachineRegisterInfo &MRI, 1689 MachineOperand &SuperReg, 1690 const TargetRegisterClass *SuperRC, 1691 unsigned SubIdx, 1692 const TargetRegisterClass *SubRC) 1693 const { 1694 MachineBasicBlock *MBB = MI->getParent(); 1695 DebugLoc DL = MI->getDebugLoc(); 1696 unsigned SubReg = MRI.createVirtualRegister(SubRC); 1697 1698 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) { 1699 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg) 1700 .addReg(SuperReg.getReg(), 0, SubIdx); 1701 return SubReg; 1702 } 1703 1704 // Just in case the super register is itself a sub-register, copy it to a new 1705 // value so we don't need to worry about merging its subreg index with the 1706 // SubIdx passed to this function. The register coalescer should be able to 1707 // eliminate this extra copy. 1708 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC); 1709 1710 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg) 1711 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg()); 1712 1713 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg) 1714 .addReg(NewSuperReg, 0, SubIdx); 1715 1716 return SubReg; 1717 } 1718 1719 MachineOperand SIInstrInfo::buildExtractSubRegOrImm( 1720 MachineBasicBlock::iterator MII, 1721 MachineRegisterInfo &MRI, 1722 MachineOperand &Op, 1723 const TargetRegisterClass *SuperRC, 1724 unsigned SubIdx, 1725 const TargetRegisterClass *SubRC) const { 1726 if (Op.isImm()) { 1727 // XXX - Is there a better way to do this? 1728 if (SubIdx == AMDGPU::sub0) 1729 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF); 1730 if (SubIdx == AMDGPU::sub1) 1731 return MachineOperand::CreateImm(Op.getImm() >> 32); 1732 1733 llvm_unreachable("Unhandled register index for immediate"); 1734 } 1735 1736 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, 1737 SubIdx, SubRC); 1738 return MachineOperand::CreateReg(SubReg, false); 1739 } 1740 1741 // Change the order of operands from (0, 1, 2) to (0, 2, 1) 1742 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const { 1743 assert(Inst->getNumExplicitOperands() == 3); 1744 MachineOperand Op1 = Inst->getOperand(1); 1745 Inst->RemoveOperand(1); 1746 Inst->addOperand(Op1); 1747 } 1748 1749 bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI, 1750 const MCOperandInfo &OpInfo, 1751 const MachineOperand &MO) const { 1752 if (!MO.isReg()) 1753 return false; 1754 1755 unsigned Reg = MO.getReg(); 1756 const TargetRegisterClass *RC = 1757 TargetRegisterInfo::isVirtualRegister(Reg) ? 1758 MRI.getRegClass(Reg) : 1759 RI.getPhysRegClass(Reg); 1760 1761 const SIRegisterInfo *TRI = 1762 static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo()); 1763 RC = TRI->getSubRegClass(RC, MO.getSubReg()); 1764 1765 // In order to be legal, the common sub-class must be equal to the 1766 // class of the current operand. For example: 1767 // 1768 // v_mov_b32 s0 ; Operand defined as vsrc_32 1769 // ; RI.getCommonSubClass(s0,vsrc_32) = sgpr ; LEGAL 1770 // 1771 // s_sendmsg 0, s0 ; Operand defined as m0reg 1772 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL 1773 1774 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC; 1775 } 1776 1777 bool SIInstrInfo::isLegalVSrcOperand(const MachineRegisterInfo &MRI, 1778 const MCOperandInfo &OpInfo, 1779 const MachineOperand &MO) const { 1780 if (MO.isReg()) 1781 return isLegalRegOperand(MRI, OpInfo, MO); 1782 1783 // Handle non-register types that are treated like immediates. 1784 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI()); 1785 return true; 1786 } 1787 1788 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx, 1789 const MachineOperand *MO) const { 1790 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 1791 const MCInstrDesc &InstDesc = MI->getDesc(); 1792 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx]; 1793 const TargetRegisterClass *DefinedRC = 1794 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr; 1795 if (!MO) 1796 MO = &MI->getOperand(OpIdx); 1797 1798 if (isVALU(*MI) && 1799 usesConstantBus(MRI, *MO, DefinedRC->getSize())) { 1800 1801 RegSubRegPair SGPRUsed; 1802 if (MO->isReg()) 1803 SGPRUsed = RegSubRegPair(MO->getReg(), MO->getSubReg()); 1804 1805 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1806 if (i == OpIdx) 1807 continue; 1808 const MachineOperand &Op = MI->getOperand(i); 1809 if (Op.isReg() && 1810 (Op.getReg() != SGPRUsed.Reg || Op.getSubReg() != SGPRUsed.SubReg) && 1811 usesConstantBus(MRI, Op, getOpSize(*MI, i))) { 1812 return false; 1813 } 1814 } 1815 } 1816 1817 if (MO->isReg()) { 1818 assert(DefinedRC); 1819 return isLegalRegOperand(MRI, OpInfo, *MO); 1820 } 1821 1822 1823 // Handle non-register types that are treated like immediates. 1824 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI()); 1825 1826 if (!DefinedRC) { 1827 // This operand expects an immediate. 1828 return true; 1829 } 1830 1831 return isImmOperandLegal(MI, OpIdx, *MO); 1832 } 1833 1834 void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI, 1835 MachineInstr *MI) const { 1836 unsigned Opc = MI->getOpcode(); 1837 const MCInstrDesc &InstrDesc = get(Opc); 1838 1839 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1); 1840 MachineOperand &Src1 = MI->getOperand(Src1Idx); 1841 1842 // If there is an implicit SGPR use such as VCC use for v_addc_u32/v_subb_u32 1843 // we need to only have one constant bus use. 1844 // 1845 // Note we do not need to worry about literal constants here. They are 1846 // disabled for the operand type for instructions because they will always 1847 // violate the one constant bus use rule. 1848 bool HasImplicitSGPR = findImplicitSGPRRead(*MI) != AMDGPU::NoRegister; 1849 if (HasImplicitSGPR) { 1850 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); 1851 MachineOperand &Src0 = MI->getOperand(Src0Idx); 1852 1853 if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg())) 1854 legalizeOpWithMove(MI, Src0Idx); 1855 } 1856 1857 // VOP2 src0 instructions support all operand types, so we don't need to check 1858 // their legality. If src1 is already legal, we don't need to do anything. 1859 if (isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src1)) 1860 return; 1861 1862 // We do not use commuteInstruction here because it is too aggressive and will 1863 // commute if it is possible. We only want to commute here if it improves 1864 // legality. This can be called a fairly large number of times so don't waste 1865 // compile time pointlessly swapping and checking legality again. 1866 if (HasImplicitSGPR || !MI->isCommutable()) { 1867 legalizeOpWithMove(MI, Src1Idx); 1868 return; 1869 } 1870 1871 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); 1872 MachineOperand &Src0 = MI->getOperand(Src0Idx); 1873 1874 // If src0 can be used as src1, commuting will make the operands legal. 1875 // Otherwise we have to give up and insert a move. 1876 // 1877 // TODO: Other immediate-like operand kinds could be commuted if there was a 1878 // MachineOperand::ChangeTo* for them. 1879 if ((!Src1.isImm() && !Src1.isReg()) || 1880 !isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0)) { 1881 legalizeOpWithMove(MI, Src1Idx); 1882 return; 1883 } 1884 1885 int CommutedOpc = commuteOpcode(*MI); 1886 if (CommutedOpc == -1) { 1887 legalizeOpWithMove(MI, Src1Idx); 1888 return; 1889 } 1890 1891 MI->setDesc(get(CommutedOpc)); 1892 1893 unsigned Src0Reg = Src0.getReg(); 1894 unsigned Src0SubReg = Src0.getSubReg(); 1895 bool Src0Kill = Src0.isKill(); 1896 1897 if (Src1.isImm()) 1898 Src0.ChangeToImmediate(Src1.getImm()); 1899 else if (Src1.isReg()) { 1900 Src0.ChangeToRegister(Src1.getReg(), false, false, Src1.isKill()); 1901 Src0.setSubReg(Src1.getSubReg()); 1902 } else 1903 llvm_unreachable("Should only have register or immediate operands"); 1904 1905 Src1.ChangeToRegister(Src0Reg, false, false, Src0Kill); 1906 Src1.setSubReg(Src0SubReg); 1907 } 1908 1909 // Legalize VOP3 operands. Because all operand types are supported for any 1910 // operand, and since literal constants are not allowed and should never be 1911 // seen, we only need to worry about inserting copies if we use multiple SGPR 1912 // operands. 1913 void SIInstrInfo::legalizeOperandsVOP3( 1914 MachineRegisterInfo &MRI, 1915 MachineInstr *MI) const { 1916 unsigned Opc = MI->getOpcode(); 1917 1918 int VOP3Idx[3] = { 1919 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0), 1920 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1), 1921 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2) 1922 }; 1923 1924 // Find the one SGPR operand we are allowed to use. 1925 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx); 1926 1927 for (unsigned i = 0; i < 3; ++i) { 1928 int Idx = VOP3Idx[i]; 1929 if (Idx == -1) 1930 break; 1931 MachineOperand &MO = MI->getOperand(Idx); 1932 1933 // We should never see a VOP3 instruction with an illegal immediate operand. 1934 if (!MO.isReg()) 1935 continue; 1936 1937 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg()))) 1938 continue; // VGPRs are legal 1939 1940 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) { 1941 SGPRReg = MO.getReg(); 1942 // We can use one SGPR in each VOP3 instruction. 1943 continue; 1944 } 1945 1946 // If we make it this far, then the operand is not legal and we must 1947 // legalize it. 1948 legalizeOpWithMove(MI, Idx); 1949 } 1950 } 1951 1952 unsigned SIInstrInfo::readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr *UseMI, 1953 MachineRegisterInfo &MRI) const { 1954 const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg); 1955 const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC); 1956 unsigned DstReg = MRI.createVirtualRegister(SRC); 1957 unsigned SubRegs = VRC->getSize() / 4; 1958 1959 SmallVector<unsigned, 8> SRegs; 1960 for (unsigned i = 0; i < SubRegs; ++i) { 1961 unsigned SGPR = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); 1962 BuildMI(*UseMI->getParent(), UseMI, UseMI->getDebugLoc(), 1963 get(AMDGPU::V_READFIRSTLANE_B32), SGPR) 1964 .addReg(SrcReg, 0, RI.getSubRegFromChannel(i)); 1965 SRegs.push_back(SGPR); 1966 } 1967 1968 MachineInstrBuilder MIB = BuildMI(*UseMI->getParent(), UseMI, 1969 UseMI->getDebugLoc(), 1970 get(AMDGPU::REG_SEQUENCE), DstReg); 1971 for (unsigned i = 0; i < SubRegs; ++i) { 1972 MIB.addReg(SRegs[i]); 1973 MIB.addImm(RI.getSubRegFromChannel(i)); 1974 } 1975 return DstReg; 1976 } 1977 1978 void SIInstrInfo::legalizeOperandsSMRD(MachineRegisterInfo &MRI, 1979 MachineInstr *MI) const { 1980 1981 // If the pointer is store in VGPRs, then we need to move them to 1982 // SGPRs using v_readfirstlane. This is safe because we only select 1983 // loads with uniform pointers to SMRD instruction so we know the 1984 // pointer value is uniform. 1985 MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase); 1986 if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) { 1987 unsigned SGPR = readlaneVGPRToSGPR(SBase->getReg(), MI, MRI); 1988 SBase->setReg(SGPR); 1989 } 1990 } 1991 1992 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const { 1993 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 1994 1995 // Legalize VOP2 1996 if (isVOP2(*MI) || isVOPC(*MI)) { 1997 legalizeOperandsVOP2(MRI, MI); 1998 return; 1999 } 2000 2001 // Legalize VOP3 2002 if (isVOP3(*MI)) { 2003 legalizeOperandsVOP3(MRI, MI); 2004 return; 2005 } 2006 2007 // Legalize SMRD 2008 if (isSMRD(*MI)) { 2009 legalizeOperandsSMRD(MRI, MI); 2010 return; 2011 } 2012 2013 // Legalize REG_SEQUENCE and PHI 2014 // The register class of the operands much be the same type as the register 2015 // class of the output. 2016 if (MI->getOpcode() == AMDGPU::PHI) { 2017 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr; 2018 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) { 2019 if (!MI->getOperand(i).isReg() || 2020 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) 2021 continue; 2022 const TargetRegisterClass *OpRC = 2023 MRI.getRegClass(MI->getOperand(i).getReg()); 2024 if (RI.hasVGPRs(OpRC)) { 2025 VRC = OpRC; 2026 } else { 2027 SRC = OpRC; 2028 } 2029 } 2030 2031 // If any of the operands are VGPR registers, then they all most be 2032 // otherwise we will create illegal VGPR->SGPR copies when legalizing 2033 // them. 2034 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) { 2035 if (!VRC) { 2036 assert(SRC); 2037 VRC = RI.getEquivalentVGPRClass(SRC); 2038 } 2039 RC = VRC; 2040 } else { 2041 RC = SRC; 2042 } 2043 2044 // Update all the operands so they have the same type. 2045 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) { 2046 MachineOperand &Op = MI->getOperand(I); 2047 if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg())) 2048 continue; 2049 unsigned DstReg = MRI.createVirtualRegister(RC); 2050 2051 // MI is a PHI instruction. 2052 MachineBasicBlock *InsertBB = MI->getOperand(I + 1).getMBB(); 2053 MachineBasicBlock::iterator Insert = InsertBB->getFirstTerminator(); 2054 2055 BuildMI(*InsertBB, Insert, MI->getDebugLoc(), get(AMDGPU::COPY), DstReg) 2056 .addOperand(Op); 2057 Op.setReg(DstReg); 2058 } 2059 } 2060 2061 // REG_SEQUENCE doesn't really require operand legalization, but if one has a 2062 // VGPR dest type and SGPR sources, insert copies so all operands are 2063 // VGPRs. This seems to help operand folding / the register coalescer. 2064 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) { 2065 MachineBasicBlock *MBB = MI->getParent(); 2066 const TargetRegisterClass *DstRC = getOpRegClass(*MI, 0); 2067 if (RI.hasVGPRs(DstRC)) { 2068 // Update all the operands so they are VGPR register classes. These may 2069 // not be the same register class because REG_SEQUENCE supports mixing 2070 // subregister index types e.g. sub0_sub1 + sub2 + sub3 2071 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) { 2072 MachineOperand &Op = MI->getOperand(I); 2073 if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg())) 2074 continue; 2075 2076 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); 2077 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC); 2078 if (VRC == OpRC) 2079 continue; 2080 2081 unsigned DstReg = MRI.createVirtualRegister(VRC); 2082 2083 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), DstReg) 2084 .addOperand(Op); 2085 2086 Op.setReg(DstReg); 2087 Op.setIsKill(); 2088 } 2089 } 2090 2091 return; 2092 } 2093 2094 // Legalize INSERT_SUBREG 2095 // src0 must have the same register class as dst 2096 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) { 2097 unsigned Dst = MI->getOperand(0).getReg(); 2098 unsigned Src0 = MI->getOperand(1).getReg(); 2099 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); 2100 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0); 2101 if (DstRC != Src0RC) { 2102 MachineBasicBlock &MBB = *MI->getParent(); 2103 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC); 2104 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0) 2105 .addReg(Src0); 2106 MI->getOperand(1).setReg(NewSrc0); 2107 } 2108 return; 2109 } 2110 2111 // Legalize MIMG 2112 if (isMIMG(*MI)) { 2113 MachineOperand *SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc); 2114 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) { 2115 unsigned SGPR = readlaneVGPRToSGPR(SRsrc->getReg(), MI, MRI); 2116 SRsrc->setReg(SGPR); 2117 } 2118 2119 MachineOperand *SSamp = getNamedOperand(*MI, AMDGPU::OpName::ssamp); 2120 if (SSamp && !RI.isSGPRClass(MRI.getRegClass(SSamp->getReg()))) { 2121 unsigned SGPR = readlaneVGPRToSGPR(SSamp->getReg(), MI, MRI); 2122 SSamp->setReg(SGPR); 2123 } 2124 return; 2125 } 2126 2127 // Legalize MUBUF* instructions 2128 // FIXME: If we start using the non-addr64 instructions for compute, we 2129 // may need to legalize them here. 2130 int SRsrcIdx = 2131 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc); 2132 if (SRsrcIdx != -1) { 2133 // We have an MUBUF instruction 2134 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx); 2135 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass; 2136 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()), 2137 RI.getRegClass(SRsrcRC))) { 2138 // The operands are legal. 2139 // FIXME: We may need to legalize operands besided srsrc. 2140 return; 2141 } 2142 2143 MachineBasicBlock &MBB = *MI->getParent(); 2144 2145 // Extract the ptr from the resource descriptor. 2146 unsigned SRsrcPtr = buildExtractSubReg(MI, MRI, *SRsrc, 2147 &AMDGPU::VReg_128RegClass, AMDGPU::sub0_sub1, &AMDGPU::VReg_64RegClass); 2148 2149 // Create an empty resource descriptor 2150 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass); 2151 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); 2152 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); 2153 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass); 2154 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat(); 2155 2156 // Zero64 = 0 2157 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64), 2158 Zero64) 2159 .addImm(0); 2160 2161 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0} 2162 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), 2163 SRsrcFormatLo) 2164 .addImm(RsrcDataFormat & 0xFFFFFFFF); 2165 2166 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32} 2167 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), 2168 SRsrcFormatHi) 2169 .addImm(RsrcDataFormat >> 32); 2170 2171 // NewSRsrc = {Zero64, SRsrcFormat} 2172 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewSRsrc) 2173 .addReg(Zero64) 2174 .addImm(AMDGPU::sub0_sub1) 2175 .addReg(SRsrcFormatLo) 2176 .addImm(AMDGPU::sub2) 2177 .addReg(SRsrcFormatHi) 2178 .addImm(AMDGPU::sub3); 2179 2180 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr); 2181 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); 2182 if (VAddr) { 2183 // This is already an ADDR64 instruction so we need to add the pointer 2184 // extracted from the resource descriptor to the current value of VAddr. 2185 unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 2186 unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 2187 2188 // NewVaddrLo = SRsrcPtr:sub0 + VAddr:sub0 2189 DebugLoc DL = MI->getDebugLoc(); 2190 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), NewVAddrLo) 2191 .addReg(SRsrcPtr, 0, AMDGPU::sub0) 2192 .addReg(VAddr->getReg(), 0, AMDGPU::sub0); 2193 2194 // NewVaddrHi = SRsrcPtr:sub1 + VAddr:sub1 2195 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e32), NewVAddrHi) 2196 .addReg(SRsrcPtr, 0, AMDGPU::sub1) 2197 .addReg(VAddr->getReg(), 0, AMDGPU::sub1); 2198 2199 // NewVaddr = {NewVaddrHi, NewVaddrLo} 2200 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr) 2201 .addReg(NewVAddrLo) 2202 .addImm(AMDGPU::sub0) 2203 .addReg(NewVAddrHi) 2204 .addImm(AMDGPU::sub1); 2205 } else { 2206 // This instructions is the _OFFSET variant, so we need to convert it to 2207 // ADDR64. 2208 assert(MBB.getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() 2209 < AMDGPUSubtarget::VOLCANIC_ISLANDS && 2210 "FIXME: Need to emit flat atomics here"); 2211 2212 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata); 2213 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset); 2214 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset); 2215 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode()); 2216 2217 // Atomics rith return have have an additional tied operand and are 2218 // missing some of the special bits. 2219 MachineOperand *VDataIn = getNamedOperand(*MI, AMDGPU::OpName::vdata_in); 2220 MachineInstr *Addr64; 2221 2222 if (!VDataIn) { 2223 // Regular buffer load / store. 2224 MachineInstrBuilder MIB 2225 = BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode)) 2226 .addOperand(*VData) 2227 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr. 2228 // This will be replaced later 2229 // with the new value of vaddr. 2230 .addOperand(*SRsrc) 2231 .addOperand(*SOffset) 2232 .addOperand(*Offset); 2233 2234 // Atomics do not have this operand. 2235 if (const MachineOperand *GLC 2236 = getNamedOperand(*MI, AMDGPU::OpName::glc)) { 2237 MIB.addImm(GLC->getImm()); 2238 } 2239 2240 MIB.addImm(getNamedImmOperand(*MI, AMDGPU::OpName::slc)); 2241 2242 if (const MachineOperand *TFE 2243 = getNamedOperand(*MI, AMDGPU::OpName::tfe)) { 2244 MIB.addImm(TFE->getImm()); 2245 } 2246 2247 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 2248 Addr64 = MIB; 2249 } else { 2250 // Atomics with return. 2251 Addr64 = BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode)) 2252 .addOperand(*VData) 2253 .addOperand(*VDataIn) 2254 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr. 2255 // This will be replaced later 2256 // with the new value of vaddr. 2257 .addOperand(*SRsrc) 2258 .addOperand(*SOffset) 2259 .addOperand(*Offset) 2260 .addImm(getNamedImmOperand(*MI, AMDGPU::OpName::slc)) 2261 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 2262 } 2263 2264 MI->removeFromParent(); 2265 MI = Addr64; 2266 2267 // NewVaddr = {NewVaddrHi, NewVaddrLo} 2268 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr) 2269 .addReg(SRsrcPtr, 0, AMDGPU::sub0) 2270 .addImm(AMDGPU::sub0) 2271 .addReg(SRsrcPtr, 0, AMDGPU::sub1) 2272 .addImm(AMDGPU::sub1); 2273 2274 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr); 2275 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc); 2276 } 2277 2278 // Update the instruction to use NewVaddr 2279 VAddr->setReg(NewVAddr); 2280 // Update the instruction to use NewSRsrc 2281 SRsrc->setReg(NewSRsrc); 2282 } 2283 } 2284 2285 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const { 2286 SmallVector<MachineInstr *, 128> Worklist; 2287 Worklist.push_back(&TopInst); 2288 2289 while (!Worklist.empty()) { 2290 MachineInstr *Inst = Worklist.pop_back_val(); 2291 MachineBasicBlock *MBB = Inst->getParent(); 2292 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 2293 2294 unsigned Opcode = Inst->getOpcode(); 2295 unsigned NewOpcode = getVALUOp(*Inst); 2296 2297 // Handle some special cases 2298 switch (Opcode) { 2299 default: 2300 break; 2301 case AMDGPU::S_AND_B64: 2302 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_AND_B32_e64); 2303 Inst->eraseFromParent(); 2304 continue; 2305 2306 case AMDGPU::S_OR_B64: 2307 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_OR_B32_e64); 2308 Inst->eraseFromParent(); 2309 continue; 2310 2311 case AMDGPU::S_XOR_B64: 2312 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_XOR_B32_e64); 2313 Inst->eraseFromParent(); 2314 continue; 2315 2316 case AMDGPU::S_NOT_B64: 2317 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::V_NOT_B32_e32); 2318 Inst->eraseFromParent(); 2319 continue; 2320 2321 case AMDGPU::S_BCNT1_I32_B64: 2322 splitScalar64BitBCNT(Worklist, Inst); 2323 Inst->eraseFromParent(); 2324 continue; 2325 2326 case AMDGPU::S_BFE_I64: { 2327 splitScalar64BitBFE(Worklist, Inst); 2328 Inst->eraseFromParent(); 2329 continue; 2330 } 2331 2332 case AMDGPU::S_LSHL_B32: 2333 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { 2334 NewOpcode = AMDGPU::V_LSHLREV_B32_e64; 2335 swapOperands(Inst); 2336 } 2337 break; 2338 case AMDGPU::S_ASHR_I32: 2339 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { 2340 NewOpcode = AMDGPU::V_ASHRREV_I32_e64; 2341 swapOperands(Inst); 2342 } 2343 break; 2344 case AMDGPU::S_LSHR_B32: 2345 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { 2346 NewOpcode = AMDGPU::V_LSHRREV_B32_e64; 2347 swapOperands(Inst); 2348 } 2349 break; 2350 case AMDGPU::S_LSHL_B64: 2351 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { 2352 NewOpcode = AMDGPU::V_LSHLREV_B64; 2353 swapOperands(Inst); 2354 } 2355 break; 2356 case AMDGPU::S_ASHR_I64: 2357 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { 2358 NewOpcode = AMDGPU::V_ASHRREV_I64; 2359 swapOperands(Inst); 2360 } 2361 break; 2362 case AMDGPU::S_LSHR_B64: 2363 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { 2364 NewOpcode = AMDGPU::V_LSHRREV_B64; 2365 swapOperands(Inst); 2366 } 2367 break; 2368 2369 case AMDGPU::S_ABS_I32: 2370 lowerScalarAbs(Worklist, Inst); 2371 Inst->eraseFromParent(); 2372 continue; 2373 2374 case AMDGPU::S_CBRANCH_SCC0: 2375 case AMDGPU::S_CBRANCH_SCC1: 2376 // Clear unused bits of vcc 2377 BuildMI(*MBB, Inst, Inst->getDebugLoc(), get(AMDGPU::S_AND_B64), AMDGPU::VCC) 2378 .addReg(AMDGPU::EXEC) 2379 .addReg(AMDGPU::VCC); 2380 break; 2381 2382 case AMDGPU::S_BFE_U64: 2383 case AMDGPU::S_BFM_B64: 2384 llvm_unreachable("Moving this op to VALU not implemented"); 2385 } 2386 2387 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) { 2388 // We cannot move this instruction to the VALU, so we should try to 2389 // legalize its operands instead. 2390 legalizeOperands(Inst); 2391 continue; 2392 } 2393 2394 // Use the new VALU Opcode. 2395 const MCInstrDesc &NewDesc = get(NewOpcode); 2396 Inst->setDesc(NewDesc); 2397 2398 // Remove any references to SCC. Vector instructions can't read from it, and 2399 // We're just about to add the implicit use / defs of VCC, and we don't want 2400 // both. 2401 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) { 2402 MachineOperand &Op = Inst->getOperand(i); 2403 if (Op.isReg() && Op.getReg() == AMDGPU::SCC) { 2404 Inst->RemoveOperand(i); 2405 addSCCDefUsersToVALUWorklist(Inst, Worklist); 2406 } 2407 } 2408 2409 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) { 2410 // We are converting these to a BFE, so we need to add the missing 2411 // operands for the size and offset. 2412 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16; 2413 Inst->addOperand(MachineOperand::CreateImm(0)); 2414 Inst->addOperand(MachineOperand::CreateImm(Size)); 2415 2416 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) { 2417 // The VALU version adds the second operand to the result, so insert an 2418 // extra 0 operand. 2419 Inst->addOperand(MachineOperand::CreateImm(0)); 2420 } 2421 2422 Inst->addImplicitDefUseOperands(*Inst->getParent()->getParent()); 2423 2424 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) { 2425 const MachineOperand &OffsetWidthOp = Inst->getOperand(2); 2426 // If we need to move this to VGPRs, we need to unpack the second operand 2427 // back into the 2 separate ones for bit offset and width. 2428 assert(OffsetWidthOp.isImm() && 2429 "Scalar BFE is only implemented for constant width and offset"); 2430 uint32_t Imm = OffsetWidthOp.getImm(); 2431 2432 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0]. 2433 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16]. 2434 Inst->RemoveOperand(2); // Remove old immediate. 2435 Inst->addOperand(MachineOperand::CreateImm(Offset)); 2436 Inst->addOperand(MachineOperand::CreateImm(BitWidth)); 2437 } 2438 2439 bool HasDst = Inst->getOperand(0).isReg() && Inst->getOperand(0).isDef(); 2440 unsigned NewDstReg = AMDGPU::NoRegister; 2441 if (HasDst) { 2442 // Update the destination register class. 2443 const TargetRegisterClass *NewDstRC = getDestEquivalentVGPRClass(*Inst); 2444 if (!NewDstRC) 2445 continue; 2446 2447 unsigned DstReg = Inst->getOperand(0).getReg(); 2448 NewDstReg = MRI.createVirtualRegister(NewDstRC); 2449 MRI.replaceRegWith(DstReg, NewDstReg); 2450 } 2451 2452 // Legalize the operands 2453 legalizeOperands(Inst); 2454 2455 if (HasDst) 2456 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist); 2457 } 2458 } 2459 2460 //===----------------------------------------------------------------------===// 2461 // Indirect addressing callbacks 2462 //===----------------------------------------------------------------------===// 2463 2464 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const { 2465 return &AMDGPU::VGPR_32RegClass; 2466 } 2467 2468 void SIInstrInfo::lowerScalarAbs(SmallVectorImpl<MachineInstr *> &Worklist, 2469 MachineInstr *Inst) const { 2470 MachineBasicBlock &MBB = *Inst->getParent(); 2471 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2472 MachineBasicBlock::iterator MII = Inst; 2473 DebugLoc DL = Inst->getDebugLoc(); 2474 2475 MachineOperand &Dest = Inst->getOperand(0); 2476 MachineOperand &Src = Inst->getOperand(1); 2477 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 2478 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 2479 2480 BuildMI(MBB, MII, DL, get(AMDGPU::V_SUB_I32_e32), TmpReg) 2481 .addImm(0) 2482 .addReg(Src.getReg()); 2483 2484 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg) 2485 .addReg(Src.getReg()) 2486 .addReg(TmpReg); 2487 2488 MRI.replaceRegWith(Dest.getReg(), ResultReg); 2489 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); 2490 } 2491 2492 void SIInstrInfo::splitScalar64BitUnaryOp( 2493 SmallVectorImpl<MachineInstr *> &Worklist, 2494 MachineInstr *Inst, 2495 unsigned Opcode) const { 2496 MachineBasicBlock &MBB = *Inst->getParent(); 2497 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2498 2499 MachineOperand &Dest = Inst->getOperand(0); 2500 MachineOperand &Src0 = Inst->getOperand(1); 2501 DebugLoc DL = Inst->getDebugLoc(); 2502 2503 MachineBasicBlock::iterator MII = Inst; 2504 2505 const MCInstrDesc &InstDesc = get(Opcode); 2506 const TargetRegisterClass *Src0RC = Src0.isReg() ? 2507 MRI.getRegClass(Src0.getReg()) : 2508 &AMDGPU::SGPR_32RegClass; 2509 2510 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); 2511 2512 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, 2513 AMDGPU::sub0, Src0SubRC); 2514 2515 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); 2516 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); 2517 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); 2518 2519 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC); 2520 BuildMI(MBB, MII, DL, InstDesc, DestSub0) 2521 .addOperand(SrcReg0Sub0); 2522 2523 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, 2524 AMDGPU::sub1, Src0SubRC); 2525 2526 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC); 2527 BuildMI(MBB, MII, DL, InstDesc, DestSub1) 2528 .addOperand(SrcReg0Sub1); 2529 2530 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC); 2531 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg) 2532 .addReg(DestSub0) 2533 .addImm(AMDGPU::sub0) 2534 .addReg(DestSub1) 2535 .addImm(AMDGPU::sub1); 2536 2537 MRI.replaceRegWith(Dest.getReg(), FullDestReg); 2538 2539 // We don't need to legalizeOperands here because for a single operand, src0 2540 // will support any kind of input. 2541 2542 // Move all users of this moved value. 2543 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist); 2544 } 2545 2546 void SIInstrInfo::splitScalar64BitBinaryOp( 2547 SmallVectorImpl<MachineInstr *> &Worklist, 2548 MachineInstr *Inst, 2549 unsigned Opcode) const { 2550 MachineBasicBlock &MBB = *Inst->getParent(); 2551 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2552 2553 MachineOperand &Dest = Inst->getOperand(0); 2554 MachineOperand &Src0 = Inst->getOperand(1); 2555 MachineOperand &Src1 = Inst->getOperand(2); 2556 DebugLoc DL = Inst->getDebugLoc(); 2557 2558 MachineBasicBlock::iterator MII = Inst; 2559 2560 const MCInstrDesc &InstDesc = get(Opcode); 2561 const TargetRegisterClass *Src0RC = Src0.isReg() ? 2562 MRI.getRegClass(Src0.getReg()) : 2563 &AMDGPU::SGPR_32RegClass; 2564 2565 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); 2566 const TargetRegisterClass *Src1RC = Src1.isReg() ? 2567 MRI.getRegClass(Src1.getReg()) : 2568 &AMDGPU::SGPR_32RegClass; 2569 2570 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); 2571 2572 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, 2573 AMDGPU::sub0, Src0SubRC); 2574 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, 2575 AMDGPU::sub0, Src1SubRC); 2576 2577 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); 2578 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); 2579 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); 2580 2581 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC); 2582 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0) 2583 .addOperand(SrcReg0Sub0) 2584 .addOperand(SrcReg1Sub0); 2585 2586 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, 2587 AMDGPU::sub1, Src0SubRC); 2588 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, 2589 AMDGPU::sub1, Src1SubRC); 2590 2591 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC); 2592 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1) 2593 .addOperand(SrcReg0Sub1) 2594 .addOperand(SrcReg1Sub1); 2595 2596 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC); 2597 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg) 2598 .addReg(DestSub0) 2599 .addImm(AMDGPU::sub0) 2600 .addReg(DestSub1) 2601 .addImm(AMDGPU::sub1); 2602 2603 MRI.replaceRegWith(Dest.getReg(), FullDestReg); 2604 2605 // Try to legalize the operands in case we need to swap the order to keep it 2606 // valid. 2607 legalizeOperands(LoHalf); 2608 legalizeOperands(HiHalf); 2609 2610 // Move all users of this moved vlaue. 2611 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist); 2612 } 2613 2614 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist, 2615 MachineInstr *Inst) const { 2616 MachineBasicBlock &MBB = *Inst->getParent(); 2617 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2618 2619 MachineBasicBlock::iterator MII = Inst; 2620 DebugLoc DL = Inst->getDebugLoc(); 2621 2622 MachineOperand &Dest = Inst->getOperand(0); 2623 MachineOperand &Src = Inst->getOperand(1); 2624 2625 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64); 2626 const TargetRegisterClass *SrcRC = Src.isReg() ? 2627 MRI.getRegClass(Src.getReg()) : 2628 &AMDGPU::SGPR_32RegClass; 2629 2630 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 2631 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 2632 2633 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0); 2634 2635 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC, 2636 AMDGPU::sub0, SrcSubRC); 2637 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC, 2638 AMDGPU::sub1, SrcSubRC); 2639 2640 BuildMI(MBB, MII, DL, InstDesc, MidReg) 2641 .addOperand(SrcRegSub0) 2642 .addImm(0); 2643 2644 BuildMI(MBB, MII, DL, InstDesc, ResultReg) 2645 .addOperand(SrcRegSub1) 2646 .addReg(MidReg); 2647 2648 MRI.replaceRegWith(Dest.getReg(), ResultReg); 2649 2650 // We don't need to legalize operands here. src0 for etiher instruction can be 2651 // an SGPR, and the second input is unused or determined here. 2652 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); 2653 } 2654 2655 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist, 2656 MachineInstr *Inst) const { 2657 MachineBasicBlock &MBB = *Inst->getParent(); 2658 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2659 MachineBasicBlock::iterator MII = Inst; 2660 DebugLoc DL = Inst->getDebugLoc(); 2661 2662 MachineOperand &Dest = Inst->getOperand(0); 2663 uint32_t Imm = Inst->getOperand(2).getImm(); 2664 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0]. 2665 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16]. 2666 2667 (void) Offset; 2668 2669 // Only sext_inreg cases handled. 2670 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 && 2671 BitWidth <= 32 && 2672 Offset == 0 && 2673 "Not implemented"); 2674 2675 if (BitWidth < 32) { 2676 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 2677 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 2678 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); 2679 2680 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo) 2681 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0) 2682 .addImm(0) 2683 .addImm(BitWidth); 2684 2685 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi) 2686 .addImm(31) 2687 .addReg(MidRegLo); 2688 2689 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg) 2690 .addReg(MidRegLo) 2691 .addImm(AMDGPU::sub0) 2692 .addReg(MidRegHi) 2693 .addImm(AMDGPU::sub1); 2694 2695 MRI.replaceRegWith(Dest.getReg(), ResultReg); 2696 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); 2697 return; 2698 } 2699 2700 MachineOperand &Src = Inst->getOperand(1); 2701 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 2702 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); 2703 2704 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg) 2705 .addImm(31) 2706 .addReg(Src.getReg(), 0, AMDGPU::sub0); 2707 2708 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg) 2709 .addReg(Src.getReg(), 0, AMDGPU::sub0) 2710 .addImm(AMDGPU::sub0) 2711 .addReg(TmpReg) 2712 .addImm(AMDGPU::sub1); 2713 2714 MRI.replaceRegWith(Dest.getReg(), ResultReg); 2715 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); 2716 } 2717 2718 void SIInstrInfo::addUsersToMoveToVALUWorklist( 2719 unsigned DstReg, 2720 MachineRegisterInfo &MRI, 2721 SmallVectorImpl<MachineInstr *> &Worklist) const { 2722 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg), 2723 E = MRI.use_end(); I != E; ++I) { 2724 MachineInstr &UseMI = *I->getParent(); 2725 if (!canReadVGPR(UseMI, I.getOperandNo())) { 2726 Worklist.push_back(&UseMI); 2727 } 2728 } 2729 } 2730 2731 void SIInstrInfo::addSCCDefUsersToVALUWorklist(MachineInstr *SCCDefInst, 2732 SmallVectorImpl<MachineInstr *> &Worklist) const { 2733 // This assumes that all the users of SCC are in the same block 2734 // as the SCC def. 2735 for (MachineBasicBlock::iterator I = SCCDefInst, 2736 E = SCCDefInst->getParent()->end(); I != E; ++I) { 2737 2738 // Exit if we find another SCC def. 2739 if (I->findRegisterDefOperandIdx(AMDGPU::SCC) != -1) 2740 return; 2741 2742 if (I->findRegisterUseOperandIdx(AMDGPU::SCC) != -1) 2743 Worklist.push_back(I); 2744 } 2745 } 2746 2747 const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass( 2748 const MachineInstr &Inst) const { 2749 const TargetRegisterClass *NewDstRC = getOpRegClass(Inst, 0); 2750 2751 switch (Inst.getOpcode()) { 2752 // For target instructions, getOpRegClass just returns the virtual register 2753 // class associated with the operand, so we need to find an equivalent VGPR 2754 // register class in order to move the instruction to the VALU. 2755 case AMDGPU::COPY: 2756 case AMDGPU::PHI: 2757 case AMDGPU::REG_SEQUENCE: 2758 case AMDGPU::INSERT_SUBREG: 2759 if (RI.hasVGPRs(NewDstRC)) 2760 return nullptr; 2761 2762 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC); 2763 if (!NewDstRC) 2764 return nullptr; 2765 return NewDstRC; 2766 default: 2767 return NewDstRC; 2768 } 2769 } 2770 2771 // Find the one SGPR operand we are allowed to use. 2772 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI, 2773 int OpIndices[3]) const { 2774 const MCInstrDesc &Desc = MI->getDesc(); 2775 2776 // Find the one SGPR operand we are allowed to use. 2777 // 2778 // First we need to consider the instruction's operand requirements before 2779 // legalizing. Some operands are required to be SGPRs, such as implicit uses 2780 // of VCC, but we are still bound by the constant bus requirement to only use 2781 // one. 2782 // 2783 // If the operand's class is an SGPR, we can never move it. 2784 2785 unsigned SGPRReg = findImplicitSGPRRead(*MI); 2786 if (SGPRReg != AMDGPU::NoRegister) 2787 return SGPRReg; 2788 2789 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister }; 2790 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 2791 2792 for (unsigned i = 0; i < 3; ++i) { 2793 int Idx = OpIndices[i]; 2794 if (Idx == -1) 2795 break; 2796 2797 const MachineOperand &MO = MI->getOperand(Idx); 2798 if (!MO.isReg()) 2799 continue; 2800 2801 // Is this operand statically required to be an SGPR based on the operand 2802 // constraints? 2803 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass); 2804 bool IsRequiredSGPR = RI.isSGPRClass(OpRC); 2805 if (IsRequiredSGPR) 2806 return MO.getReg(); 2807 2808 // If this could be a VGPR or an SGPR, Check the dynamic register class. 2809 unsigned Reg = MO.getReg(); 2810 const TargetRegisterClass *RegRC = MRI.getRegClass(Reg); 2811 if (RI.isSGPRClass(RegRC)) 2812 UsedSGPRs[i] = Reg; 2813 } 2814 2815 // We don't have a required SGPR operand, so we have a bit more freedom in 2816 // selecting operands to move. 2817 2818 // Try to select the most used SGPR. If an SGPR is equal to one of the 2819 // others, we choose that. 2820 // 2821 // e.g. 2822 // V_FMA_F32 v0, s0, s0, s0 -> No moves 2823 // V_FMA_F32 v0, s0, s1, s0 -> Move s1 2824 2825 // TODO: If some of the operands are 64-bit SGPRs and some 32, we should 2826 // prefer those. 2827 2828 if (UsedSGPRs[0] != AMDGPU::NoRegister) { 2829 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2]) 2830 SGPRReg = UsedSGPRs[0]; 2831 } 2832 2833 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) { 2834 if (UsedSGPRs[1] == UsedSGPRs[2]) 2835 SGPRReg = UsedSGPRs[1]; 2836 } 2837 2838 return SGPRReg; 2839 } 2840 2841 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved, 2842 const MachineFunction &MF) const { 2843 int End = getIndirectIndexEnd(MF); 2844 int Begin = getIndirectIndexBegin(MF); 2845 2846 if (End == -1) 2847 return; 2848 2849 2850 for (int Index = Begin; Index <= End; ++Index) 2851 Reserved.set(AMDGPU::VGPR_32RegClass.getRegister(Index)); 2852 2853 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index) 2854 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index)); 2855 2856 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index) 2857 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index)); 2858 2859 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index) 2860 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index)); 2861 2862 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index) 2863 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index)); 2864 2865 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index) 2866 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index)); 2867 } 2868 2869 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI, 2870 unsigned OperandName) const { 2871 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName); 2872 if (Idx == -1) 2873 return nullptr; 2874 2875 return &MI.getOperand(Idx); 2876 } 2877 2878 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const { 2879 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT; 2880 if (ST.isAmdHsaOS()) { 2881 RsrcDataFormat |= (1ULL << 56); 2882 2883 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) 2884 // Set MTYPE = 2 2885 RsrcDataFormat |= (2ULL << 59); 2886 } 2887 2888 return RsrcDataFormat; 2889 } 2890 2891 uint64_t SIInstrInfo::getScratchRsrcWords23() const { 2892 uint64_t Rsrc23 = getDefaultRsrcDataFormat() | 2893 AMDGPU::RSRC_TID_ENABLE | 2894 0xffffffff; // Size; 2895 2896 uint64_t EltSizeValue = Log2_32(ST.getMaxPrivateElementSize()) - 1; 2897 2898 Rsrc23 |= (EltSizeValue << AMDGPU::RSRC_ELEMENT_SIZE_SHIFT); 2899 2900 // If TID_ENABLE is set, DATA_FORMAT specifies stride bits [14:17]. 2901 // Clear them unless we want a huge stride. 2902 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) 2903 Rsrc23 &= ~AMDGPU::RSRC_DATA_FORMAT; 2904 2905 return Rsrc23; 2906 } 2907 2908 bool SIInstrInfo::isLowLatencyInstruction(const MachineInstr *MI) const { 2909 unsigned Opc = MI->getOpcode(); 2910 2911 return isSMRD(Opc); 2912 } 2913 2914 bool SIInstrInfo::isHighLatencyInstruction(const MachineInstr *MI) const { 2915 unsigned Opc = MI->getOpcode(); 2916 2917 return isMUBUF(Opc) || isMTBUF(Opc) || isMIMG(Opc); 2918 } 2919 2920 ArrayRef<std::pair<int, const char *>> 2921 SIInstrInfo::getSerializableTargetIndices() const { 2922 static const std::pair<int, const char *> TargetIndices[] = { 2923 {AMDGPU::TI_CONSTDATA_START, "amdgpu-constdata-start"}, 2924 {AMDGPU::TI_SCRATCH_RSRC_DWORD0, "amdgpu-scratch-rsrc-dword0"}, 2925 {AMDGPU::TI_SCRATCH_RSRC_DWORD1, "amdgpu-scratch-rsrc-dword1"}, 2926 {AMDGPU::TI_SCRATCH_RSRC_DWORD2, "amdgpu-scratch-rsrc-dword2"}, 2927 {AMDGPU::TI_SCRATCH_RSRC_DWORD3, "amdgpu-scratch-rsrc-dword3"}}; 2928 return makeArrayRef(TargetIndices); 2929 } 2930