1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// SI Instruction format definitions.
11//
12//===----------------------------------------------------------------------===//
13
14def isGCN : Predicate<"Subtarget->getGeneration() "
15                      ">= SISubtarget::SOUTHERN_ISLANDS">,
16            AssemblerPredicate<"FeatureGCN">;
17def isSI : Predicate<"Subtarget->getGeneration() "
18                      "== SISubtarget::SOUTHERN_ISLANDS">,
19           AssemblerPredicate<"FeatureSouthernIslands">;
20
21
22class InstSI <dag outs, dag ins, string asm = "",
23              list<dag> pattern = []> :
24  AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
25  let SubtargetPredicate = isGCN;
26
27  // Low bits - basic encoding information.
28  field bit SALU = 0;
29  field bit VALU = 0;
30
31  // SALU instruction formats.
32  field bit SOP1 = 0;
33  field bit SOP2 = 0;
34  field bit SOPC = 0;
35  field bit SOPK = 0;
36  field bit SOPP = 0;
37
38  // VALU instruction formats.
39  field bit VOP1 = 0;
40  field bit VOP2 = 0;
41  field bit VOPC = 0;
42  field bit VOP3 = 0;
43  field bit VOP3P = 0;
44  field bit VINTRP = 0;
45  field bit SDWA = 0;
46  field bit DPP = 0;
47
48  // Memory instruction formats.
49  field bit MUBUF = 0;
50  field bit MTBUF = 0;
51  field bit SMRD = 0;
52  field bit MIMG = 0;
53  field bit EXP = 0;
54  field bit FLAT = 0;
55  field bit DS = 0;
56
57  // Pseudo instruction formats.
58  field bit VGPRSpill = 0;
59  field bit SGPRSpill = 0;
60
61  // High bits - other information.
62  field bit VM_CNT = 0;
63  field bit EXP_CNT = 0;
64  field bit LGKM_CNT = 0;
65
66  // Whether WQM _must_ be enabled for this instruction.
67  field bit WQM = 0;
68
69  // Whether WQM _must_ be disabled for this instruction.
70  field bit DisableWQM = 0;
71
72  field bit Gather4 = 0;
73
74  // Most sopk treat the immediate as a signed 16-bit, however some
75  // use it as unsigned.
76  field bit SOPKZext = 0;
77
78  // This is an s_store_dword* instruction that requires a cache flush
79  // on wave termination. It is necessary to distinguish from mayStore
80  // SMEM instructions like the cache flush ones.
81  field bit ScalarStore = 0;
82
83  // Whether the operands can be ignored when computing the
84  // instruction size.
85  field bit FixedSize = 0;
86
87  // This bit tells the assembler to use the 32-bit encoding in case it
88  // is unable to infer the encoding from the operands.
89  field bit VOPAsmPrefer32Bit = 0;
90
91  // This bit indicates that this is a VOP3 opcode which supports op_sel
92  // modifier (gfx9 only).
93  field bit VOP3_OPSEL = 0;
94
95  // Is it possible for this instruction to be atomic?
96  field bit maybeAtomic = 0;
97
98  // This bit indicates that this is a 16-bit instruction which zero-fills
99  // unused bits in dst. Note that new GFX9 opcodes preserve unused bits.
100  field bit F16_ZFILL = 0;
101
102  // This bit indicates that this has a floating point result type, so
103  // the clamp modifier has floating point semantics.
104  field bit FPClamp = 0;
105
106  // This bit indicates that instruction may support integer clamping
107  // which depends on GPU features.
108  field bit IntClamp = 0;
109
110  // This field indicates that the clamp applies to the low component
111  // of a packed output register.
112  field bit ClampLo = 0;
113
114  // This field indicates that the clamp applies to the high component
115  // of a packed output register.
116  field bit ClampHi = 0;
117
118  // These need to be kept in sync with the enum in SIInstrFlags.
119  let TSFlags{0} = SALU;
120  let TSFlags{1} = VALU;
121
122  let TSFlags{2} = SOP1;
123  let TSFlags{3} = SOP2;
124  let TSFlags{4} = SOPC;
125  let TSFlags{5} = SOPK;
126  let TSFlags{6} = SOPP;
127
128  let TSFlags{7} = VOP1;
129  let TSFlags{8} = VOP2;
130  let TSFlags{9} = VOPC;
131  let TSFlags{10} = VOP3;
132  let TSFlags{12} = VOP3P;
133
134  let TSFlags{13} = VINTRP;
135  let TSFlags{14} = SDWA;
136  let TSFlags{15} = DPP;
137
138  let TSFlags{16} = MUBUF;
139  let TSFlags{17} = MTBUF;
140  let TSFlags{18} = SMRD;
141  let TSFlags{19} = MIMG;
142  let TSFlags{20} = EXP;
143  let TSFlags{21} = FLAT;
144  let TSFlags{22} = DS;
145
146  let TSFlags{23} = VGPRSpill;
147  let TSFlags{24} = SGPRSpill;
148
149  let TSFlags{32} = VM_CNT;
150  let TSFlags{33} = EXP_CNT;
151  let TSFlags{34} = LGKM_CNT;
152
153  let TSFlags{35} = WQM;
154  let TSFlags{36} = DisableWQM;
155  let TSFlags{37} = Gather4;
156
157  let TSFlags{38} = SOPKZext;
158  let TSFlags{39} = ScalarStore;
159  let TSFlags{40} = FixedSize;
160  let TSFlags{41} = VOPAsmPrefer32Bit;
161  let TSFlags{42} = VOP3_OPSEL;
162
163  let TSFlags{43} = maybeAtomic;
164  let TSFlags{44} = F16_ZFILL;
165
166  let TSFlags{45} = FPClamp;
167  let TSFlags{46} = IntClamp;
168  let TSFlags{47} = ClampLo;
169  let TSFlags{48} = ClampHi;
170
171  let SchedRW = [Write32Bit];
172
173  field bits<1> DisableSIDecoder = 0;
174  field bits<1> DisableVIDecoder = 0;
175  field bits<1> DisableDecoder = 0;
176
177  let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);
178  let AsmVariantName = AMDGPUAsmVariants.Default;
179}
180
181class PseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
182  : InstSI<outs, ins, asm, pattern> {
183  let isPseudo = 1;
184  let isCodeGenOnly = 1;
185}
186
187class SPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
188  : PseudoInstSI<outs, ins, pattern, asm> {
189  let SALU = 1;
190}
191
192class VPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
193  : PseudoInstSI<outs, ins, pattern, asm> {
194  let VALU = 1;
195  let Uses = [EXEC];
196}
197
198class CFPseudoInstSI<dag outs, dag ins, list<dag> pattern = [],
199  bit UseExec = 0, bit DefExec = 0> :
200  SPseudoInstSI<outs, ins, pattern> {
201
202  let Uses = !if(UseExec, [EXEC], []);
203  let Defs = !if(DefExec, [EXEC, SCC], [SCC]);
204  let mayLoad = 0;
205  let mayStore = 0;
206  let hasSideEffects = 0;
207}
208
209class Enc32 {
210  field bits<32> Inst;
211  int Size = 4;
212}
213
214class Enc64 {
215  field bits<64> Inst;
216  int Size = 8;
217}
218
219class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
220
221class VINTRPe <bits<2> op> : Enc32 {
222  bits<8> vdst;
223  bits<8> vsrc;
224  bits<2> attrchan;
225  bits<6> attr;
226
227  let Inst{7-0} = vsrc;
228  let Inst{9-8} = attrchan;
229  let Inst{15-10} = attr;
230  let Inst{17-16} = op;
231  let Inst{25-18} = vdst;
232  let Inst{31-26} = 0x32; // encoding
233}
234
235class MIMGe <bits<7> op> : Enc64 {
236  bits<8> vdata;
237  bits<4> dmask;
238  bits<1> unorm;
239  bits<1> glc;
240  bits<1> da;
241  bits<1> r128;
242  bits<1> tfe;
243  bits<1> lwe;
244  bits<1> slc;
245  bits<8> vaddr;
246  bits<7> srsrc;
247  bits<7> ssamp;
248
249  let Inst{11-8} = dmask;
250  let Inst{12} = unorm;
251  let Inst{13} = glc;
252  let Inst{14} = da;
253  let Inst{15} = r128;
254  let Inst{16} = tfe;
255  let Inst{17} = lwe;
256  let Inst{24-18} = op;
257  let Inst{25} = slc;
258  let Inst{31-26} = 0x3c;
259  let Inst{39-32} = vaddr;
260  let Inst{47-40} = vdata;
261  let Inst{52-48} = srsrc{6-2};
262  let Inst{57-53} = ssamp{6-2};
263}
264
265class EXPe : Enc64 {
266  bits<4> en;
267  bits<6> tgt;
268  bits<1> compr;
269  bits<1> done;
270  bits<1> vm;
271  bits<8> src0;
272  bits<8> src1;
273  bits<8> src2;
274  bits<8> src3;
275
276  let Inst{3-0} = en;
277  let Inst{9-4} = tgt;
278  let Inst{10} = compr;
279  let Inst{11} = done;
280  let Inst{12} = vm;
281  let Inst{31-26} = 0x3e;
282  let Inst{39-32} = src0;
283  let Inst{47-40} = src1;
284  let Inst{55-48} = src2;
285  let Inst{63-56} = src3;
286}
287
288let Uses = [EXEC] in {
289
290class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
291    InstSI <outs, ins, asm, pattern> {
292  let VINTRP = 1;
293  // VINTRP instructions read parameter values from LDS, but these parameter
294  // values are stored outside of the LDS memory that is allocated to the
295  // shader for general purpose use.
296  //
297  // While it may be possible for ds_read/ds_write instructions to access
298  // the parameter values in LDS, this would essentially be an out-of-bounds
299  // memory access which we consider to be undefined behavior.
300  //
301  // So even though these instructions read memory, this memory is outside the
302  // addressable memory space for the shader, and we consider these instructions
303  // to be readnone.
304  let mayLoad = 0;
305  let mayStore = 0;
306  let hasSideEffects = 0;
307}
308
309class EXPCommon<dag outs, dag ins, string asm, list<dag> pattern> :
310  InstSI<outs, ins, asm, pattern> {
311  let EXP = 1;
312  let EXP_CNT = 1;
313  let mayLoad = 0; // Set to 1 if done bit is set.
314  let mayStore = 1;
315  let UseNamedOperandTable = 1;
316  let Uses = [EXEC];
317  let SchedRW = [WriteExport];
318}
319
320} // End Uses = [EXEC]
321
322class MIMG <dag outs, dag ins, string asm, list<dag> pattern> :
323    InstSI <outs, ins, asm, pattern> {
324
325  let VM_CNT = 1;
326  let EXP_CNT = 1;
327  let MIMG = 1;
328  let Uses = [EXEC];
329
330  let UseNamedOperandTable = 1;
331  let hasSideEffects = 0; // XXX ????
332}
333