1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// SI Instruction format definitions. 11// 12//===----------------------------------------------------------------------===// 13 14class InstSI <dag outs, dag ins, string asm = "", 15 list<dag> pattern = []> : 16 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl { 17 18 field bits<1> VM_CNT = 0; 19 field bits<1> EXP_CNT = 0; 20 field bits<1> LGKM_CNT = 0; 21 22 field bits<1> SALU = 0; 23 field bits<1> VALU = 0; 24 25 field bits<1> SOP1 = 0; 26 field bits<1> SOP2 = 0; 27 field bits<1> SOPC = 0; 28 field bits<1> SOPK = 0; 29 field bits<1> SOPP = 0; 30 31 field bits<1> VOP1 = 0; 32 field bits<1> VOP2 = 0; 33 field bits<1> VOP3 = 0; 34 field bits<1> VOPC = 0; 35 field bits<1> SDWA = 0; 36 field bits<1> DPP = 0; 37 38 field bits<1> MUBUF = 0; 39 field bits<1> MTBUF = 0; 40 field bits<1> SMRD = 0; 41 field bits<1> DS = 0; 42 field bits<1> MIMG = 0; 43 field bits<1> FLAT = 0; 44 field bits<1> WQM = 0; 45 field bits<1> VGPRSpill = 0; 46 47 // This bit tells the assembler to use the 32-bit encoding in case it 48 // is unable to infer the encoding from the operands. 49 field bits<1> VOPAsmPrefer32Bit = 0; 50 51 // These need to be kept in sync with the enum in SIInstrFlags. 52 let TSFlags{0} = VM_CNT; 53 let TSFlags{1} = EXP_CNT; 54 let TSFlags{2} = LGKM_CNT; 55 56 let TSFlags{3} = SALU; 57 let TSFlags{4} = VALU; 58 59 let TSFlags{5} = SOP1; 60 let TSFlags{6} = SOP2; 61 let TSFlags{7} = SOPC; 62 let TSFlags{8} = SOPK; 63 let TSFlags{9} = SOPP; 64 65 let TSFlags{10} = VOP1; 66 let TSFlags{11} = VOP2; 67 let TSFlags{12} = VOP3; 68 let TSFlags{13} = VOPC; 69 let TSFlags{14} = SDWA; 70 let TSFlags{15} = DPP; 71 72 let TSFlags{16} = MUBUF; 73 let TSFlags{17} = MTBUF; 74 let TSFlags{18} = SMRD; 75 let TSFlags{19} = DS; 76 let TSFlags{20} = MIMG; 77 let TSFlags{21} = FLAT; 78 let TSFlags{22} = WQM; 79 let TSFlags{23} = VGPRSpill; 80 let TSFlags{24} = VOPAsmPrefer32Bit; 81 82 let SchedRW = [Write32Bit]; 83 84 field bits<1> DisableSIDecoder = 0; 85 field bits<1> DisableVIDecoder = 0; 86 field bits<1> DisableDecoder = 0; 87 88 let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1); 89} 90 91class Enc32 { 92 field bits<32> Inst; 93 int Size = 4; 94} 95 96class Enc64 { 97 field bits<64> Inst; 98 int Size = 8; 99} 100 101class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">; 102 103let Uses = [EXEC] in { 104 105class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> : 106 InstSI <outs, ins, asm, pattern> { 107 108 let mayLoad = 0; 109 let mayStore = 0; 110 let hasSideEffects = 0; 111 let UseNamedOperandTable = 1; 112 let VALU = 1; 113} 114 115class VOPCCommon <dag ins, string asm, list<dag> pattern> : 116 VOPAnyCommon <(outs), ins, asm, pattern> { 117 118 let VOPC = 1; 119 let Size = 4; 120 let Defs = [VCC]; 121} 122 123class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> : 124 VOPAnyCommon <outs, ins, asm, pattern> { 125 126 let VOP1 = 1; 127 let Size = 4; 128} 129 130class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> : 131 VOPAnyCommon <outs, ins, asm, pattern> { 132 133 let VOP2 = 1; 134 let Size = 4; 135} 136 137class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern, bit HasMods = 0, bit VOP3Only = 0> : 138 VOPAnyCommon <outs, ins, asm, pattern> { 139 140 // Using complex patterns gives VOP3 patterns a very high complexity rating, 141 // but standalone patterns are almost always prefered, so we need to adjust the 142 // priority lower. The goal is to use a high number to reduce complexity to 143 // zero (or less than zero). 144 let AddedComplexity = -1000; 145 146 let VOP3 = 1; 147 let VALU = 1; 148 149 let AsmMatchConverter = 150 !if(!eq(VOP3Only,1), 151 "cvtVOP3", 152 !if(!eq(HasMods,1), "cvtVOP3_2_mod", "")); 153 154 let isCodeGenOnly = 0; 155 156 int Size = 8; 157 158 // Because SGPRs may be allowed if there are multiple operands, we 159 // need a post-isel hook to insert copies in order to avoid 160 // violating constant bus requirements. 161 let hasPostISelHook = 1; 162} 163 164} // End Uses = [EXEC] 165 166//===----------------------------------------------------------------------===// 167// Scalar operations 168//===----------------------------------------------------------------------===// 169 170class SOP1e <bits<8> op> : Enc32 { 171 bits<7> sdst; 172 bits<8> src0; 173 174 let Inst{7-0} = src0; 175 let Inst{15-8} = op; 176 let Inst{22-16} = sdst; 177 let Inst{31-23} = 0x17d; //encoding; 178} 179 180class SOP2e <bits<7> op> : Enc32 { 181 bits<7> sdst; 182 bits<8> src0; 183 bits<8> src1; 184 185 let Inst{7-0} = src0; 186 let Inst{15-8} = src1; 187 let Inst{22-16} = sdst; 188 let Inst{29-23} = op; 189 let Inst{31-30} = 0x2; // encoding 190} 191 192class SOPCe <bits<7> op> : Enc32 { 193 bits<8> src0; 194 bits<8> src1; 195 196 let Inst{7-0} = src0; 197 let Inst{15-8} = src1; 198 let Inst{22-16} = op; 199 let Inst{31-23} = 0x17e; 200} 201 202class SOPKe <bits<5> op> : Enc32 { 203 bits <7> sdst; 204 bits <16> simm16; 205 206 let Inst{15-0} = simm16; 207 let Inst{22-16} = sdst; 208 let Inst{27-23} = op; 209 let Inst{31-28} = 0xb; //encoding 210} 211 212class SOPK64e <bits<5> op> : Enc64 { 213 bits <7> sdst = 0; 214 bits <16> simm16; 215 bits <32> imm; 216 217 let Inst{15-0} = simm16; 218 let Inst{22-16} = sdst; 219 let Inst{27-23} = op; 220 let Inst{31-28} = 0xb; 221 222 let Inst{63-32} = imm; 223} 224 225class SOPPe <bits<7> op> : Enc32 { 226 bits <16> simm16; 227 228 let Inst{15-0} = simm16; 229 let Inst{22-16} = op; 230 let Inst{31-23} = 0x17f; // encoding 231} 232 233class SMRDe <bits<5> op, bits<1> imm> : Enc32 { 234 bits<7> sdst; 235 bits<7> sbase; 236 237 let Inst{8} = imm; 238 let Inst{14-9} = sbase{6-1}; 239 let Inst{21-15} = sdst; 240 let Inst{26-22} = op; 241 let Inst{31-27} = 0x18; //encoding 242} 243 244class SMRD_IMMe <bits<5> op> : SMRDe<op, 1> { 245 bits<8> offset; 246 let Inst{7-0} = offset; 247} 248 249class SMRD_SOFFe <bits<5> op> : SMRDe<op, 0> { 250 bits<8> soff; 251 let Inst{7-0} = soff; 252} 253 254 255 256class SMRD_IMMe_ci <bits<5> op> : Enc64 { 257 bits<7> sdst; 258 bits<7> sbase; 259 bits<32> offset; 260 261 let Inst{7-0} = 0xff; 262 let Inst{8} = 0; 263 let Inst{14-9} = sbase{6-1}; 264 let Inst{21-15} = sdst; 265 let Inst{26-22} = op; 266 let Inst{31-27} = 0x18; //encoding 267 let Inst{63-32} = offset; 268} 269 270let SchedRW = [WriteSALU] in { 271class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> : 272 InstSI<outs, ins, asm, pattern> { 273 let mayLoad = 0; 274 let mayStore = 0; 275 let hasSideEffects = 0; 276 let isCodeGenOnly = 0; 277 let SALU = 1; 278 let SOP1 = 1; 279} 280 281class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> : 282 InstSI <outs, ins, asm, pattern> { 283 284 let mayLoad = 0; 285 let mayStore = 0; 286 let hasSideEffects = 0; 287 let isCodeGenOnly = 0; 288 let SALU = 1; 289 let SOP2 = 1; 290 291 let UseNamedOperandTable = 1; 292} 293 294class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 295 InstSI<outs, ins, asm, pattern>, SOPCe <op> { 296 297 let mayLoad = 0; 298 let mayStore = 0; 299 let hasSideEffects = 0; 300 let SALU = 1; 301 let SOPC = 1; 302 let isCodeGenOnly = 0; 303 let Defs = [SCC]; 304 305 let UseNamedOperandTable = 1; 306} 307 308class SOPK <dag outs, dag ins, string asm, list<dag> pattern> : 309 InstSI <outs, ins , asm, pattern> { 310 311 let mayLoad = 0; 312 let mayStore = 0; 313 let hasSideEffects = 0; 314 let SALU = 1; 315 let SOPK = 1; 316 317 let UseNamedOperandTable = 1; 318} 319 320class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> : 321 InstSI <(outs), ins, asm, pattern >, SOPPe <op> { 322 323 let mayLoad = 0; 324 let mayStore = 0; 325 let hasSideEffects = 0; 326 let SALU = 1; 327 let SOPP = 1; 328 329 let UseNamedOperandTable = 1; 330} 331 332} // let SchedRW = [WriteSALU] 333 334class SMRD <dag outs, dag ins, string asm, list<dag> pattern> : 335 InstSI<outs, ins, asm, pattern> { 336 337 let LGKM_CNT = 1; 338 let SMRD = 1; 339 let mayStore = 0; 340 let mayLoad = 1; 341 let hasSideEffects = 0; 342 let UseNamedOperandTable = 1; 343 let SchedRW = [WriteSMEM]; 344} 345 346//===----------------------------------------------------------------------===// 347// Vector ALU operations 348//===----------------------------------------------------------------------===// 349 350class VOP1e <bits<8> op> : Enc32 { 351 bits<8> vdst; 352 bits<9> src0; 353 354 let Inst{8-0} = src0; 355 let Inst{16-9} = op; 356 let Inst{24-17} = vdst; 357 let Inst{31-25} = 0x3f; //encoding 358} 359 360class VOP2e <bits<6> op> : Enc32 { 361 bits<8> vdst; 362 bits<9> src0; 363 bits<8> src1; 364 365 let Inst{8-0} = src0; 366 let Inst{16-9} = src1; 367 let Inst{24-17} = vdst; 368 let Inst{30-25} = op; 369 let Inst{31} = 0x0; //encoding 370} 371 372class VOP2_MADKe <bits<6> op> : Enc64 { 373 374 bits<8> vdst; 375 bits<9> src0; 376 bits<8> src1; 377 bits<32> imm; 378 379 let Inst{8-0} = src0; 380 let Inst{16-9} = src1; 381 let Inst{24-17} = vdst; 382 let Inst{30-25} = op; 383 let Inst{31} = 0x0; // encoding 384 let Inst{63-32} = imm; 385} 386 387class VOP3a <bits<9> op> : Enc64 { 388 bits<2> src0_modifiers; 389 bits<9> src0; 390 bits<2> src1_modifiers; 391 bits<9> src1; 392 bits<2> src2_modifiers; 393 bits<9> src2; 394 bits<1> clamp; 395 bits<2> omod; 396 397 let Inst{8} = src0_modifiers{1}; 398 let Inst{9} = src1_modifiers{1}; 399 let Inst{10} = src2_modifiers{1}; 400 let Inst{11} = clamp; 401 let Inst{25-17} = op; 402 let Inst{31-26} = 0x34; //encoding 403 let Inst{40-32} = src0; 404 let Inst{49-41} = src1; 405 let Inst{58-50} = src2; 406 let Inst{60-59} = omod; 407 let Inst{61} = src0_modifiers{0}; 408 let Inst{62} = src1_modifiers{0}; 409 let Inst{63} = src2_modifiers{0}; 410} 411 412class VOP3e <bits<9> op> : VOP3a <op> { 413 bits<8> vdst; 414 415 let Inst{7-0} = vdst; 416} 417 418// Encoding used for VOPC instructions encoded as VOP3 419// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst 420class VOP3ce <bits<9> op> : VOP3a <op> { 421 bits<8> sdst; 422 423 let Inst{7-0} = sdst; 424} 425 426class VOP3be <bits<9> op> : Enc64 { 427 bits<8> vdst; 428 bits<2> src0_modifiers; 429 bits<9> src0; 430 bits<2> src1_modifiers; 431 bits<9> src1; 432 bits<2> src2_modifiers; 433 bits<9> src2; 434 bits<7> sdst; 435 bits<2> omod; 436 437 let Inst{7-0} = vdst; 438 let Inst{14-8} = sdst; 439 let Inst{25-17} = op; 440 let Inst{31-26} = 0x34; //encoding 441 let Inst{40-32} = src0; 442 let Inst{49-41} = src1; 443 let Inst{58-50} = src2; 444 let Inst{60-59} = omod; 445 let Inst{61} = src0_modifiers{0}; 446 let Inst{62} = src1_modifiers{0}; 447 let Inst{63} = src2_modifiers{0}; 448} 449 450class VOPCe <bits<8> op> : Enc32 { 451 bits<9> src0; 452 bits<8> src1; 453 454 let Inst{8-0} = src0; 455 let Inst{16-9} = src1; 456 let Inst{24-17} = op; 457 let Inst{31-25} = 0x3e; 458} 459 460class VINTRPe <bits<2> op> : Enc32 { 461 bits<8> vdst; 462 bits<8> vsrc; 463 bits<2> attrchan; 464 bits<6> attr; 465 466 let Inst{7-0} = vsrc; 467 let Inst{9-8} = attrchan; 468 let Inst{15-10} = attr; 469 let Inst{17-16} = op; 470 let Inst{25-18} = vdst; 471 let Inst{31-26} = 0x32; // encoding 472} 473 474class DSe <bits<8> op> : Enc64 { 475 bits<8> vdst; 476 bits<1> gds; 477 bits<8> addr; 478 bits<8> data0; 479 bits<8> data1; 480 bits<8> offset0; 481 bits<8> offset1; 482 483 let Inst{7-0} = offset0; 484 let Inst{15-8} = offset1; 485 let Inst{17} = gds; 486 let Inst{25-18} = op; 487 let Inst{31-26} = 0x36; //encoding 488 let Inst{39-32} = addr; 489 let Inst{47-40} = data0; 490 let Inst{55-48} = data1; 491 let Inst{63-56} = vdst; 492} 493 494class MUBUFe <bits<7> op> : Enc64 { 495 bits<12> offset; 496 bits<1> offen; 497 bits<1> idxen; 498 bits<1> glc; 499 bits<1> addr64; 500 bits<1> lds; 501 bits<8> vaddr; 502 bits<8> vdata; 503 bits<7> srsrc; 504 bits<1> slc; 505 bits<1> tfe; 506 bits<8> soffset; 507 508 let Inst{11-0} = offset; 509 let Inst{12} = offen; 510 let Inst{13} = idxen; 511 let Inst{14} = glc; 512 let Inst{15} = addr64; 513 let Inst{16} = lds; 514 let Inst{24-18} = op; 515 let Inst{31-26} = 0x38; //encoding 516 let Inst{39-32} = vaddr; 517 let Inst{47-40} = vdata; 518 let Inst{52-48} = srsrc{6-2}; 519 let Inst{54} = slc; 520 let Inst{55} = tfe; 521 let Inst{63-56} = soffset; 522} 523 524class MTBUFe <bits<3> op> : Enc64 { 525 bits<8> vdata; 526 bits<12> offset; 527 bits<1> offen; 528 bits<1> idxen; 529 bits<1> glc; 530 bits<1> addr64; 531 bits<4> dfmt; 532 bits<3> nfmt; 533 bits<8> vaddr; 534 bits<7> srsrc; 535 bits<1> slc; 536 bits<1> tfe; 537 bits<8> soffset; 538 539 let Inst{11-0} = offset; 540 let Inst{12} = offen; 541 let Inst{13} = idxen; 542 let Inst{14} = glc; 543 let Inst{15} = addr64; 544 let Inst{18-16} = op; 545 let Inst{22-19} = dfmt; 546 let Inst{25-23} = nfmt; 547 let Inst{31-26} = 0x3a; //encoding 548 let Inst{39-32} = vaddr; 549 let Inst{47-40} = vdata; 550 let Inst{52-48} = srsrc{6-2}; 551 let Inst{54} = slc; 552 let Inst{55} = tfe; 553 let Inst{63-56} = soffset; 554} 555 556class MIMGe <bits<7> op> : Enc64 { 557 bits<8> vdata; 558 bits<4> dmask; 559 bits<1> unorm; 560 bits<1> glc; 561 bits<1> da; 562 bits<1> r128; 563 bits<1> tfe; 564 bits<1> lwe; 565 bits<1> slc; 566 bits<8> vaddr; 567 bits<7> srsrc; 568 bits<7> ssamp; 569 570 let Inst{11-8} = dmask; 571 let Inst{12} = unorm; 572 let Inst{13} = glc; 573 let Inst{14} = da; 574 let Inst{15} = r128; 575 let Inst{16} = tfe; 576 let Inst{17} = lwe; 577 let Inst{24-18} = op; 578 let Inst{25} = slc; 579 let Inst{31-26} = 0x3c; 580 let Inst{39-32} = vaddr; 581 let Inst{47-40} = vdata; 582 let Inst{52-48} = srsrc{6-2}; 583 let Inst{57-53} = ssamp{6-2}; 584} 585 586class FLATe<bits<7> op> : Enc64 { 587 bits<8> addr; 588 bits<8> data; 589 bits<8> vdst; 590 bits<1> slc; 591 bits<1> glc; 592 bits<1> tfe; 593 594 // 15-0 is reserved. 595 let Inst{16} = glc; 596 let Inst{17} = slc; 597 let Inst{24-18} = op; 598 let Inst{31-26} = 0x37; // Encoding. 599 let Inst{39-32} = addr; 600 let Inst{47-40} = data; 601 // 54-48 is reserved. 602 let Inst{55} = tfe; 603 let Inst{63-56} = vdst; 604} 605 606class EXPe : Enc64 { 607 bits<4> en; 608 bits<6> tgt; 609 bits<1> compr; 610 bits<1> done; 611 bits<1> vm; 612 bits<8> vsrc0; 613 bits<8> vsrc1; 614 bits<8> vsrc2; 615 bits<8> vsrc3; 616 617 let Inst{3-0} = en; 618 let Inst{9-4} = tgt; 619 let Inst{10} = compr; 620 let Inst{11} = done; 621 let Inst{12} = vm; 622 let Inst{31-26} = 0x3e; 623 let Inst{39-32} = vsrc0; 624 let Inst{47-40} = vsrc1; 625 let Inst{55-48} = vsrc2; 626 let Inst{63-56} = vsrc3; 627} 628 629let Uses = [EXEC] in { 630 631class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> : 632 VOP1Common <outs, ins, asm, pattern>, 633 VOP1e<op> { 634 let isCodeGenOnly = 0; 635} 636 637class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> : 638 VOP2Common <outs, ins, asm, pattern>, VOP2e<op> { 639 let isCodeGenOnly = 0; 640} 641 642class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> : 643 VOPCCommon <ins, asm, pattern>, VOPCe <op>; 644 645class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> : 646 InstSI <outs, ins, asm, pattern> { 647 let mayLoad = 1; 648 let mayStore = 0; 649 let hasSideEffects = 0; 650} 651 652} // End Uses = [EXEC] 653 654//===----------------------------------------------------------------------===// 655// Vector I/O operations 656//===----------------------------------------------------------------------===// 657 658class DS <dag outs, dag ins, string asm, list<dag> pattern> : 659 InstSI <outs, ins, asm, pattern> { 660 661 let LGKM_CNT = 1; 662 let DS = 1; 663 let UseNamedOperandTable = 1; 664 let Uses = [M0, EXEC]; 665 666 // Most instruction load and store data, so set this as the default. 667 let mayLoad = 1; 668 let mayStore = 1; 669 670 let hasSideEffects = 0; 671 let AsmMatchConverter = "cvtDS"; 672 let SchedRW = [WriteLDS]; 673} 674 675class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> : 676 InstSI<outs, ins, asm, pattern> { 677 678 let VM_CNT = 1; 679 let EXP_CNT = 1; 680 let MUBUF = 1; 681 let Uses = [EXEC]; 682 683 let hasSideEffects = 0; 684 let UseNamedOperandTable = 1; 685 let AsmMatchConverter = "cvtMubuf"; 686 let SchedRW = [WriteVMEM]; 687} 688 689class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> : 690 InstSI<outs, ins, asm, pattern> { 691 692 let VM_CNT = 1; 693 let EXP_CNT = 1; 694 let MTBUF = 1; 695 let Uses = [EXEC]; 696 697 let hasSideEffects = 0; 698 let UseNamedOperandTable = 1; 699 let SchedRW = [WriteVMEM]; 700} 701 702class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 703 InstSI<outs, ins, asm, pattern>, FLATe <op> { 704 let FLAT = 1; 705 // Internally, FLAT instruction are executed as both an LDS and a 706 // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT 707 // and are not considered done until both have been decremented. 708 let VM_CNT = 1; 709 let LGKM_CNT = 1; 710 711 let Uses = [EXEC, FLAT_SCR]; // M0 712 713 let UseNamedOperandTable = 1; 714 let hasSideEffects = 0; 715 let SchedRW = [WriteVMEM]; 716} 717 718class MIMG <dag outs, dag ins, string asm, list<dag> pattern> : 719 InstSI <outs, ins, asm, pattern> { 720 721 let VM_CNT = 1; 722 let EXP_CNT = 1; 723 let MIMG = 1; 724 let Uses = [EXEC]; 725 726 let UseNamedOperandTable = 1; 727 let hasSideEffects = 0; // XXX ???? 728} 729