1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// SI Instruction format definitions. 11// 12//===----------------------------------------------------------------------===// 13 14class InstSI <dag outs, dag ins, string asm, list<dag> pattern> : 15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl { 16 17 field bits<1> VM_CNT = 0; 18 field bits<1> EXP_CNT = 0; 19 field bits<1> LGKM_CNT = 0; 20 21 field bits<1> SALU = 0; 22 field bits<1> VALU = 0; 23 24 field bits<1> SOP1 = 0; 25 field bits<1> SOP2 = 0; 26 field bits<1> SOPC = 0; 27 field bits<1> SOPK = 0; 28 field bits<1> SOPP = 0; 29 30 field bits<1> VOP1 = 0; 31 field bits<1> VOP2 = 0; 32 field bits<1> VOP3 = 0; 33 field bits<1> VOPC = 0; 34 field bits<1> DPP = 0; 35 36 field bits<1> MUBUF = 0; 37 field bits<1> MTBUF = 0; 38 field bits<1> SMRD = 0; 39 field bits<1> DS = 0; 40 field bits<1> MIMG = 0; 41 field bits<1> FLAT = 0; 42 field bits<1> WQM = 0; 43 field bits<1> VGPRSpill = 0; 44 45 // This bit tells the assembler to use the 32-bit encoding in case it 46 // is unable to infer the encoding from the operands. 47 field bits<1> VOPAsmPrefer32Bit = 0; 48 49 // These need to be kept in sync with the enum in SIInstrFlags. 50 let TSFlags{0} = VM_CNT; 51 let TSFlags{1} = EXP_CNT; 52 let TSFlags{2} = LGKM_CNT; 53 54 let TSFlags{3} = SALU; 55 let TSFlags{4} = VALU; 56 57 let TSFlags{5} = SOP1; 58 let TSFlags{6} = SOP2; 59 let TSFlags{7} = SOPC; 60 let TSFlags{8} = SOPK; 61 let TSFlags{9} = SOPP; 62 63 let TSFlags{10} = VOP1; 64 let TSFlags{11} = VOP2; 65 let TSFlags{12} = VOP3; 66 let TSFlags{13} = VOPC; 67 let TSFlags{14} = DPP; 68 69 let TSFlags{15} = MUBUF; 70 let TSFlags{16} = MTBUF; 71 let TSFlags{17} = SMRD; 72 let TSFlags{18} = DS; 73 let TSFlags{19} = MIMG; 74 let TSFlags{20} = FLAT; 75 let TSFlags{21} = WQM; 76 let TSFlags{22} = VGPRSpill; 77 let TSFlags{23} = VOPAsmPrefer32Bit; 78 79 let SchedRW = [Write32Bit]; 80 81 field bits<1> DisableSIDecoder = 0; 82 field bits<1> DisableVIDecoder = 0; 83 field bits<1> DisableDecoder = 0; 84 85 let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1); 86} 87 88class Enc32 { 89 field bits<32> Inst; 90 int Size = 4; 91} 92 93class Enc64 { 94 field bits<64> Inst; 95 int Size = 8; 96} 97 98class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">; 99 100let Uses = [EXEC] in { 101 102class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> : 103 InstSI <outs, ins, asm, pattern> { 104 105 let mayLoad = 0; 106 let mayStore = 0; 107 let hasSideEffects = 0; 108 let UseNamedOperandTable = 1; 109 let VALU = 1; 110} 111 112class VOPCCommon <dag ins, string asm, list<dag> pattern> : 113 VOPAnyCommon <(outs), ins, asm, pattern> { 114 115 let VOPC = 1; 116 let Size = 4; 117 let Defs = [VCC]; 118} 119 120class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> : 121 VOPAnyCommon <outs, ins, asm, pattern> { 122 123 let VOP1 = 1; 124 let Size = 4; 125} 126 127class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> : 128 VOPAnyCommon <outs, ins, asm, pattern> { 129 130 let VOP2 = 1; 131 let Size = 4; 132} 133 134class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern, bit HasMods = 0, bit VOP3Only = 0> : 135 VOPAnyCommon <outs, ins, asm, pattern> { 136 137 // Using complex patterns gives VOP3 patterns a very high complexity rating, 138 // but standalone patterns are almost always prefered, so we need to adjust the 139 // priority lower. The goal is to use a high number to reduce complexity to 140 // zero (or less than zero). 141 let AddedComplexity = -1000; 142 143 let VOP3 = 1; 144 let VALU = 1; 145 146 let AsmMatchConverter = 147 !if(!eq(VOP3Only,1), 148 "cvtVOP3_only", 149 !if(!eq(HasMods,1), "cvtVOP3_2_mod", "cvtVOP3_2_nomod")); 150 let isCodeGenOnly = 0; 151 152 int Size = 8; 153 154 // Because SGPRs may be allowed if there are multiple operands, we 155 // need a post-isel hook to insert copies in order to avoid 156 // violating constant bus requirements. 157 let hasPostISelHook = 1; 158} 159 160} // End Uses = [EXEC] 161 162//===----------------------------------------------------------------------===// 163// Scalar operations 164//===----------------------------------------------------------------------===// 165 166class SOP1e <bits<8> op> : Enc32 { 167 bits<7> sdst; 168 bits<8> src0; 169 170 let Inst{7-0} = src0; 171 let Inst{15-8} = op; 172 let Inst{22-16} = sdst; 173 let Inst{31-23} = 0x17d; //encoding; 174} 175 176class SOP2e <bits<7> op> : Enc32 { 177 bits<7> sdst; 178 bits<8> src0; 179 bits<8> src1; 180 181 let Inst{7-0} = src0; 182 let Inst{15-8} = src1; 183 let Inst{22-16} = sdst; 184 let Inst{29-23} = op; 185 let Inst{31-30} = 0x2; // encoding 186} 187 188class SOPCe <bits<7> op> : Enc32 { 189 bits<8> src0; 190 bits<8> src1; 191 192 let Inst{7-0} = src0; 193 let Inst{15-8} = src1; 194 let Inst{22-16} = op; 195 let Inst{31-23} = 0x17e; 196} 197 198class SOPKe <bits<5> op> : Enc32 { 199 bits <7> sdst; 200 bits <16> simm16; 201 202 let Inst{15-0} = simm16; 203 let Inst{22-16} = sdst; 204 let Inst{27-23} = op; 205 let Inst{31-28} = 0xb; //encoding 206} 207 208class SOPK64e <bits<5> op> : Enc64 { 209 bits <7> sdst = 0; 210 bits <16> simm16; 211 bits <32> imm; 212 213 let Inst{15-0} = simm16; 214 let Inst{22-16} = sdst; 215 let Inst{27-23} = op; 216 let Inst{31-28} = 0xb; 217 218 let Inst{63-32} = imm; 219} 220 221class SOPPe <bits<7> op> : Enc32 { 222 bits <16> simm16; 223 224 let Inst{15-0} = simm16; 225 let Inst{22-16} = op; 226 let Inst{31-23} = 0x17f; // encoding 227} 228 229class SMRDe <bits<5> op, bits<1> imm> : Enc32 { 230 bits<7> sdst; 231 bits<7> sbase; 232 233 let Inst{8} = imm; 234 let Inst{14-9} = sbase{6-1}; 235 let Inst{21-15} = sdst; 236 let Inst{26-22} = op; 237 let Inst{31-27} = 0x18; //encoding 238} 239 240class SMRD_IMMe <bits<5> op> : SMRDe<op, 1> { 241 bits<8> offset; 242 let Inst{7-0} = offset; 243} 244 245class SMRD_SOFFe <bits<5> op> : SMRDe<op, 0> { 246 bits<8> soff; 247 let Inst{7-0} = soff; 248} 249 250 251 252class SMRD_IMMe_ci <bits<5> op> : Enc64 { 253 bits<7> sdst; 254 bits<7> sbase; 255 bits<32> offset; 256 257 let Inst{7-0} = 0xff; 258 let Inst{8} = 0; 259 let Inst{14-9} = sbase{6-1}; 260 let Inst{21-15} = sdst; 261 let Inst{26-22} = op; 262 let Inst{31-27} = 0x18; //encoding 263 let Inst{63-32} = offset; 264} 265 266let SchedRW = [WriteSALU] in { 267class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> : 268 InstSI<outs, ins, asm, pattern> { 269 let mayLoad = 0; 270 let mayStore = 0; 271 let hasSideEffects = 0; 272 let isCodeGenOnly = 0; 273 let SALU = 1; 274 let SOP1 = 1; 275} 276 277class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> : 278 InstSI <outs, ins, asm, pattern> { 279 280 let mayLoad = 0; 281 let mayStore = 0; 282 let hasSideEffects = 0; 283 let isCodeGenOnly = 0; 284 let SALU = 1; 285 let SOP2 = 1; 286 287 let UseNamedOperandTable = 1; 288} 289 290class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 291 InstSI<outs, ins, asm, pattern>, SOPCe <op> { 292 293 let mayLoad = 0; 294 let mayStore = 0; 295 let hasSideEffects = 0; 296 let SALU = 1; 297 let SOPC = 1; 298 let isCodeGenOnly = 0; 299 let Defs = [SCC]; 300 301 let UseNamedOperandTable = 1; 302} 303 304class SOPK <dag outs, dag ins, string asm, list<dag> pattern> : 305 InstSI <outs, ins , asm, pattern> { 306 307 let mayLoad = 0; 308 let mayStore = 0; 309 let hasSideEffects = 0; 310 let SALU = 1; 311 let SOPK = 1; 312 313 let UseNamedOperandTable = 1; 314} 315 316class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> : 317 InstSI <(outs), ins, asm, pattern >, SOPPe <op> { 318 319 let mayLoad = 0; 320 let mayStore = 0; 321 let hasSideEffects = 0; 322 let SALU = 1; 323 let SOPP = 1; 324 325 let UseNamedOperandTable = 1; 326} 327 328} // let SchedRW = [WriteSALU] 329 330class SMRD <dag outs, dag ins, string asm, list<dag> pattern> : 331 InstSI<outs, ins, asm, pattern> { 332 333 let LGKM_CNT = 1; 334 let SMRD = 1; 335 let mayStore = 0; 336 let mayLoad = 1; 337 let hasSideEffects = 0; 338 let UseNamedOperandTable = 1; 339 let SchedRW = [WriteSMEM]; 340} 341 342//===----------------------------------------------------------------------===// 343// Vector ALU operations 344//===----------------------------------------------------------------------===// 345 346class VOP1e <bits<8> op> : Enc32 { 347 bits<8> vdst; 348 bits<9> src0; 349 350 let Inst{8-0} = src0; 351 let Inst{16-9} = op; 352 let Inst{24-17} = vdst; 353 let Inst{31-25} = 0x3f; //encoding 354} 355 356class VOP2e <bits<6> op> : Enc32 { 357 bits<8> vdst; 358 bits<9> src0; 359 bits<8> src1; 360 361 let Inst{8-0} = src0; 362 let Inst{16-9} = src1; 363 let Inst{24-17} = vdst; 364 let Inst{30-25} = op; 365 let Inst{31} = 0x0; //encoding 366} 367 368class VOP2_MADKe <bits<6> op> : Enc64 { 369 370 bits<8> vdst; 371 bits<9> src0; 372 bits<8> vsrc1; 373 bits<32> src2; 374 375 let Inst{8-0} = src0; 376 let Inst{16-9} = vsrc1; 377 let Inst{24-17} = vdst; 378 let Inst{30-25} = op; 379 let Inst{31} = 0x0; // encoding 380 let Inst{63-32} = src2; 381} 382 383class VOP3a <bits<9> op> : Enc64 { 384 bits<2> src0_modifiers; 385 bits<9> src0; 386 bits<2> src1_modifiers; 387 bits<9> src1; 388 bits<2> src2_modifiers; 389 bits<9> src2; 390 bits<1> clamp; 391 bits<2> omod; 392 393 let Inst{8} = src0_modifiers{1}; 394 let Inst{9} = src1_modifiers{1}; 395 let Inst{10} = src2_modifiers{1}; 396 let Inst{11} = clamp; 397 let Inst{25-17} = op; 398 let Inst{31-26} = 0x34; //encoding 399 let Inst{40-32} = src0; 400 let Inst{49-41} = src1; 401 let Inst{58-50} = src2; 402 let Inst{60-59} = omod; 403 let Inst{61} = src0_modifiers{0}; 404 let Inst{62} = src1_modifiers{0}; 405 let Inst{63} = src2_modifiers{0}; 406} 407 408class VOP3e <bits<9> op> : VOP3a <op> { 409 bits<8> vdst; 410 411 let Inst{7-0} = vdst; 412} 413 414// Encoding used for VOPC instructions encoded as VOP3 415// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst 416class VOP3ce <bits<9> op> : VOP3a <op> { 417 bits<8> sdst; 418 419 let Inst{7-0} = sdst; 420} 421 422class VOP3be <bits<9> op> : Enc64 { 423 bits<8> vdst; 424 bits<2> src0_modifiers; 425 bits<9> src0; 426 bits<2> src1_modifiers; 427 bits<9> src1; 428 bits<2> src2_modifiers; 429 bits<9> src2; 430 bits<7> sdst; 431 bits<2> omod; 432 433 let Inst{7-0} = vdst; 434 let Inst{14-8} = sdst; 435 let Inst{25-17} = op; 436 let Inst{31-26} = 0x34; //encoding 437 let Inst{40-32} = src0; 438 let Inst{49-41} = src1; 439 let Inst{58-50} = src2; 440 let Inst{60-59} = omod; 441 let Inst{61} = src0_modifiers{0}; 442 let Inst{62} = src1_modifiers{0}; 443 let Inst{63} = src2_modifiers{0}; 444} 445 446class VOPCe <bits<8> op> : Enc32 { 447 bits<9> src0; 448 bits<8> src1; 449 450 let Inst{8-0} = src0; 451 let Inst{16-9} = src1; 452 let Inst{24-17} = op; 453 let Inst{31-25} = 0x3e; 454} 455 456class VINTRPe <bits<2> op> : Enc32 { 457 bits<8> vdst; 458 bits<8> vsrc; 459 bits<2> attrchan; 460 bits<6> attr; 461 462 let Inst{7-0} = vsrc; 463 let Inst{9-8} = attrchan; 464 let Inst{15-10} = attr; 465 let Inst{17-16} = op; 466 let Inst{25-18} = vdst; 467 let Inst{31-26} = 0x32; // encoding 468} 469 470class DSe <bits<8> op> : Enc64 { 471 bits<8> vdst; 472 bits<1> gds; 473 bits<8> addr; 474 bits<8> data0; 475 bits<8> data1; 476 bits<8> offset0; 477 bits<8> offset1; 478 479 let Inst{7-0} = offset0; 480 let Inst{15-8} = offset1; 481 let Inst{17} = gds; 482 let Inst{25-18} = op; 483 let Inst{31-26} = 0x36; //encoding 484 let Inst{39-32} = addr; 485 let Inst{47-40} = data0; 486 let Inst{55-48} = data1; 487 let Inst{63-56} = vdst; 488} 489 490class MUBUFe <bits<7> op> : Enc64 { 491 bits<12> offset; 492 bits<1> offen; 493 bits<1> idxen; 494 bits<1> glc; 495 bits<1> addr64; 496 bits<1> lds; 497 bits<8> vaddr; 498 bits<8> vdata; 499 bits<7> srsrc; 500 bits<1> slc; 501 bits<1> tfe; 502 bits<8> soffset; 503 504 let Inst{11-0} = offset; 505 let Inst{12} = offen; 506 let Inst{13} = idxen; 507 let Inst{14} = glc; 508 let Inst{15} = addr64; 509 let Inst{16} = lds; 510 let Inst{24-18} = op; 511 let Inst{31-26} = 0x38; //encoding 512 let Inst{39-32} = vaddr; 513 let Inst{47-40} = vdata; 514 let Inst{52-48} = srsrc{6-2}; 515 let Inst{54} = slc; 516 let Inst{55} = tfe; 517 let Inst{63-56} = soffset; 518} 519 520class MTBUFe <bits<3> op> : Enc64 { 521 bits<8> vdata; 522 bits<12> offset; 523 bits<1> offen; 524 bits<1> idxen; 525 bits<1> glc; 526 bits<1> addr64; 527 bits<4> dfmt; 528 bits<3> nfmt; 529 bits<8> vaddr; 530 bits<7> srsrc; 531 bits<1> slc; 532 bits<1> tfe; 533 bits<8> soffset; 534 535 let Inst{11-0} = offset; 536 let Inst{12} = offen; 537 let Inst{13} = idxen; 538 let Inst{14} = glc; 539 let Inst{15} = addr64; 540 let Inst{18-16} = op; 541 let Inst{22-19} = dfmt; 542 let Inst{25-23} = nfmt; 543 let Inst{31-26} = 0x3a; //encoding 544 let Inst{39-32} = vaddr; 545 let Inst{47-40} = vdata; 546 let Inst{52-48} = srsrc{6-2}; 547 let Inst{54} = slc; 548 let Inst{55} = tfe; 549 let Inst{63-56} = soffset; 550} 551 552class MIMGe <bits<7> op> : Enc64 { 553 bits<8> vdata; 554 bits<4> dmask; 555 bits<1> unorm; 556 bits<1> glc; 557 bits<1> da; 558 bits<1> r128; 559 bits<1> tfe; 560 bits<1> lwe; 561 bits<1> slc; 562 bits<8> vaddr; 563 bits<7> srsrc; 564 bits<7> ssamp; 565 566 let Inst{11-8} = dmask; 567 let Inst{12} = unorm; 568 let Inst{13} = glc; 569 let Inst{14} = da; 570 let Inst{15} = r128; 571 let Inst{16} = tfe; 572 let Inst{17} = lwe; 573 let Inst{24-18} = op; 574 let Inst{25} = slc; 575 let Inst{31-26} = 0x3c; 576 let Inst{39-32} = vaddr; 577 let Inst{47-40} = vdata; 578 let Inst{52-48} = srsrc{6-2}; 579 let Inst{57-53} = ssamp{6-2}; 580} 581 582class FLATe<bits<7> op> : Enc64 { 583 bits<8> addr; 584 bits<8> data; 585 bits<8> vdst; 586 bits<1> slc; 587 bits<1> glc; 588 bits<1> tfe; 589 590 // 15-0 is reserved. 591 let Inst{16} = glc; 592 let Inst{17} = slc; 593 let Inst{24-18} = op; 594 let Inst{31-26} = 0x37; // Encoding. 595 let Inst{39-32} = addr; 596 let Inst{47-40} = data; 597 // 54-48 is reserved. 598 let Inst{55} = tfe; 599 let Inst{63-56} = vdst; 600} 601 602class EXPe : Enc64 { 603 bits<4> en; 604 bits<6> tgt; 605 bits<1> compr; 606 bits<1> done; 607 bits<1> vm; 608 bits<8> vsrc0; 609 bits<8> vsrc1; 610 bits<8> vsrc2; 611 bits<8> vsrc3; 612 613 let Inst{3-0} = en; 614 let Inst{9-4} = tgt; 615 let Inst{10} = compr; 616 let Inst{11} = done; 617 let Inst{12} = vm; 618 let Inst{31-26} = 0x3e; 619 let Inst{39-32} = vsrc0; 620 let Inst{47-40} = vsrc1; 621 let Inst{55-48} = vsrc2; 622 let Inst{63-56} = vsrc3; 623} 624 625let Uses = [EXEC] in { 626 627class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> : 628 VOP1Common <outs, ins, asm, pattern>, 629 VOP1e<op> { 630 let isCodeGenOnly = 0; 631} 632 633class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> : 634 VOP2Common <outs, ins, asm, pattern>, VOP2e<op> { 635 let isCodeGenOnly = 0; 636} 637 638class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> : 639 VOPCCommon <ins, asm, pattern>, VOPCe <op>; 640 641class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> : 642 InstSI <outs, ins, asm, pattern> { 643 let mayLoad = 1; 644 let mayStore = 0; 645 let hasSideEffects = 0; 646} 647 648} // End Uses = [EXEC] 649 650//===----------------------------------------------------------------------===// 651// Vector I/O operations 652//===----------------------------------------------------------------------===// 653 654class DS <dag outs, dag ins, string asm, list<dag> pattern> : 655 InstSI <outs, ins, asm, pattern> { 656 657 let LGKM_CNT = 1; 658 let DS = 1; 659 let UseNamedOperandTable = 1; 660 let Uses = [M0, EXEC]; 661 662 // Most instruction load and store data, so set this as the default. 663 let mayLoad = 1; 664 let mayStore = 1; 665 666 let hasSideEffects = 0; 667 let AsmMatchConverter = "cvtDS"; 668 let SchedRW = [WriteLDS]; 669} 670 671class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> : 672 InstSI<outs, ins, asm, pattern> { 673 674 let VM_CNT = 1; 675 let EXP_CNT = 1; 676 let MUBUF = 1; 677 let Uses = [EXEC]; 678 679 let hasSideEffects = 0; 680 let UseNamedOperandTable = 1; 681 let AsmMatchConverter = "cvtMubuf"; 682 let SchedRW = [WriteVMEM]; 683} 684 685class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> : 686 InstSI<outs, ins, asm, pattern> { 687 688 let VM_CNT = 1; 689 let EXP_CNT = 1; 690 let MTBUF = 1; 691 let Uses = [EXEC]; 692 693 let hasSideEffects = 0; 694 let UseNamedOperandTable = 1; 695 let SchedRW = [WriteVMEM]; 696} 697 698class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 699 InstSI<outs, ins, asm, pattern>, FLATe <op> { 700 let FLAT = 1; 701 // Internally, FLAT instruction are executed as both an LDS and a 702 // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT 703 // and are not considered done until both have been decremented. 704 let VM_CNT = 1; 705 let LGKM_CNT = 1; 706 707 let Uses = [EXEC, FLAT_SCR]; // M0 708 709 let UseNamedOperandTable = 1; 710 let hasSideEffects = 0; 711 let AsmMatchConverter = "cvtFlat"; 712 let SchedRW = [WriteVMEM]; 713} 714 715class MIMG <dag outs, dag ins, string asm, list<dag> pattern> : 716 InstSI <outs, ins, asm, pattern> { 717 718 let VM_CNT = 1; 719 let EXP_CNT = 1; 720 let MIMG = 1; 721 let Uses = [EXEC]; 722 723 let UseNamedOperandTable = 1; 724 let hasSideEffects = 0; // XXX ???? 725} 726