1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// SI Instruction format definitions.
10//
11//===----------------------------------------------------------------------===//
12
13class InstSI <dag outs, dag ins, string asm = "",
14              list<dag> pattern = []> :
15  AMDGPUInst<outs, ins, asm, pattern>, GCNPredicateControl {
16  // Low bits - basic encoding information.
17  field bit SALU = 0;
18  field bit VALU = 0;
19
20  // SALU instruction formats.
21  field bit SOP1 = 0;
22  field bit SOP2 = 0;
23  field bit SOPC = 0;
24  field bit SOPK = 0;
25  field bit SOPP = 0;
26
27  // VALU instruction formats.
28  field bit VOP1 = 0;
29  field bit VOP2 = 0;
30  field bit VOPC = 0;
31  field bit VOP3 = 0;
32  field bit VOP3P = 0;
33  field bit VINTRP = 0;
34  field bit SDWA = 0;
35  field bit DPP = 0;
36  field bit TRANS = 0;
37
38  // Memory instruction formats.
39  field bit MUBUF = 0;
40  field bit MTBUF = 0;
41  field bit SMRD = 0;
42  field bit MIMG = 0;
43  field bit EXP = 0;
44  field bit FLAT = 0;
45  field bit DS = 0;
46
47  // Pseudo instruction formats.
48  field bit VGPRSpill = 0;
49  field bit SGPRSpill = 0;
50
51  // LDSDIR instruction format.
52  field bit LDSDIR = 0;
53
54  // VINTERP instruction format.
55  field bit VINTERP = 0;
56
57  // High bits - other information.
58  field bit VM_CNT = 0;
59  field bit EXP_CNT = 0;
60  field bit LGKM_CNT = 0;
61
62  // Whether WQM _must_ be enabled for this instruction.
63  field bit WQM = 0;
64
65  // Whether WQM _must_ be disabled for this instruction.
66  field bit DisableWQM = 0;
67
68  field bit Gather4 = 0;
69
70  // Most sopk treat the immediate as a signed 16-bit, however some
71  // use it as unsigned.
72  field bit SOPKZext = 0;
73
74  // This is an s_store_dword* instruction that requires a cache flush
75  // on wave termination. It is necessary to distinguish from mayStore
76  // SMEM instructions like the cache flush ones.
77  field bit ScalarStore = 0;
78
79  // Whether the operands can be ignored when computing the
80  // instruction size.
81  field bit FixedSize = 0;
82
83  // This bit tells the assembler to use the 32-bit encoding in case it
84  // is unable to infer the encoding from the operands.
85  field bit VOPAsmPrefer32Bit = 0;
86
87  // This bit indicates that this is a VOP3 opcode which supports op_sel
88  // modifier (gfx9 only).
89  field bit VOP3_OPSEL = 0;
90
91  // Is it possible for this instruction to be atomic?
92  field bit maybeAtomic = 0;
93
94  // This bit indicates that this is a VI instruction which is renamed
95  // in GFX9. Required for correct mapping from pseudo to MC.
96  field bit renamedInGFX9 = 0;
97
98  // This bit indicates that this has a floating point result type, so
99  // the clamp modifier has floating point semantics.
100  field bit FPClamp = 0;
101
102  // This bit indicates that instruction may support integer clamping
103  // which depends on GPU features.
104  field bit IntClamp = 0;
105
106  // This field indicates that the clamp applies to the low component
107  // of a packed output register.
108  field bit ClampLo = 0;
109
110  // This field indicates that the clamp applies to the high component
111  // of a packed output register.
112  field bit ClampHi = 0;
113
114  // This bit indicates that this is a packed VOP3P instruction
115  field bit IsPacked = 0;
116
117  // This bit indicates that this is a D16 buffer instruction.
118  field bit D16Buf = 0;
119
120  // This field indicates that FLAT instruction accesses FLAT_GLBL segment.
121  // Must be 0 for non-FLAT instructions.
122  field bit FlatGlobal = 0;
123
124  // Reads the mode register, usually for FP environment.
125  field bit ReadsModeReg = 0;
126
127  // This bit indicates that this uses the floating point double precision
128  // rounding mode flags
129  field bit FPDPRounding = 0;
130
131  // Instruction is FP atomic.
132  field bit FPAtomic = 0;
133
134  // This bit indicates that this is one of MFMA instructions.
135  field bit IsMAI = 0;
136
137  // This bit indicates that this is one of DOT instructions.
138  field bit IsDOT = 0;
139
140  // This field indicates that FLAT instruction accesses FLAT_SCRATCH segment.
141  // Must be 0 for non-FLAT instructions.
142  field bit FlatScratch = 0;
143
144  // Atomic without a return.
145  field bit IsAtomicNoRet = 0;
146
147  // Atomic with return.
148  field bit IsAtomicRet = 0;
149
150  // These need to be kept in sync with the enum in SIInstrFlags.
151  let TSFlags{0} = SALU;
152  let TSFlags{1} = VALU;
153
154  let TSFlags{2} = SOP1;
155  let TSFlags{3} = SOP2;
156  let TSFlags{4} = SOPC;
157  let TSFlags{5} = SOPK;
158  let TSFlags{6} = SOPP;
159
160  let TSFlags{7} = VOP1;
161  let TSFlags{8} = VOP2;
162  let TSFlags{9} = VOPC;
163  let TSFlags{10} = VOP3;
164  let TSFlags{12} = VOP3P;
165
166  let TSFlags{13} = VINTRP;
167  let TSFlags{14} = SDWA;
168  let TSFlags{15} = DPP;
169  let TSFlags{16} = TRANS;
170
171  let TSFlags{17} = MUBUF;
172  let TSFlags{18} = MTBUF;
173  let TSFlags{19} = SMRD;
174  let TSFlags{20} = MIMG;
175  let TSFlags{21} = EXP;
176  let TSFlags{22} = FLAT;
177  let TSFlags{23} = DS;
178
179  let TSFlags{24} = VGPRSpill;
180  let TSFlags{25} = SGPRSpill;
181
182  let TSFlags{26} = LDSDIR;
183  let TSFlags{27} = VINTERP;
184
185  let TSFlags{32} = VM_CNT;
186  let TSFlags{33} = EXP_CNT;
187  let TSFlags{34} = LGKM_CNT;
188
189  let TSFlags{35} = WQM;
190  let TSFlags{36} = DisableWQM;
191  let TSFlags{37} = Gather4;
192
193  let TSFlags{38} = SOPKZext;
194  let TSFlags{39} = ScalarStore;
195  let TSFlags{40} = FixedSize;
196  let TSFlags{41} = VOPAsmPrefer32Bit;
197  let TSFlags{42} = VOP3_OPSEL;
198
199  let TSFlags{43} = maybeAtomic;
200  let TSFlags{44} = renamedInGFX9;
201
202  let TSFlags{45} = FPClamp;
203  let TSFlags{46} = IntClamp;
204  let TSFlags{47} = ClampLo;
205  let TSFlags{48} = ClampHi;
206
207  let TSFlags{49} = IsPacked;
208
209  let TSFlags{50} = D16Buf;
210
211  let TSFlags{51} = FlatGlobal;
212
213  let TSFlags{52} = FPDPRounding;
214
215  let TSFlags{53} = FPAtomic;
216
217  let TSFlags{54} = IsMAI;
218
219  let TSFlags{55} = IsDOT;
220
221  let TSFlags{56} = FlatScratch;
222
223  let TSFlags{57} = IsAtomicNoRet;
224
225  let TSFlags{58} = IsAtomicRet;
226
227  let SchedRW = [Write32Bit];
228
229  let AsmVariantName = AMDGPUAsmVariants.Default;
230
231  // Avoid changing source registers in a way that violates constant bus read limitations.
232  let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
233}
234
235class PseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
236  : InstSI<outs, ins, asm, pattern> {
237  let isPseudo = 1;
238  let isCodeGenOnly = 1;
239}
240
241class SPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
242  : PseudoInstSI<outs, ins, pattern, asm> {
243  let SALU = 1;
244}
245
246class VPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
247  : PseudoInstSI<outs, ins, pattern, asm> {
248  let VALU = 1;
249  let Uses = [EXEC];
250}
251
252class CFPseudoInstSI<dag outs, dag ins, list<dag> pattern = [],
253  bit UseExec = 0, bit DefExec = 0> :
254  SPseudoInstSI<outs, ins, pattern> {
255
256  let Uses = !if(UseExec, [EXEC], []);
257  let Defs = !if(DefExec, [EXEC, SCC], [SCC]);
258  let mayLoad = 0;
259  let mayStore = 0;
260  let hasSideEffects = 0;
261}
262
263class Enc32 {
264  field bits<32> Inst;
265  int Size = 4;
266}
267
268class Enc64 {
269  field bits<64> Inst;
270  int Size = 8;
271}
272
273def CPolBit {
274  int GLC = 0;
275  int SLC = 1;
276  int DLC = 2;
277  int SCC = 4;
278}
279
280class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
281
282class VINTRPe <bits<2> op> : Enc32 {
283  bits<8> vdst;
284  bits<8> vsrc;
285  bits<2> attrchan;
286  bits<6> attr;
287
288  let Inst{7-0} = vsrc;
289  let Inst{9-8} = attrchan;
290  let Inst{15-10} = attr;
291  let Inst{17-16} = op;
292  let Inst{25-18} = vdst;
293  let Inst{31-26} = 0x32; // encoding
294}
295
296class MIMGe_gfxpre11 : Enc64 {
297  bits<10> vdata;
298  bits<4> dmask;
299  bits<1> unorm;
300  bits<5> cpol;
301  bits<1> r128;
302  bits<1> tfe;
303  bits<1> lwe;
304  bit d16;
305  bits<7> srsrc;
306  bits<7> ssamp;
307
308  let Inst{11-8} = dmask;
309  let Inst{12} = unorm;
310  let Inst{13} = cpol{CPolBit.GLC};
311  let Inst{15} = r128;
312  let Inst{17} = lwe;
313  let Inst{25} = cpol{CPolBit.SLC};
314  let Inst{31-26} = 0x3c;
315  let Inst{47-40} = vdata{7-0};
316  let Inst{52-48} = srsrc{6-2};
317  let Inst{57-53} = ssamp{6-2};
318  let Inst{63} = d16;
319}
320
321class MIMGe_gfx6789 <bits<8> op> : MIMGe_gfxpre11 {
322  bits<8> vaddr;
323  bits<1> da;
324
325  let Inst{0} = op{7};
326  let Inst{7} = cpol{CPolBit.SCC};
327  let Inst{14} = da;
328  let Inst{16} = tfe;
329  let Inst{24-18} = op{6-0};
330  let Inst{39-32} = vaddr;
331}
332
333class MIMGe_gfx90a <bits<8> op> : MIMGe_gfxpre11 {
334  bits<8> vaddr;
335  bits<1> da;
336
337  let Inst{0} = op{7};
338  let Inst{7} = cpol{CPolBit.SCC};
339  let Inst{14} = da;
340  let Inst{16} = vdata{9}; // ACC bit
341  let Inst{24-18} = op{6-0};
342  let Inst{39-32} = vaddr;
343}
344
345class MIMGe_gfx10 <bits<8> op> : MIMGe_gfxpre11 {
346  bits<8> vaddr0;
347  bits<3> dim;
348  bits<2> nsa;
349  bits<1> a16;
350
351  let Inst{0} = op{7};
352  let Inst{2-1} = nsa;
353  let Inst{5-3} = dim;
354  let Inst{7} = cpol{CPolBit.DLC};
355  let Inst{16} = tfe;
356  let Inst{24-18} = op{6-0};
357  let Inst{39-32} = vaddr0;
358  let Inst{62} = a16;
359}
360
361class MIMGe_gfx11 <bits<8> op> : Enc64 {
362  bits<8> vdata;
363  bits<4> dmask;
364  bits<1> unorm;
365  bits<5> cpol;
366  bits<1> r128;
367  bits<1> tfe;
368  bits<1> lwe;
369  bits<7> srsrc;
370  bits<7> ssamp;
371  bit d16;
372  bits<1> a16;
373  bits<8> vaddr0;
374  bits<3> dim;
375  bits<1> nsa;
376
377  let Inst{0} = nsa;
378  let Inst{4-2} = dim;
379  let Inst{7} = unorm;
380  let Inst{11-8} = dmask;
381  let Inst{12} = cpol{CPolBit.SLC};
382  let Inst{13} = cpol{CPolBit.DLC};
383  let Inst{14} = cpol{CPolBit.GLC};
384  let Inst{15} = r128;
385  let Inst{16} = a16;
386  let Inst{17} = d16;
387  let Inst{25-18} = op;
388  let Inst{31-26} = 0x3c;
389  let Inst{39-32} = vaddr0;
390  let Inst{47-40} = vdata;
391  let Inst{52-48} = srsrc{6-2};
392  let Inst{53} = tfe;
393  let Inst{54} = lwe;
394  let Inst{62-58} = ssamp{6-2};
395}
396
397class EXPe : Enc64 {
398  bits<4> en;
399  bits<6> tgt;
400  bits<1> done;
401  bits<8> src0;
402  bits<8> src1;
403  bits<8> src2;
404  bits<8> src3;
405
406  let Inst{3-0} = en;
407  let Inst{9-4} = tgt;
408  let Inst{11} = done;
409  let Inst{31-26} = 0x3e;
410  let Inst{39-32} = src0;
411  let Inst{47-40} = src1;
412  let Inst{55-48} = src2;
413  let Inst{63-56} = src3;
414}
415
416// Pre-GFX11 encoding has compr and vm bits.
417class EXPe_ComprVM : EXPe {
418  bits<1> compr;
419  bits<1> vm;
420
421  let Inst{10} = compr;
422  let Inst{12} = vm;
423}
424
425// GFX11+ encoding has row bit.
426class EXPe_Row : EXPe {
427  bits<1> row;
428
429  let Inst{13} = row;
430}
431
432let Uses = [EXEC] in {
433
434class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
435    InstSI <outs, ins, asm, pattern> {
436  let VINTRP = 1;
437  // VINTRP instructions read parameter values from LDS, but these parameter
438  // values are stored outside of the LDS memory that is allocated to the
439  // shader for general purpose use.
440  //
441  // While it may be possible for ds_read/ds_write instructions to access
442  // the parameter values in LDS, this would essentially be an out-of-bounds
443  // memory access which we consider to be undefined behavior.
444  //
445  // So even though these instructions read memory, this memory is outside the
446  // addressable memory space for the shader, and we consider these instructions
447  // to be readnone.
448  let mayLoad = 0;
449  let mayStore = 0;
450  let hasSideEffects = 0;
451  let VALU = 1;
452}
453
454} // End Uses = [EXEC]
455