1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// SI Instruction format definitions.
11//
12//===----------------------------------------------------------------------===//
13
14class InstSI <dag outs, dag ins, string asm = "",
15              list<dag> pattern = []> :
16  AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
17
18  // Low bits - basic encoding information.
19  field bit SALU = 0;
20  field bit VALU = 0;
21
22  // SALU instruction formats.
23  field bit SOP1 = 0;
24  field bit SOP2 = 0;
25  field bit SOPC = 0;
26  field bit SOPK = 0;
27  field bit SOPP = 0;
28
29  // VALU instruction formats.
30  field bit VOP1 = 0;
31  field bit VOP2 = 0;
32  field bit VOPC = 0;
33  field bit VOP3 = 0;
34  field bit VINTRP = 0;
35  field bit SDWA = 0;
36  field bit DPP = 0;
37
38  // Memory instruction formats.
39  field bit MUBUF = 0;
40  field bit MTBUF = 0;
41  field bit SMRD = 0;
42  field bit MIMG = 0;
43  field bit EXP = 0;
44  field bit FLAT = 0;
45  field bit DS = 0;
46
47   // Pseudo instruction formats.
48  field bit VGPRSpill = 0;
49  field bit SGPRSpill = 0;
50
51  // High bits - other information.
52  field bit VM_CNT = 0;
53  field bit EXP_CNT = 0;
54  field bit LGKM_CNT = 0;
55
56  // Whether WQM _must_ be enabled for this instruction.
57  field bit WQM = 0;
58
59  // Whether WQM _must_ be disabled for this instruction.
60  field bit DisableWQM = 0;
61
62  field bit Gather4 = 0;
63
64  // Most sopk treat the immediate as a signed 16-bit, however some
65  // use it as unsigned.
66  field bit SOPKZext = 0;
67
68  // This is an s_store_dword* instruction that requires a cache flush
69  // on wave termination. It is necessary to distinguish from mayStore
70  // SMEM instructions like the cache flush ones.
71  field bit ScalarStore = 0;
72
73  // Whether the operands can be ignored when computing the
74  // instruction size.
75  field bit FixedSize = 0;
76
77  // This bit tells the assembler to use the 32-bit encoding in case it
78  // is unable to infer the encoding from the operands.
79  field bit VOPAsmPrefer32Bit = 0;
80
81  // This bit indicates that this has a floating point result type, so
82  // the clamp modifier has floating point semantics.
83  field bit FPClamp = 0;
84
85  // These need to be kept in sync with the enum in SIInstrFlags.
86  let TSFlags{0} = SALU;
87  let TSFlags{1} = VALU;
88
89  let TSFlags{2} = SOP1;
90  let TSFlags{3} = SOP2;
91  let TSFlags{4} = SOPC;
92  let TSFlags{5} = SOPK;
93  let TSFlags{6} = SOPP;
94
95  let TSFlags{7} = VOP1;
96  let TSFlags{8} = VOP2;
97  let TSFlags{9} = VOPC;
98  let TSFlags{10} = VOP3;
99
100  let TSFlags{13} = VINTRP;
101  let TSFlags{14} = SDWA;
102  let TSFlags{15} = DPP;
103
104  let TSFlags{16} = MUBUF;
105  let TSFlags{17} = MTBUF;
106  let TSFlags{18} = SMRD;
107  let TSFlags{19} = MIMG;
108  let TSFlags{20} = EXP;
109  let TSFlags{21} = FLAT;
110  let TSFlags{22} = DS;
111
112  let TSFlags{23} = VGPRSpill;
113  let TSFlags{24} = SGPRSpill;
114
115  let TSFlags{32} = VM_CNT;
116  let TSFlags{33} = EXP_CNT;
117  let TSFlags{34} = LGKM_CNT;
118
119  let TSFlags{35} = WQM;
120  let TSFlags{36} = DisableWQM;
121  let TSFlags{37} = Gather4;
122
123  let TSFlags{38} = SOPKZext;
124  let TSFlags{39} = ScalarStore;
125  let TSFlags{40} = FixedSize;
126  let TSFlags{41} = VOPAsmPrefer32Bit;
127  let TSFlags{42} = FPClamp;
128
129  let SchedRW = [Write32Bit];
130
131  field bits<1> DisableSIDecoder = 0;
132  field bits<1> DisableVIDecoder = 0;
133  field bits<1> DisableDecoder = 0;
134
135  let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);
136  let AsmVariantName = AMDGPUAsmVariants.Default;
137}
138
139class PseudoInstSI<dag outs, dag ins, list<dag> pattern = []>
140  : InstSI<outs, ins, "", pattern> {
141  let isPseudo = 1;
142  let isCodeGenOnly = 1;
143}
144
145class SPseudoInstSI<dag outs, dag ins, list<dag> pattern = []>
146  : PseudoInstSI<outs, ins, pattern> {
147  let SALU = 1;
148}
149
150class VPseudoInstSI<dag outs, dag ins, list<dag> pattern = []>
151  : PseudoInstSI<outs, ins, pattern> {
152  let VALU = 1;
153  let Uses = [EXEC];
154}
155
156class CFPseudoInstSI<dag outs, dag ins, list<dag> pattern = [],
157  bit UseExec = 0, bit DefExec = 0> :
158  SPseudoInstSI<outs, ins, pattern> {
159
160  let Uses = !if(UseExec, [EXEC], []);
161  let Defs = !if(DefExec, [EXEC, SCC], [SCC]);
162  let mayLoad = 0;
163  let mayStore = 0;
164  let hasSideEffects = 0;
165}
166
167class Enc32 {
168  field bits<32> Inst;
169  int Size = 4;
170}
171
172class Enc64 {
173  field bits<64> Inst;
174  int Size = 8;
175}
176
177class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
178
179class VINTRPe <bits<2> op> : Enc32 {
180  bits<8> vdst;
181  bits<8> vsrc;
182  bits<2> attrchan;
183  bits<6> attr;
184
185  let Inst{7-0} = vsrc;
186  let Inst{9-8} = attrchan;
187  let Inst{15-10} = attr;
188  let Inst{17-16} = op;
189  let Inst{25-18} = vdst;
190  let Inst{31-26} = 0x32; // encoding
191}
192
193class MIMGe <bits<7> op> : Enc64 {
194  bits<8> vdata;
195  bits<4> dmask;
196  bits<1> unorm;
197  bits<1> glc;
198  bits<1> da;
199  bits<1> r128;
200  bits<1> tfe;
201  bits<1> lwe;
202  bits<1> slc;
203  bits<8> vaddr;
204  bits<7> srsrc;
205  bits<7> ssamp;
206
207  let Inst{11-8} = dmask;
208  let Inst{12} = unorm;
209  let Inst{13} = glc;
210  let Inst{14} = da;
211  let Inst{15} = r128;
212  let Inst{16} = tfe;
213  let Inst{17} = lwe;
214  let Inst{24-18} = op;
215  let Inst{25} = slc;
216  let Inst{31-26} = 0x3c;
217  let Inst{39-32} = vaddr;
218  let Inst{47-40} = vdata;
219  let Inst{52-48} = srsrc{6-2};
220  let Inst{57-53} = ssamp{6-2};
221}
222
223class EXPe : Enc64 {
224  bits<4> en;
225  bits<6> tgt;
226  bits<1> compr;
227  bits<1> done;
228  bits<1> vm;
229  bits<8> vsrc0;
230  bits<8> vsrc1;
231  bits<8> vsrc2;
232  bits<8> vsrc3;
233
234  let Inst{3-0} = en;
235  let Inst{9-4} = tgt;
236  let Inst{10} = compr;
237  let Inst{11} = done;
238  let Inst{12} = vm;
239  let Inst{31-26} = 0x3e;
240  let Inst{39-32} = vsrc0;
241  let Inst{47-40} = vsrc1;
242  let Inst{55-48} = vsrc2;
243  let Inst{63-56} = vsrc3;
244}
245
246let Uses = [EXEC] in {
247
248class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
249    InstSI <outs, ins, asm, pattern> {
250  let VINTRP = 1;
251  // VINTRP instructions read parameter values from LDS, but these parameter
252  // values are stored outside of the LDS memory that is allocated to the
253  // shader for general purpose use.
254  //
255  // While it may be possible for ds_read/ds_write instructions to access
256  // the parameter values in LDS, this would essentially be an out-of-bounds
257  // memory access which we consider to be undefined behavior.
258  //
259  // So even though these instructions read memory, this memory is outside the
260  // addressable memory space for the shader, and we consider these instructions
261  // to be readnone.
262  let mayLoad = 0;
263  let mayStore = 0;
264  let hasSideEffects = 0;
265}
266
267class EXPCommon<dag outs, dag ins, string asm, list<dag> pattern> :
268  InstSI<outs, ins, asm, pattern> {
269  let EXP = 1;
270  let EXP_CNT = 1;
271  let mayLoad = 0; // Set to 1 if done bit is set.
272  let mayStore = 1;
273  let UseNamedOperandTable = 1;
274  let Uses = [EXEC];
275  let SchedRW = [WriteExport];
276}
277
278} // End Uses = [EXEC]
279
280class MIMG <dag outs, dag ins, string asm, list<dag> pattern> :
281    InstSI <outs, ins, asm, pattern> {
282
283  let VM_CNT = 1;
284  let EXP_CNT = 1;
285  let MIMG = 1;
286  let Uses = [EXEC];
287
288  let UseNamedOperandTable = 1;
289  let hasSideEffects = 0; // XXX ????
290}
291