1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// SI Instruction format definitions. 11// 12//===----------------------------------------------------------------------===// 13 14class InstSI <dag outs, dag ins, string asm = "", 15 list<dag> pattern = []> : 16 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl { 17 18 field bits<1> VM_CNT = 0; 19 field bits<1> EXP_CNT = 0; 20 field bits<1> LGKM_CNT = 0; 21 22 field bits<1> SALU = 0; 23 field bits<1> VALU = 0; 24 25 field bits<1> SOP1 = 0; 26 field bits<1> SOP2 = 0; 27 field bits<1> SOPC = 0; 28 field bits<1> SOPK = 0; 29 field bits<1> SOPP = 0; 30 31 field bits<1> VOP1 = 0; 32 field bits<1> VOP2 = 0; 33 field bits<1> VOP3 = 0; 34 field bits<1> VOPC = 0; 35 field bits<1> SDWA = 0; 36 field bits<1> DPP = 0; 37 38 field bits<1> MUBUF = 0; 39 field bits<1> MTBUF = 0; 40 field bits<1> SMRD = 0; 41 field bits<1> DS = 0; 42 field bits<1> MIMG = 0; 43 field bits<1> FLAT = 0; 44 45 // Whether WQM _must_ be enabled for this instruction. 46 field bits<1> WQM = 0; 47 field bits<1> VGPRSpill = 0; 48 49 // This bit tells the assembler to use the 32-bit encoding in case it 50 // is unable to infer the encoding from the operands. 51 field bits<1> VOPAsmPrefer32Bit = 0; 52 53 field bits<1> Gather4 = 0; 54 55 // Whether WQM _must_ be disabled for this instruction. 56 field bits<1> DisableWQM = 0; 57 58 // These need to be kept in sync with the enum in SIInstrFlags. 59 let TSFlags{0} = VM_CNT; 60 let TSFlags{1} = EXP_CNT; 61 let TSFlags{2} = LGKM_CNT; 62 63 let TSFlags{3} = SALU; 64 let TSFlags{4} = VALU; 65 66 let TSFlags{5} = SOP1; 67 let TSFlags{6} = SOP2; 68 let TSFlags{7} = SOPC; 69 let TSFlags{8} = SOPK; 70 let TSFlags{9} = SOPP; 71 72 let TSFlags{10} = VOP1; 73 let TSFlags{11} = VOP2; 74 let TSFlags{12} = VOP3; 75 let TSFlags{13} = VOPC; 76 let TSFlags{14} = SDWA; 77 let TSFlags{15} = DPP; 78 79 let TSFlags{16} = MUBUF; 80 let TSFlags{17} = MTBUF; 81 let TSFlags{18} = SMRD; 82 let TSFlags{19} = DS; 83 let TSFlags{20} = MIMG; 84 let TSFlags{21} = FLAT; 85 let TSFlags{22} = WQM; 86 let TSFlags{23} = VGPRSpill; 87 let TSFlags{24} = VOPAsmPrefer32Bit; 88 let TSFlags{25} = Gather4; 89 let TSFlags{26} = DisableWQM; 90 91 let SchedRW = [Write32Bit]; 92 93 field bits<1> DisableSIDecoder = 0; 94 field bits<1> DisableVIDecoder = 0; 95 field bits<1> DisableDecoder = 0; 96 97 let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1); 98 let AsmVariantName = AMDGPUAsmVariants.Default; 99} 100 101class PseudoInstSI<dag outs, dag ins, list<dag> pattern = []> 102 : InstSI<outs, ins, "", pattern> { 103 let isPseudo = 1; 104 let isCodeGenOnly = 1; 105} 106 107class SPseudoInstSI<dag outs, dag ins, list<dag> pattern = []> 108 : PseudoInstSI<outs, ins, pattern> { 109 let SALU = 1; 110} 111 112class VPseudoInstSI<dag outs, dag ins, list<dag> pattern = []> 113 : PseudoInstSI<outs, ins, pattern> { 114 let VALU = 1; 115 let Uses = [EXEC]; 116} 117 118class CFPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], 119 bit UseExec = 0, bit DefExec = 0> : 120 SPseudoInstSI<outs, ins, pattern> { 121 122 let Uses = !if(UseExec, [EXEC], []); 123 let Defs = !if(DefExec, [EXEC, SCC], [SCC]); 124} 125 126class Enc32 { 127 field bits<32> Inst; 128 int Size = 4; 129} 130 131class Enc64 { 132 field bits<64> Inst; 133 int Size = 8; 134} 135 136class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">; 137 138let Uses = [EXEC] in { 139 140class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> : 141 InstSI <outs, ins, asm, pattern> { 142 143 let mayLoad = 0; 144 let mayStore = 0; 145 let hasSideEffects = 0; 146 let UseNamedOperandTable = 1; 147 let VALU = 1; 148} 149 150class VOPCCommon <dag ins, string asm, list<dag> pattern> : 151 VOPAnyCommon <(outs), ins, asm, pattern> { 152 153 let VOPC = 1; 154 let Size = 4; 155 let Defs = [VCC]; 156} 157 158class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> : 159 VOPAnyCommon <outs, ins, asm, pattern> { 160 161 let VOP1 = 1; 162 let Size = 4; 163} 164 165class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> : 166 VOPAnyCommon <outs, ins, asm, pattern> { 167 168 let VOP2 = 1; 169 let Size = 4; 170} 171 172class VOP3Common <dag outs, dag ins, string asm = "", 173 list<dag> pattern = [], bit HasMods = 0, 174 bit VOP3Only = 0> : 175 VOPAnyCommon <outs, ins, asm, pattern> { 176 177 // Using complex patterns gives VOP3 patterns a very high complexity rating, 178 // but standalone patterns are almost always prefered, so we need to adjust the 179 // priority lower. The goal is to use a high number to reduce complexity to 180 // zero (or less than zero). 181 let AddedComplexity = -1000; 182 183 let VOP3 = 1; 184 let VALU = 1; 185 186 let AsmMatchConverter = 187 !if(!eq(VOP3Only,1), 188 "cvtVOP3", 189 !if(!eq(HasMods,1), "cvtVOP3_2_mod", "")); 190 191 let AsmVariantName = AMDGPUAsmVariants.VOP3; 192 193 let isCodeGenOnly = 0; 194 195 int Size = 8; 196 197 // Because SGPRs may be allowed if there are multiple operands, we 198 // need a post-isel hook to insert copies in order to avoid 199 // violating constant bus requirements. 200 let hasPostISelHook = 1; 201} 202 203} // End Uses = [EXEC] 204 205//===----------------------------------------------------------------------===// 206// Vector ALU operations 207//===----------------------------------------------------------------------===// 208 209class VOP1e <bits<8> op> : Enc32 { 210 bits<8> vdst; 211 bits<9> src0; 212 213 let Inst{8-0} = src0; 214 let Inst{16-9} = op; 215 let Inst{24-17} = vdst; 216 let Inst{31-25} = 0x3f; //encoding 217} 218 219class VOP2e <bits<6> op> : Enc32 { 220 bits<8> vdst; 221 bits<9> src0; 222 bits<8> src1; 223 224 let Inst{8-0} = src0; 225 let Inst{16-9} = src1; 226 let Inst{24-17} = vdst; 227 let Inst{30-25} = op; 228 let Inst{31} = 0x0; //encoding 229} 230 231class VOP2_MADKe <bits<6> op> : Enc64 { 232 233 bits<8> vdst; 234 bits<9> src0; 235 bits<8> src1; 236 bits<32> imm; 237 238 let Inst{8-0} = src0; 239 let Inst{16-9} = src1; 240 let Inst{24-17} = vdst; 241 let Inst{30-25} = op; 242 let Inst{31} = 0x0; // encoding 243 let Inst{63-32} = imm; 244} 245 246class VOP3a <bits<9> op> : Enc64 { 247 bits<2> src0_modifiers; 248 bits<9> src0; 249 bits<2> src1_modifiers; 250 bits<9> src1; 251 bits<2> src2_modifiers; 252 bits<9> src2; 253 bits<1> clamp; 254 bits<2> omod; 255 256 let Inst{8} = src0_modifiers{1}; 257 let Inst{9} = src1_modifiers{1}; 258 let Inst{10} = src2_modifiers{1}; 259 let Inst{11} = clamp; 260 let Inst{25-17} = op; 261 let Inst{31-26} = 0x34; //encoding 262 let Inst{40-32} = src0; 263 let Inst{49-41} = src1; 264 let Inst{58-50} = src2; 265 let Inst{60-59} = omod; 266 let Inst{61} = src0_modifiers{0}; 267 let Inst{62} = src1_modifiers{0}; 268 let Inst{63} = src2_modifiers{0}; 269} 270 271class VOP3e <bits<9> op> : VOP3a <op> { 272 bits<8> vdst; 273 274 let Inst{7-0} = vdst; 275} 276 277// Encoding used for VOPC instructions encoded as VOP3 278// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst 279class VOP3ce <bits<9> op> : VOP3a <op> { 280 bits<8> sdst; 281 282 let Inst{7-0} = sdst; 283} 284 285class VOP3be <bits<9> op> : Enc64 { 286 bits<8> vdst; 287 bits<2> src0_modifiers; 288 bits<9> src0; 289 bits<2> src1_modifiers; 290 bits<9> src1; 291 bits<2> src2_modifiers; 292 bits<9> src2; 293 bits<7> sdst; 294 bits<2> omod; 295 296 let Inst{7-0} = vdst; 297 let Inst{14-8} = sdst; 298 let Inst{25-17} = op; 299 let Inst{31-26} = 0x34; //encoding 300 let Inst{40-32} = src0; 301 let Inst{49-41} = src1; 302 let Inst{58-50} = src2; 303 let Inst{60-59} = omod; 304 let Inst{61} = src0_modifiers{0}; 305 let Inst{62} = src1_modifiers{0}; 306 let Inst{63} = src2_modifiers{0}; 307} 308 309class VOPCe <bits<8> op> : Enc32 { 310 bits<9> src0; 311 bits<8> src1; 312 313 let Inst{8-0} = src0; 314 let Inst{16-9} = src1; 315 let Inst{24-17} = op; 316 let Inst{31-25} = 0x3e; 317} 318 319class VINTRPe <bits<2> op> : Enc32 { 320 bits<8> vdst; 321 bits<8> vsrc; 322 bits<2> attrchan; 323 bits<6> attr; 324 325 let Inst{7-0} = vsrc; 326 let Inst{9-8} = attrchan; 327 let Inst{15-10} = attr; 328 let Inst{17-16} = op; 329 let Inst{25-18} = vdst; 330 let Inst{31-26} = 0x32; // encoding 331} 332 333class MUBUFe <bits<7> op> : Enc64 { 334 bits<12> offset; 335 bits<1> offen; 336 bits<1> idxen; 337 bits<1> glc; 338 bits<1> addr64; 339 bits<1> lds; 340 bits<8> vaddr; 341 bits<8> vdata; 342 bits<7> srsrc; 343 bits<1> slc; 344 bits<1> tfe; 345 bits<8> soffset; 346 347 let Inst{11-0} = offset; 348 let Inst{12} = offen; 349 let Inst{13} = idxen; 350 let Inst{14} = glc; 351 let Inst{15} = addr64; 352 let Inst{16} = lds; 353 let Inst{24-18} = op; 354 let Inst{31-26} = 0x38; //encoding 355 let Inst{39-32} = vaddr; 356 let Inst{47-40} = vdata; 357 let Inst{52-48} = srsrc{6-2}; 358 let Inst{54} = slc; 359 let Inst{55} = tfe; 360 let Inst{63-56} = soffset; 361} 362 363class MTBUFe <bits<3> op> : Enc64 { 364 bits<8> vdata; 365 bits<12> offset; 366 bits<1> offen; 367 bits<1> idxen; 368 bits<1> glc; 369 bits<1> addr64; 370 bits<4> dfmt; 371 bits<3> nfmt; 372 bits<8> vaddr; 373 bits<7> srsrc; 374 bits<1> slc; 375 bits<1> tfe; 376 bits<8> soffset; 377 378 let Inst{11-0} = offset; 379 let Inst{12} = offen; 380 let Inst{13} = idxen; 381 let Inst{14} = glc; 382 let Inst{15} = addr64; 383 let Inst{18-16} = op; 384 let Inst{22-19} = dfmt; 385 let Inst{25-23} = nfmt; 386 let Inst{31-26} = 0x3a; //encoding 387 let Inst{39-32} = vaddr; 388 let Inst{47-40} = vdata; 389 let Inst{52-48} = srsrc{6-2}; 390 let Inst{54} = slc; 391 let Inst{55} = tfe; 392 let Inst{63-56} = soffset; 393} 394 395class MIMGe <bits<7> op> : Enc64 { 396 bits<8> vdata; 397 bits<4> dmask; 398 bits<1> unorm; 399 bits<1> glc; 400 bits<1> da; 401 bits<1> r128; 402 bits<1> tfe; 403 bits<1> lwe; 404 bits<1> slc; 405 bits<8> vaddr; 406 bits<7> srsrc; 407 bits<7> ssamp; 408 409 let Inst{11-8} = dmask; 410 let Inst{12} = unorm; 411 let Inst{13} = glc; 412 let Inst{14} = da; 413 let Inst{15} = r128; 414 let Inst{16} = tfe; 415 let Inst{17} = lwe; 416 let Inst{24-18} = op; 417 let Inst{25} = slc; 418 let Inst{31-26} = 0x3c; 419 let Inst{39-32} = vaddr; 420 let Inst{47-40} = vdata; 421 let Inst{52-48} = srsrc{6-2}; 422 let Inst{57-53} = ssamp{6-2}; 423} 424 425class EXPe : Enc64 { 426 bits<4> en; 427 bits<6> tgt; 428 bits<1> compr; 429 bits<1> done; 430 bits<1> vm; 431 bits<8> vsrc0; 432 bits<8> vsrc1; 433 bits<8> vsrc2; 434 bits<8> vsrc3; 435 436 let Inst{3-0} = en; 437 let Inst{9-4} = tgt; 438 let Inst{10} = compr; 439 let Inst{11} = done; 440 let Inst{12} = vm; 441 let Inst{31-26} = 0x3e; 442 let Inst{39-32} = vsrc0; 443 let Inst{47-40} = vsrc1; 444 let Inst{55-48} = vsrc2; 445 let Inst{63-56} = vsrc3; 446} 447 448let Uses = [EXEC] in { 449 450class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> : 451 VOP1Common <outs, ins, asm, pattern>, 452 VOP1e<op> { 453 let isCodeGenOnly = 0; 454} 455 456class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> : 457 VOP2Common <outs, ins, asm, pattern>, VOP2e<op> { 458 let isCodeGenOnly = 0; 459} 460 461class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> : 462 VOPCCommon <ins, asm, pattern>, VOPCe <op>; 463 464class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> : 465 InstSI <outs, ins, asm, pattern> { 466 let mayLoad = 1; 467 let mayStore = 0; 468 let hasSideEffects = 0; 469} 470 471} // End Uses = [EXEC] 472 473//===----------------------------------------------------------------------===// 474// Vector I/O operations 475//===----------------------------------------------------------------------===// 476 477class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> : 478 InstSI<outs, ins, asm, pattern> { 479 480 let VM_CNT = 1; 481 let EXP_CNT = 1; 482 let MUBUF = 1; 483 let Uses = [EXEC]; 484 485 let hasSideEffects = 0; 486 let UseNamedOperandTable = 1; 487 let AsmMatchConverter = "cvtMubuf"; 488 let SchedRW = [WriteVMEM]; 489} 490 491class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> : 492 InstSI<outs, ins, asm, pattern> { 493 494 let VM_CNT = 1; 495 let EXP_CNT = 1; 496 let MTBUF = 1; 497 let Uses = [EXEC]; 498 499 let hasSideEffects = 0; 500 let UseNamedOperandTable = 1; 501 let SchedRW = [WriteVMEM]; 502} 503 504class MIMG <dag outs, dag ins, string asm, list<dag> pattern> : 505 InstSI <outs, ins, asm, pattern> { 506 507 let VM_CNT = 1; 508 let EXP_CNT = 1; 509 let MIMG = 1; 510 let Uses = [EXEC]; 511 512 let UseNamedOperandTable = 1; 513 let hasSideEffects = 0; // XXX ???? 514} 515