1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// SI Instruction format definitions.
11//
12//===----------------------------------------------------------------------===//
13
14def isGCN : Predicate<"Subtarget->getGeneration() "
15                      ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">,
16            AssemblerPredicate<"FeatureGCN">;
17def isSI : Predicate<"Subtarget->getGeneration() "
18                      "== AMDGPUSubtarget::SOUTHERN_ISLANDS">,
19           AssemblerPredicate<"FeatureSouthernIslands">;
20
21
22class InstSI <dag outs, dag ins, string asm = "",
23              list<dag> pattern = []> :
24  AMDGPUInst<outs, ins, asm, pattern>, GCNPredicateControl {
25  let SubtargetPredicate = isGCN;
26
27  // Low bits - basic encoding information.
28  field bit SALU = 0;
29  field bit VALU = 0;
30
31  // SALU instruction formats.
32  field bit SOP1 = 0;
33  field bit SOP2 = 0;
34  field bit SOPC = 0;
35  field bit SOPK = 0;
36  field bit SOPP = 0;
37
38  // VALU instruction formats.
39  field bit VOP1 = 0;
40  field bit VOP2 = 0;
41  field bit VOPC = 0;
42  field bit VOP3 = 0;
43  field bit VOP3P = 0;
44  field bit VINTRP = 0;
45  field bit SDWA = 0;
46  field bit DPP = 0;
47
48  // Memory instruction formats.
49  field bit MUBUF = 0;
50  field bit MTBUF = 0;
51  field bit SMRD = 0;
52  field bit MIMG = 0;
53  field bit EXP = 0;
54  field bit FLAT = 0;
55  field bit DS = 0;
56
57  // Pseudo instruction formats.
58  field bit VGPRSpill = 0;
59  field bit SGPRSpill = 0;
60
61  // High bits - other information.
62  field bit VM_CNT = 0;
63  field bit EXP_CNT = 0;
64  field bit LGKM_CNT = 0;
65
66  // Whether WQM _must_ be enabled for this instruction.
67  field bit WQM = 0;
68
69  // Whether WQM _must_ be disabled for this instruction.
70  field bit DisableWQM = 0;
71
72  field bit Gather4 = 0;
73
74  // Most sopk treat the immediate as a signed 16-bit, however some
75  // use it as unsigned.
76  field bit SOPKZext = 0;
77
78  // This is an s_store_dword* instruction that requires a cache flush
79  // on wave termination. It is necessary to distinguish from mayStore
80  // SMEM instructions like the cache flush ones.
81  field bit ScalarStore = 0;
82
83  // Whether the operands can be ignored when computing the
84  // instruction size.
85  field bit FixedSize = 0;
86
87  // This bit tells the assembler to use the 32-bit encoding in case it
88  // is unable to infer the encoding from the operands.
89  field bit VOPAsmPrefer32Bit = 0;
90
91  // This bit indicates that this is a VOP3 opcode which supports op_sel
92  // modifier (gfx9 only).
93  field bit VOP3_OPSEL = 0;
94
95  // Is it possible for this instruction to be atomic?
96  field bit maybeAtomic = 0;
97
98  // This bit indicates that this is a VI instruction which is renamed
99  // in GFX9. Required for correct mapping from pseudo to MC.
100  field bit renamedInGFX9 = 0;
101
102  // This bit indicates that this has a floating point result type, so
103  // the clamp modifier has floating point semantics.
104  field bit FPClamp = 0;
105
106  // This bit indicates that instruction may support integer clamping
107  // which depends on GPU features.
108  field bit IntClamp = 0;
109
110  // This field indicates that the clamp applies to the low component
111  // of a packed output register.
112  field bit ClampLo = 0;
113
114  // This field indicates that the clamp applies to the high component
115  // of a packed output register.
116  field bit ClampHi = 0;
117
118  // This bit indicates that this is a packed VOP3P instruction
119  field bit IsPacked = 0;
120
121  // This bit indicates that this is a D16 buffer instruction.
122  field bit D16Buf = 0;
123
124  // These need to be kept in sync with the enum in SIInstrFlags.
125  let TSFlags{0} = SALU;
126  let TSFlags{1} = VALU;
127
128  let TSFlags{2} = SOP1;
129  let TSFlags{3} = SOP2;
130  let TSFlags{4} = SOPC;
131  let TSFlags{5} = SOPK;
132  let TSFlags{6} = SOPP;
133
134  let TSFlags{7} = VOP1;
135  let TSFlags{8} = VOP2;
136  let TSFlags{9} = VOPC;
137  let TSFlags{10} = VOP3;
138  let TSFlags{12} = VOP3P;
139
140  let TSFlags{13} = VINTRP;
141  let TSFlags{14} = SDWA;
142  let TSFlags{15} = DPP;
143
144  let TSFlags{16} = MUBUF;
145  let TSFlags{17} = MTBUF;
146  let TSFlags{18} = SMRD;
147  let TSFlags{19} = MIMG;
148  let TSFlags{20} = EXP;
149  let TSFlags{21} = FLAT;
150  let TSFlags{22} = DS;
151
152  let TSFlags{23} = VGPRSpill;
153  let TSFlags{24} = SGPRSpill;
154
155  let TSFlags{32} = VM_CNT;
156  let TSFlags{33} = EXP_CNT;
157  let TSFlags{34} = LGKM_CNT;
158
159  let TSFlags{35} = WQM;
160  let TSFlags{36} = DisableWQM;
161  let TSFlags{37} = Gather4;
162
163  let TSFlags{38} = SOPKZext;
164  let TSFlags{39} = ScalarStore;
165  let TSFlags{40} = FixedSize;
166  let TSFlags{41} = VOPAsmPrefer32Bit;
167  let TSFlags{42} = VOP3_OPSEL;
168
169  let TSFlags{43} = maybeAtomic;
170  let TSFlags{44} = renamedInGFX9;
171
172  let TSFlags{45} = FPClamp;
173  let TSFlags{46} = IntClamp;
174  let TSFlags{47} = ClampLo;
175  let TSFlags{48} = ClampHi;
176
177  let TSFlags{49} = IsPacked;
178
179  let TSFlags{50} = D16Buf;
180
181  let SchedRW = [Write32Bit];
182
183  field bits<1> DisableSIDecoder = 0;
184  field bits<1> DisableVIDecoder = 0;
185  field bits<1> DisableDecoder = 0;
186
187  let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);
188  let AsmVariantName = AMDGPUAsmVariants.Default;
189
190  // Avoid changing source registers in a way that violates constant bus read limitations.
191  let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0))))));
192}
193
194class PseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
195  : InstSI<outs, ins, asm, pattern> {
196  let isPseudo = 1;
197  let isCodeGenOnly = 1;
198}
199
200class SPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
201  : PseudoInstSI<outs, ins, pattern, asm> {
202  let SALU = 1;
203}
204
205class VPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
206  : PseudoInstSI<outs, ins, pattern, asm> {
207  let VALU = 1;
208  let Uses = [EXEC];
209}
210
211class CFPseudoInstSI<dag outs, dag ins, list<dag> pattern = [],
212  bit UseExec = 0, bit DefExec = 0> :
213  SPseudoInstSI<outs, ins, pattern> {
214
215  let Uses = !if(UseExec, [EXEC], []);
216  let Defs = !if(DefExec, [EXEC, SCC], [SCC]);
217  let mayLoad = 0;
218  let mayStore = 0;
219  let hasSideEffects = 0;
220}
221
222class Enc32 {
223  field bits<32> Inst;
224  int Size = 4;
225}
226
227class Enc64 {
228  field bits<64> Inst;
229  int Size = 8;
230}
231
232class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
233
234class VINTRPe <bits<2> op> : Enc32 {
235  bits<8> vdst;
236  bits<8> vsrc;
237  bits<2> attrchan;
238  bits<6> attr;
239
240  let Inst{7-0} = vsrc;
241  let Inst{9-8} = attrchan;
242  let Inst{15-10} = attr;
243  let Inst{17-16} = op;
244  let Inst{25-18} = vdst;
245  let Inst{31-26} = 0x32; // encoding
246}
247
248class MIMGe <bits<7> op> : Enc64 {
249  bits<8> vdata;
250  bits<4> dmask;
251  bits<1> unorm;
252  bits<1> glc;
253  bits<1> da;
254  bits<1> r128;
255  bits<1> tfe;
256  bits<1> lwe;
257  bits<1> slc;
258  bit d16;
259  bits<8> vaddr;
260  bits<7> srsrc;
261  bits<7> ssamp;
262
263  let Inst{11-8} = dmask;
264  let Inst{12} = unorm;
265  let Inst{13} = glc;
266  let Inst{14} = da;
267  let Inst{15} = r128;
268  let Inst{16} = tfe;
269  let Inst{17} = lwe;
270  let Inst{24-18} = op;
271  let Inst{25} = slc;
272  let Inst{31-26} = 0x3c;
273  let Inst{39-32} = vaddr;
274  let Inst{47-40} = vdata;
275  let Inst{52-48} = srsrc{6-2};
276  let Inst{57-53} = ssamp{6-2};
277  let Inst{63} = d16;
278}
279
280class EXPe : Enc64 {
281  bits<4> en;
282  bits<6> tgt;
283  bits<1> compr;
284  bits<1> done;
285  bits<1> vm;
286  bits<8> src0;
287  bits<8> src1;
288  bits<8> src2;
289  bits<8> src3;
290
291  let Inst{3-0} = en;
292  let Inst{9-4} = tgt;
293  let Inst{10} = compr;
294  let Inst{11} = done;
295  let Inst{12} = vm;
296  let Inst{31-26} = 0x3e;
297  let Inst{39-32} = src0;
298  let Inst{47-40} = src1;
299  let Inst{55-48} = src2;
300  let Inst{63-56} = src3;
301}
302
303let Uses = [EXEC] in {
304
305class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
306    InstSI <outs, ins, asm, pattern> {
307  let VINTRP = 1;
308  // VINTRP instructions read parameter values from LDS, but these parameter
309  // values are stored outside of the LDS memory that is allocated to the
310  // shader for general purpose use.
311  //
312  // While it may be possible for ds_read/ds_write instructions to access
313  // the parameter values in LDS, this would essentially be an out-of-bounds
314  // memory access which we consider to be undefined behavior.
315  //
316  // So even though these instructions read memory, this memory is outside the
317  // addressable memory space for the shader, and we consider these instructions
318  // to be readnone.
319  let mayLoad = 0;
320  let mayStore = 0;
321  let hasSideEffects = 0;
322  let VALU = 1;
323}
324
325class EXPCommon<dag outs, dag ins, string asm, list<dag> pattern> :
326  InstSI<outs, ins, asm, pattern> {
327  let EXP = 1;
328  let EXP_CNT = 1;
329  let mayLoad = 0; // Set to 1 if done bit is set.
330  let mayStore = 1;
331  let UseNamedOperandTable = 1;
332  let Uses = [EXEC];
333  let SchedRW = [WriteExport];
334}
335
336} // End Uses = [EXEC]
337