1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// SI Instruction format definitions.
11//
12//===----------------------------------------------------------------------===//
13
14class InstSI <dag outs, dag ins, string asm = "",
15              list<dag> pattern = []> :
16  AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
17
18  // Low bits - basic encoding information.
19  field bit SALU = 0;
20  field bit VALU = 0;
21
22  // SALU instruction formats.
23  field bit SOP1 = 0;
24  field bit SOP2 = 0;
25  field bit SOPC = 0;
26  field bit SOPK = 0;
27  field bit SOPP = 0;
28
29  // VALU instruction formats.
30  field bit VOP1 = 0;
31  field bit VOP2 = 0;
32  field bit VOPC = 0;
33  field bit VOP3 = 0;
34  field bit VOP3P = 0;
35  field bit VINTRP = 0;
36  field bit SDWA = 0;
37  field bit DPP = 0;
38
39  // Memory instruction formats.
40  field bit MUBUF = 0;
41  field bit MTBUF = 0;
42  field bit SMRD = 0;
43  field bit MIMG = 0;
44  field bit EXP = 0;
45  field bit FLAT = 0;
46  field bit DS = 0;
47
48   // Pseudo instruction formats.
49  field bit VGPRSpill = 0;
50  field bit SGPRSpill = 0;
51
52  // High bits - other information.
53  field bit VM_CNT = 0;
54  field bit EXP_CNT = 0;
55  field bit LGKM_CNT = 0;
56
57  // Whether WQM _must_ be enabled for this instruction.
58  field bit WQM = 0;
59
60  // Whether WQM _must_ be disabled for this instruction.
61  field bit DisableWQM = 0;
62
63  field bit Gather4 = 0;
64
65  // Most sopk treat the immediate as a signed 16-bit, however some
66  // use it as unsigned.
67  field bit SOPKZext = 0;
68
69  // This is an s_store_dword* instruction that requires a cache flush
70  // on wave termination. It is necessary to distinguish from mayStore
71  // SMEM instructions like the cache flush ones.
72  field bit ScalarStore = 0;
73
74  // Whether the operands can be ignored when computing the
75  // instruction size.
76  field bit FixedSize = 0;
77
78  // This bit tells the assembler to use the 32-bit encoding in case it
79  // is unable to infer the encoding from the operands.
80  field bit VOPAsmPrefer32Bit = 0;
81
82  // This bit indicates that this has a floating point result type, so
83  // the clamp modifier has floating point semantics.
84  field bit FPClamp = 0;
85
86  // These need to be kept in sync with the enum in SIInstrFlags.
87  let TSFlags{0} = SALU;
88  let TSFlags{1} = VALU;
89
90  let TSFlags{2} = SOP1;
91  let TSFlags{3} = SOP2;
92  let TSFlags{4} = SOPC;
93  let TSFlags{5} = SOPK;
94  let TSFlags{6} = SOPP;
95
96  let TSFlags{7} = VOP1;
97  let TSFlags{8} = VOP2;
98  let TSFlags{9} = VOPC;
99  let TSFlags{10} = VOP3;
100  let TSFlags{12} = VOP3P;
101
102  let TSFlags{13} = VINTRP;
103  let TSFlags{14} = SDWA;
104  let TSFlags{15} = DPP;
105
106  let TSFlags{16} = MUBUF;
107  let TSFlags{17} = MTBUF;
108  let TSFlags{18} = SMRD;
109  let TSFlags{19} = MIMG;
110  let TSFlags{20} = EXP;
111  let TSFlags{21} = FLAT;
112  let TSFlags{22} = DS;
113
114  let TSFlags{23} = VGPRSpill;
115  let TSFlags{24} = SGPRSpill;
116
117  let TSFlags{32} = VM_CNT;
118  let TSFlags{33} = EXP_CNT;
119  let TSFlags{34} = LGKM_CNT;
120
121  let TSFlags{35} = WQM;
122  let TSFlags{36} = DisableWQM;
123  let TSFlags{37} = Gather4;
124
125  let TSFlags{38} = SOPKZext;
126  let TSFlags{39} = ScalarStore;
127  let TSFlags{40} = FixedSize;
128  let TSFlags{41} = VOPAsmPrefer32Bit;
129  let TSFlags{42} = FPClamp;
130
131  let SchedRW = [Write32Bit];
132
133  field bits<1> DisableSIDecoder = 0;
134  field bits<1> DisableVIDecoder = 0;
135  field bits<1> DisableDecoder = 0;
136
137  let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);
138  let AsmVariantName = AMDGPUAsmVariants.Default;
139}
140
141class PseudoInstSI<dag outs, dag ins, list<dag> pattern = []>
142  : InstSI<outs, ins, "", pattern> {
143  let isPseudo = 1;
144  let isCodeGenOnly = 1;
145}
146
147class SPseudoInstSI<dag outs, dag ins, list<dag> pattern = []>
148  : PseudoInstSI<outs, ins, pattern> {
149  let SALU = 1;
150}
151
152class VPseudoInstSI<dag outs, dag ins, list<dag> pattern = []>
153  : PseudoInstSI<outs, ins, pattern> {
154  let VALU = 1;
155  let Uses = [EXEC];
156}
157
158class CFPseudoInstSI<dag outs, dag ins, list<dag> pattern = [],
159  bit UseExec = 0, bit DefExec = 0> :
160  SPseudoInstSI<outs, ins, pattern> {
161
162  let Uses = !if(UseExec, [EXEC], []);
163  let Defs = !if(DefExec, [EXEC, SCC], [SCC]);
164  let mayLoad = 0;
165  let mayStore = 0;
166  let hasSideEffects = 0;
167}
168
169class Enc32 {
170  field bits<32> Inst;
171  int Size = 4;
172}
173
174class Enc64 {
175  field bits<64> Inst;
176  int Size = 8;
177}
178
179class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
180
181class VINTRPe <bits<2> op> : Enc32 {
182  bits<8> vdst;
183  bits<8> vsrc;
184  bits<2> attrchan;
185  bits<6> attr;
186
187  let Inst{7-0} = vsrc;
188  let Inst{9-8} = attrchan;
189  let Inst{15-10} = attr;
190  let Inst{17-16} = op;
191  let Inst{25-18} = vdst;
192  let Inst{31-26} = 0x32; // encoding
193}
194
195class MIMGe <bits<7> op> : Enc64 {
196  bits<8> vdata;
197  bits<4> dmask;
198  bits<1> unorm;
199  bits<1> glc;
200  bits<1> da;
201  bits<1> r128;
202  bits<1> tfe;
203  bits<1> lwe;
204  bits<1> slc;
205  bits<8> vaddr;
206  bits<7> srsrc;
207  bits<7> ssamp;
208
209  let Inst{11-8} = dmask;
210  let Inst{12} = unorm;
211  let Inst{13} = glc;
212  let Inst{14} = da;
213  let Inst{15} = r128;
214  let Inst{16} = tfe;
215  let Inst{17} = lwe;
216  let Inst{24-18} = op;
217  let Inst{25} = slc;
218  let Inst{31-26} = 0x3c;
219  let Inst{39-32} = vaddr;
220  let Inst{47-40} = vdata;
221  let Inst{52-48} = srsrc{6-2};
222  let Inst{57-53} = ssamp{6-2};
223}
224
225class EXPe : Enc64 {
226  bits<4> en;
227  bits<6> tgt;
228  bits<1> compr;
229  bits<1> done;
230  bits<1> vm;
231  bits<8> vsrc0;
232  bits<8> vsrc1;
233  bits<8> vsrc2;
234  bits<8> vsrc3;
235
236  let Inst{3-0} = en;
237  let Inst{9-4} = tgt;
238  let Inst{10} = compr;
239  let Inst{11} = done;
240  let Inst{12} = vm;
241  let Inst{31-26} = 0x3e;
242  let Inst{39-32} = vsrc0;
243  let Inst{47-40} = vsrc1;
244  let Inst{55-48} = vsrc2;
245  let Inst{63-56} = vsrc3;
246}
247
248let Uses = [EXEC] in {
249
250class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
251    InstSI <outs, ins, asm, pattern> {
252  let VINTRP = 1;
253  // VINTRP instructions read parameter values from LDS, but these parameter
254  // values are stored outside of the LDS memory that is allocated to the
255  // shader for general purpose use.
256  //
257  // While it may be possible for ds_read/ds_write instructions to access
258  // the parameter values in LDS, this would essentially be an out-of-bounds
259  // memory access which we consider to be undefined behavior.
260  //
261  // So even though these instructions read memory, this memory is outside the
262  // addressable memory space for the shader, and we consider these instructions
263  // to be readnone.
264  let mayLoad = 0;
265  let mayStore = 0;
266  let hasSideEffects = 0;
267}
268
269class EXPCommon<dag outs, dag ins, string asm, list<dag> pattern> :
270  InstSI<outs, ins, asm, pattern> {
271  let EXP = 1;
272  let EXP_CNT = 1;
273  let mayLoad = 0; // Set to 1 if done bit is set.
274  let mayStore = 1;
275  let UseNamedOperandTable = 1;
276  let Uses = [EXEC];
277  let SchedRW = [WriteExport];
278}
279
280} // End Uses = [EXEC]
281
282class MIMG <dag outs, dag ins, string asm, list<dag> pattern> :
283    InstSI <outs, ins, asm, pattern> {
284
285  let VM_CNT = 1;
286  let EXP_CNT = 1;
287  let MIMG = 1;
288  let Uses = [EXEC];
289
290  let UseNamedOperandTable = 1;
291  let hasSideEffects = 0; // XXX ????
292}
293