1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// SI Instruction format definitions.
11//
12//===----------------------------------------------------------------------===//
13
14class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15    AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
16
17  field bits<1> VM_CNT = 0;
18  field bits<1> EXP_CNT = 0;
19  field bits<1> LGKM_CNT = 0;
20
21  field bits<1> SALU = 0;
22  field bits<1> VALU = 0;
23
24  field bits<1> SOP1 = 0;
25  field bits<1> SOP2 = 0;
26  field bits<1> SOPC = 0;
27  field bits<1> SOPK = 0;
28  field bits<1> SOPP = 0;
29
30  field bits<1> VOP1 = 0;
31  field bits<1> VOP2 = 0;
32  field bits<1> VOP3 = 0;
33  field bits<1> VOPC = 0;
34  field bits<1> SDWA = 0;
35  field bits<1> DPP = 0;
36
37  field bits<1> MUBUF = 0;
38  field bits<1> MTBUF = 0;
39  field bits<1> SMRD = 0;
40  field bits<1> DS = 0;
41  field bits<1> MIMG = 0;
42  field bits<1> FLAT = 0;
43  field bits<1> WQM = 0;
44  field bits<1> VGPRSpill = 0;
45
46  // This bit tells the assembler to use the 32-bit encoding in case it
47  // is unable to infer the encoding from the operands.
48  field bits<1> VOPAsmPrefer32Bit = 0;
49
50  // These need to be kept in sync with the enum in SIInstrFlags.
51  let TSFlags{0} = VM_CNT;
52  let TSFlags{1} = EXP_CNT;
53  let TSFlags{2} = LGKM_CNT;
54
55  let TSFlags{3} = SALU;
56  let TSFlags{4} = VALU;
57
58  let TSFlags{5} = SOP1;
59  let TSFlags{6} = SOP2;
60  let TSFlags{7} = SOPC;
61  let TSFlags{8} = SOPK;
62  let TSFlags{9} = SOPP;
63
64  let TSFlags{10} = VOP1;
65  let TSFlags{11} = VOP2;
66  let TSFlags{12} = VOP3;
67  let TSFlags{13} = VOPC;
68  let TSFlags{14} = SDWA;
69  let TSFlags{15} = DPP;
70
71  let TSFlags{16} = MUBUF;
72  let TSFlags{17} = MTBUF;
73  let TSFlags{18} = SMRD;
74  let TSFlags{19} = DS;
75  let TSFlags{20} = MIMG;
76  let TSFlags{21} = FLAT;
77  let TSFlags{22} = WQM;
78  let TSFlags{23} = VGPRSpill;
79  let TSFlags{24} = VOPAsmPrefer32Bit;
80
81  let SchedRW = [Write32Bit];
82
83  field bits<1> DisableSIDecoder = 0;
84  field bits<1> DisableVIDecoder = 0;
85  field bits<1> DisableDecoder = 0;
86
87  let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);
88}
89
90class Enc32 {
91  field bits<32> Inst;
92  int Size = 4;
93}
94
95class Enc64 {
96  field bits<64> Inst;
97  int Size = 8;
98}
99
100class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
101
102let Uses = [EXEC] in {
103
104class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
105    InstSI <outs, ins, asm, pattern> {
106
107  let mayLoad = 0;
108  let mayStore = 0;
109  let hasSideEffects = 0;
110  let UseNamedOperandTable = 1;
111  let VALU = 1;
112}
113
114class VOPCCommon <dag ins, string asm, list<dag> pattern> :
115    VOPAnyCommon <(outs), ins, asm, pattern> {
116
117  let VOPC = 1;
118  let Size = 4;
119  let Defs = [VCC];
120}
121
122class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> :
123    VOPAnyCommon <outs, ins, asm, pattern> {
124
125  let VOP1 = 1;
126  let Size = 4;
127}
128
129class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> :
130    VOPAnyCommon <outs, ins, asm, pattern> {
131
132  let VOP2 = 1;
133  let Size = 4;
134}
135
136class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern, bit HasMods = 0, bit VOP3Only = 0> :
137    VOPAnyCommon <outs, ins, asm, pattern> {
138
139  // Using complex patterns gives VOP3 patterns a very high complexity rating,
140  // but standalone patterns are almost always prefered, so we need to adjust the
141  // priority lower.  The goal is to use a high number to reduce complexity to
142  // zero (or less than zero).
143  let AddedComplexity = -1000;
144
145  let VOP3 = 1;
146  let VALU = 1;
147
148  let AsmMatchConverter =
149    !if(!eq(VOP3Only,1),
150        "cvtVOP3_only",
151        !if(!eq(HasMods,1), "cvtVOP3_2_mod", "cvtVOP3_2_nomod"));
152  let isCodeGenOnly = 0;
153
154  int Size = 8;
155
156  // Because SGPRs may be allowed if there are multiple operands, we
157  // need a post-isel hook to insert copies in order to avoid
158  // violating constant bus requirements.
159  let hasPostISelHook = 1;
160}
161
162} // End Uses = [EXEC]
163
164//===----------------------------------------------------------------------===//
165// Scalar operations
166//===----------------------------------------------------------------------===//
167
168class SOP1e <bits<8> op> : Enc32 {
169  bits<7> sdst;
170  bits<8> src0;
171
172  let Inst{7-0} = src0;
173  let Inst{15-8} = op;
174  let Inst{22-16} = sdst;
175  let Inst{31-23} = 0x17d; //encoding;
176}
177
178class SOP2e <bits<7> op> : Enc32 {
179  bits<7> sdst;
180  bits<8> src0;
181  bits<8> src1;
182
183  let Inst{7-0} = src0;
184  let Inst{15-8} = src1;
185  let Inst{22-16} = sdst;
186  let Inst{29-23} = op;
187  let Inst{31-30} = 0x2; // encoding
188}
189
190class SOPCe <bits<7> op> : Enc32 {
191  bits<8> src0;
192  bits<8> src1;
193
194  let Inst{7-0} = src0;
195  let Inst{15-8} = src1;
196  let Inst{22-16} = op;
197  let Inst{31-23} = 0x17e;
198}
199
200class SOPKe <bits<5> op> : Enc32 {
201  bits <7> sdst;
202  bits <16> simm16;
203
204  let Inst{15-0} = simm16;
205  let Inst{22-16} = sdst;
206  let Inst{27-23} = op;
207  let Inst{31-28} = 0xb; //encoding
208}
209
210class SOPK64e <bits<5> op> : Enc64 {
211  bits <7> sdst = 0;
212  bits <16> simm16;
213  bits <32> imm;
214
215  let Inst{15-0} = simm16;
216  let Inst{22-16} = sdst;
217  let Inst{27-23} = op;
218  let Inst{31-28} = 0xb;
219
220  let Inst{63-32} = imm;
221}
222
223class SOPPe <bits<7> op> : Enc32 {
224  bits <16> simm16;
225
226  let Inst{15-0} = simm16;
227  let Inst{22-16} = op;
228  let Inst{31-23} = 0x17f; // encoding
229}
230
231class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
232  bits<7> sdst;
233  bits<7> sbase;
234
235  let Inst{8} = imm;
236  let Inst{14-9} = sbase{6-1};
237  let Inst{21-15} = sdst;
238  let Inst{26-22} = op;
239  let Inst{31-27} = 0x18; //encoding
240}
241
242class SMRD_IMMe <bits<5> op> : SMRDe<op, 1> {
243  bits<8> offset;
244  let Inst{7-0} = offset;
245}
246
247class SMRD_SOFFe <bits<5> op> : SMRDe<op, 0> {
248  bits<8> soff;
249  let Inst{7-0} = soff;
250}
251
252
253
254class SMRD_IMMe_ci <bits<5> op> : Enc64 {
255  bits<7> sdst;
256  bits<7> sbase;
257  bits<32> offset;
258
259  let Inst{7-0}   = 0xff;
260  let Inst{8}     = 0;
261  let Inst{14-9}  = sbase{6-1};
262  let Inst{21-15} = sdst;
263  let Inst{26-22} = op;
264  let Inst{31-27} = 0x18; //encoding
265  let Inst{63-32} = offset;
266}
267
268let SchedRW = [WriteSALU] in {
269class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
270    InstSI<outs, ins, asm, pattern> {
271  let mayLoad = 0;
272  let mayStore = 0;
273  let hasSideEffects = 0;
274  let isCodeGenOnly = 0;
275  let SALU = 1;
276  let SOP1 = 1;
277}
278
279class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> :
280    InstSI <outs, ins, asm, pattern> {
281
282  let mayLoad = 0;
283  let mayStore = 0;
284  let hasSideEffects = 0;
285  let isCodeGenOnly = 0;
286  let SALU = 1;
287  let SOP2 = 1;
288
289  let UseNamedOperandTable = 1;
290}
291
292class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
293  InstSI<outs, ins, asm, pattern>, SOPCe <op> {
294
295  let mayLoad = 0;
296  let mayStore = 0;
297  let hasSideEffects = 0;
298  let SALU = 1;
299  let SOPC = 1;
300  let isCodeGenOnly = 0;
301  let Defs = [SCC];
302
303  let UseNamedOperandTable = 1;
304}
305
306class SOPK <dag outs, dag ins, string asm, list<dag> pattern> :
307   InstSI <outs, ins , asm, pattern> {
308
309  let mayLoad = 0;
310  let mayStore = 0;
311  let hasSideEffects = 0;
312  let SALU = 1;
313  let SOPK = 1;
314
315  let UseNamedOperandTable = 1;
316}
317
318class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
319		InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
320
321  let mayLoad = 0;
322  let mayStore = 0;
323  let hasSideEffects = 0;
324  let SALU = 1;
325  let SOPP = 1;
326
327  let UseNamedOperandTable = 1;
328}
329
330} // let SchedRW = [WriteSALU]
331
332class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
333    InstSI<outs, ins, asm, pattern> {
334
335  let LGKM_CNT = 1;
336  let SMRD = 1;
337  let mayStore = 0;
338  let mayLoad = 1;
339  let hasSideEffects = 0;
340  let UseNamedOperandTable = 1;
341  let SchedRW = [WriteSMEM];
342}
343
344//===----------------------------------------------------------------------===//
345// Vector ALU operations
346//===----------------------------------------------------------------------===//
347
348class VOP1e <bits<8> op> : Enc32 {
349  bits<8> vdst;
350  bits<9> src0;
351
352  let Inst{8-0} = src0;
353  let Inst{16-9} = op;
354  let Inst{24-17} = vdst;
355  let Inst{31-25} = 0x3f; //encoding
356}
357
358class VOP2e <bits<6> op> : Enc32 {
359  bits<8> vdst;
360  bits<9> src0;
361  bits<8> src1;
362
363  let Inst{8-0} = src0;
364  let Inst{16-9} = src1;
365  let Inst{24-17} = vdst;
366  let Inst{30-25} = op;
367  let Inst{31} = 0x0; //encoding
368}
369
370class VOP2_MADKe <bits<6> op> : Enc64 {
371
372  bits<8>  vdst;
373  bits<9>  src0;
374  bits<8>  src1;
375  bits<32> imm;
376
377  let Inst{8-0} = src0;
378  let Inst{16-9} = src1;
379  let Inst{24-17} = vdst;
380  let Inst{30-25} = op;
381  let Inst{31} = 0x0; // encoding
382  let Inst{63-32} = imm;
383}
384
385class VOP3a <bits<9> op> : Enc64 {
386  bits<2> src0_modifiers;
387  bits<9> src0;
388  bits<2> src1_modifiers;
389  bits<9> src1;
390  bits<2> src2_modifiers;
391  bits<9> src2;
392  bits<1> clamp;
393  bits<2> omod;
394
395  let Inst{8} = src0_modifiers{1};
396  let Inst{9} = src1_modifiers{1};
397  let Inst{10} = src2_modifiers{1};
398  let Inst{11} = clamp;
399  let Inst{25-17} = op;
400  let Inst{31-26} = 0x34; //encoding
401  let Inst{40-32} = src0;
402  let Inst{49-41} = src1;
403  let Inst{58-50} = src2;
404  let Inst{60-59} = omod;
405  let Inst{61} = src0_modifiers{0};
406  let Inst{62} = src1_modifiers{0};
407  let Inst{63} = src2_modifiers{0};
408}
409
410class VOP3e <bits<9> op> : VOP3a <op> {
411  bits<8> vdst;
412
413  let Inst{7-0} = vdst;
414}
415
416// Encoding used for VOPC instructions encoded as VOP3
417// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
418class VOP3ce <bits<9> op> : VOP3a <op> {
419  bits<8> sdst;
420
421  let Inst{7-0} = sdst;
422}
423
424class VOP3be <bits<9> op> : Enc64 {
425  bits<8> vdst;
426  bits<2> src0_modifiers;
427  bits<9> src0;
428  bits<2> src1_modifiers;
429  bits<9> src1;
430  bits<2> src2_modifiers;
431  bits<9> src2;
432  bits<7> sdst;
433  bits<2> omod;
434
435  let Inst{7-0} = vdst;
436  let Inst{14-8} = sdst;
437  let Inst{25-17} = op;
438  let Inst{31-26} = 0x34; //encoding
439  let Inst{40-32} = src0;
440  let Inst{49-41} = src1;
441  let Inst{58-50} = src2;
442  let Inst{60-59} = omod;
443  let Inst{61} = src0_modifiers{0};
444  let Inst{62} = src1_modifiers{0};
445  let Inst{63} = src2_modifiers{0};
446}
447
448class VOPCe <bits<8> op> : Enc32 {
449  bits<9> src0;
450  bits<8> src1;
451
452  let Inst{8-0} = src0;
453  let Inst{16-9} = src1;
454  let Inst{24-17} = op;
455  let Inst{31-25} = 0x3e;
456}
457
458class VINTRPe <bits<2> op> : Enc32 {
459  bits<8> vdst;
460  bits<8> vsrc;
461  bits<2> attrchan;
462  bits<6> attr;
463
464  let Inst{7-0} = vsrc;
465  let Inst{9-8} = attrchan;
466  let Inst{15-10} = attr;
467  let Inst{17-16} = op;
468  let Inst{25-18} = vdst;
469  let Inst{31-26} = 0x32; // encoding
470}
471
472class DSe <bits<8> op> : Enc64 {
473  bits<8> vdst;
474  bits<1> gds;
475  bits<8> addr;
476  bits<8> data0;
477  bits<8> data1;
478  bits<8> offset0;
479  bits<8> offset1;
480
481  let Inst{7-0} = offset0;
482  let Inst{15-8} = offset1;
483  let Inst{17} = gds;
484  let Inst{25-18} = op;
485  let Inst{31-26} = 0x36; //encoding
486  let Inst{39-32} = addr;
487  let Inst{47-40} = data0;
488  let Inst{55-48} = data1;
489  let Inst{63-56} = vdst;
490}
491
492class MUBUFe <bits<7> op> : Enc64 {
493  bits<12> offset;
494  bits<1> offen;
495  bits<1> idxen;
496  bits<1> glc;
497  bits<1> addr64;
498  bits<1> lds;
499  bits<8> vaddr;
500  bits<8> vdata;
501  bits<7> srsrc;
502  bits<1> slc;
503  bits<1> tfe;
504  bits<8> soffset;
505
506  let Inst{11-0} = offset;
507  let Inst{12} = offen;
508  let Inst{13} = idxen;
509  let Inst{14} = glc;
510  let Inst{15} = addr64;
511  let Inst{16} = lds;
512  let Inst{24-18} = op;
513  let Inst{31-26} = 0x38; //encoding
514  let Inst{39-32} = vaddr;
515  let Inst{47-40} = vdata;
516  let Inst{52-48} = srsrc{6-2};
517  let Inst{54} = slc;
518  let Inst{55} = tfe;
519  let Inst{63-56} = soffset;
520}
521
522class MTBUFe <bits<3> op> : Enc64 {
523  bits<8> vdata;
524  bits<12> offset;
525  bits<1> offen;
526  bits<1> idxen;
527  bits<1> glc;
528  bits<1> addr64;
529  bits<4> dfmt;
530  bits<3> nfmt;
531  bits<8> vaddr;
532  bits<7> srsrc;
533  bits<1> slc;
534  bits<1> tfe;
535  bits<8> soffset;
536
537  let Inst{11-0} = offset;
538  let Inst{12} = offen;
539  let Inst{13} = idxen;
540  let Inst{14} = glc;
541  let Inst{15} = addr64;
542  let Inst{18-16} = op;
543  let Inst{22-19} = dfmt;
544  let Inst{25-23} = nfmt;
545  let Inst{31-26} = 0x3a; //encoding
546  let Inst{39-32} = vaddr;
547  let Inst{47-40} = vdata;
548  let Inst{52-48} = srsrc{6-2};
549  let Inst{54} = slc;
550  let Inst{55} = tfe;
551  let Inst{63-56} = soffset;
552}
553
554class MIMGe <bits<7> op> : Enc64 {
555  bits<8> vdata;
556  bits<4> dmask;
557  bits<1> unorm;
558  bits<1> glc;
559  bits<1> da;
560  bits<1> r128;
561  bits<1> tfe;
562  bits<1> lwe;
563  bits<1> slc;
564  bits<8> vaddr;
565  bits<7> srsrc;
566  bits<7> ssamp;
567
568  let Inst{11-8} = dmask;
569  let Inst{12} = unorm;
570  let Inst{13} = glc;
571  let Inst{14} = da;
572  let Inst{15} = r128;
573  let Inst{16} = tfe;
574  let Inst{17} = lwe;
575  let Inst{24-18} = op;
576  let Inst{25} = slc;
577  let Inst{31-26} = 0x3c;
578  let Inst{39-32} = vaddr;
579  let Inst{47-40} = vdata;
580  let Inst{52-48} = srsrc{6-2};
581  let Inst{57-53} = ssamp{6-2};
582}
583
584class FLATe<bits<7> op> : Enc64 {
585  bits<8> addr;
586  bits<8> data;
587  bits<8> vdst;
588  bits<1> slc;
589  bits<1> glc;
590  bits<1> tfe;
591
592  // 15-0 is reserved.
593  let Inst{16} = glc;
594  let Inst{17} = slc;
595  let Inst{24-18} = op;
596  let Inst{31-26} = 0x37; // Encoding.
597  let Inst{39-32} = addr;
598  let Inst{47-40} = data;
599  // 54-48 is reserved.
600  let Inst{55} = tfe;
601  let Inst{63-56} = vdst;
602}
603
604class EXPe : Enc64 {
605  bits<4> en;
606  bits<6> tgt;
607  bits<1> compr;
608  bits<1> done;
609  bits<1> vm;
610  bits<8> vsrc0;
611  bits<8> vsrc1;
612  bits<8> vsrc2;
613  bits<8> vsrc3;
614
615  let Inst{3-0} = en;
616  let Inst{9-4} = tgt;
617  let Inst{10} = compr;
618  let Inst{11} = done;
619  let Inst{12} = vm;
620  let Inst{31-26} = 0x3e;
621  let Inst{39-32} = vsrc0;
622  let Inst{47-40} = vsrc1;
623  let Inst{55-48} = vsrc2;
624  let Inst{63-56} = vsrc3;
625}
626
627let Uses = [EXEC] in {
628
629class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
630    VOP1Common <outs, ins, asm, pattern>,
631    VOP1e<op> {
632  let isCodeGenOnly = 0;
633}
634
635class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
636    VOP2Common <outs, ins, asm, pattern>, VOP2e<op> {
637  let isCodeGenOnly = 0;
638}
639
640class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
641    VOPCCommon <ins, asm, pattern>, VOPCe <op>;
642
643class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
644    InstSI <outs, ins, asm, pattern> {
645  let mayLoad = 1;
646  let mayStore = 0;
647  let hasSideEffects = 0;
648}
649
650} // End Uses = [EXEC]
651
652//===----------------------------------------------------------------------===//
653// Vector I/O operations
654//===----------------------------------------------------------------------===//
655
656class DS <dag outs, dag ins, string asm, list<dag> pattern> :
657    InstSI <outs, ins, asm, pattern> {
658
659  let LGKM_CNT = 1;
660  let DS = 1;
661  let UseNamedOperandTable = 1;
662  let Uses = [M0, EXEC];
663
664  // Most instruction load and store data, so set this as the default.
665  let mayLoad = 1;
666  let mayStore = 1;
667
668  let hasSideEffects = 0;
669  let AsmMatchConverter = "cvtDS";
670  let SchedRW = [WriteLDS];
671}
672
673class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
674    InstSI<outs, ins, asm, pattern> {
675
676  let VM_CNT = 1;
677  let EXP_CNT = 1;
678  let MUBUF = 1;
679  let Uses = [EXEC];
680
681  let hasSideEffects = 0;
682  let UseNamedOperandTable = 1;
683  let AsmMatchConverter = "cvtMubuf";
684  let SchedRW = [WriteVMEM];
685}
686
687class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> :
688    InstSI<outs, ins, asm, pattern> {
689
690  let VM_CNT = 1;
691  let EXP_CNT = 1;
692  let MTBUF = 1;
693  let Uses = [EXEC];
694
695  let hasSideEffects = 0;
696  let UseNamedOperandTable = 1;
697  let SchedRW = [WriteVMEM];
698}
699
700class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
701    InstSI<outs, ins, asm, pattern>, FLATe <op> {
702  let FLAT = 1;
703  // Internally, FLAT instruction are executed as both an LDS and a
704  // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
705  // and are not considered done until both have been decremented.
706  let VM_CNT = 1;
707  let LGKM_CNT = 1;
708
709  let Uses = [EXEC, FLAT_SCR]; // M0
710
711  let UseNamedOperandTable = 1;
712  let hasSideEffects = 0;
713  let AsmMatchConverter = "cvtFlat";
714  let SchedRW = [WriteVMEM];
715}
716
717class MIMG <dag outs, dag ins, string asm, list<dag> pattern> :
718    InstSI <outs, ins, asm, pattern> {
719
720  let VM_CNT = 1;
721  let EXP_CNT = 1;
722  let MIMG = 1;
723  let Uses = [EXEC];
724
725  let UseNamedOperandTable = 1;
726  let hasSideEffects = 0; // XXX ????
727}
728