1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// SI Instruction format definitions.
11//
12//===----------------------------------------------------------------------===//
13
14class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15    AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
16
17  field bits<1> VM_CNT = 0;
18  field bits<1> EXP_CNT = 0;
19  field bits<1> LGKM_CNT = 0;
20
21  field bits<1> SALU = 0;
22  field bits<1> VALU = 0;
23
24  field bits<1> SOP1 = 0;
25  field bits<1> SOP2 = 0;
26  field bits<1> SOPC = 0;
27  field bits<1> SOPK = 0;
28  field bits<1> SOPP = 0;
29
30  field bits<1> VOP1 = 0;
31  field bits<1> VOP2 = 0;
32  field bits<1> VOP3 = 0;
33  field bits<1> VOPC = 0;
34
35  field bits<1> MUBUF = 0;
36  field bits<1> MTBUF = 0;
37  field bits<1> SMRD = 0;
38  field bits<1> DS = 0;
39  field bits<1> MIMG = 0;
40  field bits<1> FLAT = 0;
41  field bits<1> WQM = 0;
42  field bits<1> VGPRSpill = 0;
43
44  // This bit tells the assembler to use the 32-bit encoding in case it
45  // is unable to infer the encoding from the operands.
46  field bits<1> VOPAsmPrefer32Bit = 0;
47
48  // These need to be kept in sync with the enum in SIInstrFlags.
49  let TSFlags{0} = VM_CNT;
50  let TSFlags{1} = EXP_CNT;
51  let TSFlags{2} = LGKM_CNT;
52
53  let TSFlags{3} = SALU;
54  let TSFlags{4} = VALU;
55
56  let TSFlags{5} = SOP1;
57  let TSFlags{6} = SOP2;
58  let TSFlags{7} = SOPC;
59  let TSFlags{8} = SOPK;
60  let TSFlags{9} = SOPP;
61
62  let TSFlags{10} = VOP1;
63  let TSFlags{11} = VOP2;
64  let TSFlags{12} = VOP3;
65  let TSFlags{13} = VOPC;
66
67  let TSFlags{14} = MUBUF;
68  let TSFlags{15} = MTBUF;
69  let TSFlags{16} = SMRD;
70  let TSFlags{17} = DS;
71  let TSFlags{18} = MIMG;
72  let TSFlags{19} = FLAT;
73  let TSFlags{20} = WQM;
74  let TSFlags{21} = VGPRSpill;
75  let TSFlags{22} = VOPAsmPrefer32Bit;
76
77  let SchedRW = [Write32Bit];
78
79  field bits<1> DisableSIDecoder = 0;
80  field bits<1> DisableVIDecoder = 0;
81  field bits<1> DisableDecoder = 0;
82
83  let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);
84}
85
86class Enc32 {
87  field bits<32> Inst;
88  int Size = 4;
89}
90
91class Enc64 {
92  field bits<64> Inst;
93  int Size = 8;
94}
95
96class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
97
98let Uses = [EXEC] in {
99
100class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
101    InstSI <outs, ins, asm, pattern> {
102
103  let mayLoad = 0;
104  let mayStore = 0;
105  let hasSideEffects = 0;
106  let UseNamedOperandTable = 1;
107  let VALU = 1;
108}
109
110class VOPCCommon <dag ins, string asm, list<dag> pattern> :
111    VOPAnyCommon <(outs), ins, asm, pattern> {
112
113  let VOPC = 1;
114  let Size = 4;
115  let Defs = [VCC];
116}
117
118class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> :
119    VOPAnyCommon <outs, ins, asm, pattern> {
120
121  let VOP1 = 1;
122  let Size = 4;
123}
124
125class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> :
126    VOPAnyCommon <outs, ins, asm, pattern> {
127
128  let VOP2 = 1;
129  let Size = 4;
130}
131
132class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern, bit HasMods = 0, bit VOP3Only = 0> :
133    VOPAnyCommon <outs, ins, asm, pattern> {
134
135  // Using complex patterns gives VOP3 patterns a very high complexity rating,
136  // but standalone patterns are almost always prefered, so we need to adjust the
137  // priority lower.  The goal is to use a high number to reduce complexity to
138  // zero (or less than zero).
139  let AddedComplexity = -1000;
140
141  let VOP3 = 1;
142  let VALU = 1;
143
144  let AsmMatchConverter =
145    !if(!eq(VOP3Only,1),
146        "cvtVOP3_only",
147        !if(!eq(HasMods,1), "cvtVOP3_2_mod", "cvtVOP3_2_nomod"));
148  let isCodeGenOnly = 0;
149
150  int Size = 8;
151
152  // Because SGPRs may be allowed if there are multiple operands, we
153  // need a post-isel hook to insert copies in order to avoid
154  // violating constant bus requirements.
155  let hasPostISelHook = 1;
156}
157
158} // End Uses = [EXEC]
159
160//===----------------------------------------------------------------------===//
161// Scalar operations
162//===----------------------------------------------------------------------===//
163
164class SOP1e <bits<8> op> : Enc32 {
165  bits<7> sdst;
166  bits<8> ssrc0;
167
168  let Inst{7-0} = ssrc0;
169  let Inst{15-8} = op;
170  let Inst{22-16} = sdst;
171  let Inst{31-23} = 0x17d; //encoding;
172}
173
174class SOP2e <bits<7> op> : Enc32 {
175  bits<7> sdst;
176  bits<8> ssrc0;
177  bits<8> ssrc1;
178
179  let Inst{7-0} = ssrc0;
180  let Inst{15-8} = ssrc1;
181  let Inst{22-16} = sdst;
182  let Inst{29-23} = op;
183  let Inst{31-30} = 0x2; // encoding
184}
185
186class SOPCe <bits<7> op> : Enc32 {
187  bits<8> ssrc0;
188  bits<8> ssrc1;
189
190  let Inst{7-0} = ssrc0;
191  let Inst{15-8} = ssrc1;
192  let Inst{22-16} = op;
193  let Inst{31-23} = 0x17e;
194}
195
196class SOPKe <bits<5> op> : Enc32 {
197  bits <7> sdst;
198  bits <16> simm16;
199
200  let Inst{15-0} = simm16;
201  let Inst{22-16} = sdst;
202  let Inst{27-23} = op;
203  let Inst{31-28} = 0xb; //encoding
204}
205
206class SOPK64e <bits<5> op> : Enc64 {
207  bits <7> sdst = 0;
208  bits <16> simm16;
209  bits <32> imm;
210
211  let Inst{15-0} = simm16;
212  let Inst{22-16} = sdst;
213  let Inst{27-23} = op;
214  let Inst{31-28} = 0xb;
215
216  let Inst{63-32} = imm;
217}
218
219class SOPPe <bits<7> op> : Enc32 {
220  bits <16> simm16;
221
222  let Inst{15-0} = simm16;
223  let Inst{22-16} = op;
224  let Inst{31-23} = 0x17f; // encoding
225}
226
227class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
228  bits<7> sdst;
229  bits<7> sbase;
230  bits<8> offset;
231
232  let Inst{7-0} = offset;
233  let Inst{8} = imm;
234  let Inst{14-9} = sbase{6-1};
235  let Inst{21-15} = sdst;
236  let Inst{26-22} = op;
237  let Inst{31-27} = 0x18; //encoding
238}
239
240class SMRD_IMMe_ci <bits<5> op> : Enc64 {
241  bits<7> sdst;
242  bits<7> sbase;
243  bits<32> offset;
244
245  let Inst{7-0}   = 0xff;
246  let Inst{8}     = 0;
247  let Inst{14-9}  = sbase{6-1};
248  let Inst{21-15} = sdst;
249  let Inst{26-22} = op;
250  let Inst{31-27} = 0x18; //encoding
251  let Inst{63-32} = offset;
252}
253
254let SchedRW = [WriteSALU] in {
255class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
256    InstSI<outs, ins, asm, pattern> {
257  let mayLoad = 0;
258  let mayStore = 0;
259  let hasSideEffects = 0;
260  let isCodeGenOnly = 0;
261  let SALU = 1;
262  let SOP1 = 1;
263}
264
265class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> :
266    InstSI <outs, ins, asm, pattern> {
267
268  let mayLoad = 0;
269  let mayStore = 0;
270  let hasSideEffects = 0;
271  let isCodeGenOnly = 0;
272  let SALU = 1;
273  let SOP2 = 1;
274
275  let UseNamedOperandTable = 1;
276}
277
278class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
279  InstSI<outs, ins, asm, pattern>, SOPCe <op> {
280
281  let mayLoad = 0;
282  let mayStore = 0;
283  let hasSideEffects = 0;
284  let SALU = 1;
285  let SOPC = 1;
286  let isCodeGenOnly = 0;
287  let Defs = [SCC];
288
289  let UseNamedOperandTable = 1;
290}
291
292class SOPK <dag outs, dag ins, string asm, list<dag> pattern> :
293   InstSI <outs, ins , asm, pattern> {
294
295  let mayLoad = 0;
296  let mayStore = 0;
297  let hasSideEffects = 0;
298  let SALU = 1;
299  let SOPK = 1;
300
301  let UseNamedOperandTable = 1;
302}
303
304class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
305		InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
306
307  let mayLoad = 0;
308  let mayStore = 0;
309  let hasSideEffects = 0;
310  let SALU = 1;
311  let SOPP = 1;
312
313  let UseNamedOperandTable = 1;
314}
315
316} // let SchedRW = [WriteSALU]
317
318class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
319    InstSI<outs, ins, asm, pattern> {
320
321  let LGKM_CNT = 1;
322  let SMRD = 1;
323  let mayStore = 0;
324  let mayLoad = 1;
325  let hasSideEffects = 0;
326  let UseNamedOperandTable = 1;
327  let SchedRW = [WriteSMEM];
328}
329
330//===----------------------------------------------------------------------===//
331// Vector ALU operations
332//===----------------------------------------------------------------------===//
333
334class VOP1e <bits<8> op> : Enc32 {
335  bits<8> vdst;
336  bits<9> src0;
337
338  let Inst{8-0} = src0;
339  let Inst{16-9} = op;
340  let Inst{24-17} = vdst;
341  let Inst{31-25} = 0x3f; //encoding
342}
343
344class VOP2e <bits<6> op> : Enc32 {
345  bits<8> vdst;
346  bits<9> src0;
347  bits<8> src1;
348
349  let Inst{8-0} = src0;
350  let Inst{16-9} = src1;
351  let Inst{24-17} = vdst;
352  let Inst{30-25} = op;
353  let Inst{31} = 0x0; //encoding
354}
355
356class VOP2_MADKe <bits<6> op> : Enc64 {
357
358  bits<8>  vdst;
359  bits<9>  src0;
360  bits<8>  vsrc1;
361  bits<32> src2;
362
363  let Inst{8-0} = src0;
364  let Inst{16-9} = vsrc1;
365  let Inst{24-17} = vdst;
366  let Inst{30-25} = op;
367  let Inst{31} = 0x0; // encoding
368  let Inst{63-32} = src2;
369}
370
371class VOP3a <bits<9> op> : Enc64 {
372  bits<2> src0_modifiers;
373  bits<9> src0;
374  bits<2> src1_modifiers;
375  bits<9> src1;
376  bits<2> src2_modifiers;
377  bits<9> src2;
378  bits<1> clamp;
379  bits<2> omod;
380
381  let Inst{8} = src0_modifiers{1};
382  let Inst{9} = src1_modifiers{1};
383  let Inst{10} = src2_modifiers{1};
384  let Inst{11} = clamp;
385  let Inst{25-17} = op;
386  let Inst{31-26} = 0x34; //encoding
387  let Inst{40-32} = src0;
388  let Inst{49-41} = src1;
389  let Inst{58-50} = src2;
390  let Inst{60-59} = omod;
391  let Inst{61} = src0_modifiers{0};
392  let Inst{62} = src1_modifiers{0};
393  let Inst{63} = src2_modifiers{0};
394}
395
396class VOP3e <bits<9> op> : VOP3a <op> {
397  bits<8> vdst;
398
399  let Inst{7-0} = vdst;
400}
401
402// Encoding used for VOPC instructions encoded as VOP3
403// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
404class VOP3ce <bits<9> op> : VOP3a <op> {
405  bits<8> sdst;
406
407  let Inst{7-0} = sdst;
408}
409
410class VOP3be <bits<9> op> : Enc64 {
411  bits<8> vdst;
412  bits<2> src0_modifiers;
413  bits<9> src0;
414  bits<2> src1_modifiers;
415  bits<9> src1;
416  bits<2> src2_modifiers;
417  bits<9> src2;
418  bits<7> sdst;
419  bits<2> omod;
420
421  let Inst{7-0} = vdst;
422  let Inst{14-8} = sdst;
423  let Inst{25-17} = op;
424  let Inst{31-26} = 0x34; //encoding
425  let Inst{40-32} = src0;
426  let Inst{49-41} = src1;
427  let Inst{58-50} = src2;
428  let Inst{60-59} = omod;
429  let Inst{61} = src0_modifiers{0};
430  let Inst{62} = src1_modifiers{0};
431  let Inst{63} = src2_modifiers{0};
432}
433
434class VOPCe <bits<8> op> : Enc32 {
435  bits<9> src0;
436  bits<8> vsrc1;
437
438  let Inst{8-0} = src0;
439  let Inst{16-9} = vsrc1;
440  let Inst{24-17} = op;
441  let Inst{31-25} = 0x3e;
442}
443
444class VINTRPe <bits<2> op> : Enc32 {
445  bits<8> vdst;
446  bits<8> vsrc;
447  bits<2> attrchan;
448  bits<6> attr;
449
450  let Inst{7-0} = vsrc;
451  let Inst{9-8} = attrchan;
452  let Inst{15-10} = attr;
453  let Inst{17-16} = op;
454  let Inst{25-18} = vdst;
455  let Inst{31-26} = 0x32; // encoding
456}
457
458class DSe <bits<8> op> : Enc64 {
459  bits<8> vdst;
460  bits<1> gds;
461  bits<8> addr;
462  bits<8> data0;
463  bits<8> data1;
464  bits<8> offset0;
465  bits<8> offset1;
466
467  let Inst{7-0} = offset0;
468  let Inst{15-8} = offset1;
469  let Inst{17} = gds;
470  let Inst{25-18} = op;
471  let Inst{31-26} = 0x36; //encoding
472  let Inst{39-32} = addr;
473  let Inst{47-40} = data0;
474  let Inst{55-48} = data1;
475  let Inst{63-56} = vdst;
476}
477
478class MUBUFe <bits<7> op> : Enc64 {
479  bits<12> offset;
480  bits<1> offen;
481  bits<1> idxen;
482  bits<1> glc;
483  bits<1> addr64;
484  bits<1> lds;
485  bits<8> vaddr;
486  bits<8> vdata;
487  bits<7> srsrc;
488  bits<1> slc;
489  bits<1> tfe;
490  bits<8> soffset;
491
492  let Inst{11-0} = offset;
493  let Inst{12} = offen;
494  let Inst{13} = idxen;
495  let Inst{14} = glc;
496  let Inst{15} = addr64;
497  let Inst{16} = lds;
498  let Inst{24-18} = op;
499  let Inst{31-26} = 0x38; //encoding
500  let Inst{39-32} = vaddr;
501  let Inst{47-40} = vdata;
502  let Inst{52-48} = srsrc{6-2};
503  let Inst{54} = slc;
504  let Inst{55} = tfe;
505  let Inst{63-56} = soffset;
506}
507
508class MTBUFe <bits<3> op> : Enc64 {
509  bits<8> vdata;
510  bits<12> offset;
511  bits<1> offen;
512  bits<1> idxen;
513  bits<1> glc;
514  bits<1> addr64;
515  bits<4> dfmt;
516  bits<3> nfmt;
517  bits<8> vaddr;
518  bits<7> srsrc;
519  bits<1> slc;
520  bits<1> tfe;
521  bits<8> soffset;
522
523  let Inst{11-0} = offset;
524  let Inst{12} = offen;
525  let Inst{13} = idxen;
526  let Inst{14} = glc;
527  let Inst{15} = addr64;
528  let Inst{18-16} = op;
529  let Inst{22-19} = dfmt;
530  let Inst{25-23} = nfmt;
531  let Inst{31-26} = 0x3a; //encoding
532  let Inst{39-32} = vaddr;
533  let Inst{47-40} = vdata;
534  let Inst{52-48} = srsrc{6-2};
535  let Inst{54} = slc;
536  let Inst{55} = tfe;
537  let Inst{63-56} = soffset;
538}
539
540class MIMGe <bits<7> op> : Enc64 {
541  bits<8> vdata;
542  bits<4> dmask;
543  bits<1> unorm;
544  bits<1> glc;
545  bits<1> da;
546  bits<1> r128;
547  bits<1> tfe;
548  bits<1> lwe;
549  bits<1> slc;
550  bits<8> vaddr;
551  bits<7> srsrc;
552  bits<7> ssamp;
553
554  let Inst{11-8} = dmask;
555  let Inst{12} = unorm;
556  let Inst{13} = glc;
557  let Inst{14} = da;
558  let Inst{15} = r128;
559  let Inst{16} = tfe;
560  let Inst{17} = lwe;
561  let Inst{24-18} = op;
562  let Inst{25} = slc;
563  let Inst{31-26} = 0x3c;
564  let Inst{39-32} = vaddr;
565  let Inst{47-40} = vdata;
566  let Inst{52-48} = srsrc{6-2};
567  let Inst{57-53} = ssamp{6-2};
568}
569
570class FLATe<bits<7> op> : Enc64 {
571  bits<8> addr;
572  bits<8> data;
573  bits<8> vdst;
574  bits<1> slc;
575  bits<1> glc;
576  bits<1> tfe;
577
578  // 15-0 is reserved.
579  let Inst{16} = glc;
580  let Inst{17} = slc;
581  let Inst{24-18} = op;
582  let Inst{31-26} = 0x37; // Encoding.
583  let Inst{39-32} = addr;
584  let Inst{47-40} = data;
585  // 54-48 is reserved.
586  let Inst{55} = tfe;
587  let Inst{63-56} = vdst;
588}
589
590class EXPe : Enc64 {
591  bits<4> en;
592  bits<6> tgt;
593  bits<1> compr;
594  bits<1> done;
595  bits<1> vm;
596  bits<8> vsrc0;
597  bits<8> vsrc1;
598  bits<8> vsrc2;
599  bits<8> vsrc3;
600
601  let Inst{3-0} = en;
602  let Inst{9-4} = tgt;
603  let Inst{10} = compr;
604  let Inst{11} = done;
605  let Inst{12} = vm;
606  let Inst{31-26} = 0x3e;
607  let Inst{39-32} = vsrc0;
608  let Inst{47-40} = vsrc1;
609  let Inst{55-48} = vsrc2;
610  let Inst{63-56} = vsrc3;
611}
612
613let Uses = [EXEC] in {
614
615class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
616    VOP1Common <outs, ins, asm, pattern>,
617    VOP1e<op> {
618  let isCodeGenOnly = 0;
619}
620
621class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
622    VOP2Common <outs, ins, asm, pattern>, VOP2e<op> {
623  let isCodeGenOnly = 0;
624}
625
626class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
627    VOPCCommon <ins, asm, pattern>, VOPCe <op>;
628
629class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
630    InstSI <outs, ins, asm, pattern> {
631  let mayLoad = 1;
632  let mayStore = 0;
633  let hasSideEffects = 0;
634}
635
636} // End Uses = [EXEC]
637
638//===----------------------------------------------------------------------===//
639// Vector I/O operations
640//===----------------------------------------------------------------------===//
641
642class DS <dag outs, dag ins, string asm, list<dag> pattern> :
643    InstSI <outs, ins, asm, pattern> {
644
645  let LGKM_CNT = 1;
646  let DS = 1;
647  let UseNamedOperandTable = 1;
648  let Uses = [M0, EXEC];
649
650  // Most instruction load and store data, so set this as the default.
651  let mayLoad = 1;
652  let mayStore = 1;
653
654  let hasSideEffects = 0;
655  let AsmMatchConverter = "cvtDS";
656  let SchedRW = [WriteLDS];
657}
658
659class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
660    InstSI<outs, ins, asm, pattern> {
661
662  let VM_CNT = 1;
663  let EXP_CNT = 1;
664  let MUBUF = 1;
665  let Uses = [EXEC];
666
667  let hasSideEffects = 0;
668  let UseNamedOperandTable = 1;
669  let AsmMatchConverter = "cvtMubuf";
670  let SchedRW = [WriteVMEM];
671}
672
673class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> :
674    InstSI<outs, ins, asm, pattern> {
675
676  let VM_CNT = 1;
677  let EXP_CNT = 1;
678  let MTBUF = 1;
679  let Uses = [EXEC];
680
681  let hasSideEffects = 0;
682  let UseNamedOperandTable = 1;
683  let SchedRW = [WriteVMEM];
684}
685
686class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
687    InstSI<outs, ins, asm, pattern>, FLATe <op> {
688  let FLAT = 1;
689  // Internally, FLAT instruction are executed as both an LDS and a
690  // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
691  // and are not considered done until both have been decremented.
692  let VM_CNT = 1;
693  let LGKM_CNT = 1;
694
695  let Uses = [EXEC, FLAT_SCR]; // M0
696
697  let UseNamedOperandTable = 1;
698  let hasSideEffects = 0;
699  let AsmMatchConverter = "cvtFlat";
700  let SchedRW = [WriteVMEM];
701}
702
703class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
704    InstSI <outs, ins, asm, pattern>, MIMGe <op> {
705
706  let VM_CNT = 1;
707  let EXP_CNT = 1;
708  let MIMG = 1;
709  let Uses = [EXEC];
710
711  let UseNamedOperandTable = 1;
712  let hasSideEffects = 0; // XXX ????
713}
714