1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// SI Instruction format definitions.
10//
11//===----------------------------------------------------------------------===//
12
13class InstSI <dag outs, dag ins, string asm = "",
14              list<dag> pattern = []> :
15  AMDGPUInst<outs, ins, asm, pattern>, GCNPredicateControl {
16  // Low bits - basic encoding information.
17  field bit SALU = 0;
18  field bit VALU = 0;
19
20  // SALU instruction formats.
21  field bit SOP1 = 0;
22  field bit SOP2 = 0;
23  field bit SOPC = 0;
24  field bit SOPK = 0;
25  field bit SOPP = 0;
26
27  // VALU instruction formats.
28  field bit VOP1 = 0;
29  field bit VOP2 = 0;
30  field bit VOPC = 0;
31  field bit VOP3 = 0;
32  field bit VOP3P = 0;
33  field bit VINTRP = 0;
34  field bit SDWA = 0;
35  field bit DPP = 0;
36
37  // Memory instruction formats.
38  field bit MUBUF = 0;
39  field bit MTBUF = 0;
40  field bit SMRD = 0;
41  field bit MIMG = 0;
42  field bit EXP = 0;
43  field bit FLAT = 0;
44  field bit DS = 0;
45
46  // Pseudo instruction formats.
47  field bit VGPRSpill = 0;
48  field bit SGPRSpill = 0;
49
50  // High bits - other information.
51  field bit VM_CNT = 0;
52  field bit EXP_CNT = 0;
53  field bit LGKM_CNT = 0;
54
55  // Whether WQM _must_ be enabled for this instruction.
56  field bit WQM = 0;
57
58  // Whether WQM _must_ be disabled for this instruction.
59  field bit DisableWQM = 0;
60
61  field bit Gather4 = 0;
62
63  // Most sopk treat the immediate as a signed 16-bit, however some
64  // use it as unsigned.
65  field bit SOPKZext = 0;
66
67  // This is an s_store_dword* instruction that requires a cache flush
68  // on wave termination. It is necessary to distinguish from mayStore
69  // SMEM instructions like the cache flush ones.
70  field bit ScalarStore = 0;
71
72  // Whether the operands can be ignored when computing the
73  // instruction size.
74  field bit FixedSize = 0;
75
76  // This bit tells the assembler to use the 32-bit encoding in case it
77  // is unable to infer the encoding from the operands.
78  field bit VOPAsmPrefer32Bit = 0;
79
80  // This bit indicates that this is a VOP3 opcode which supports op_sel
81  // modifier (gfx9 only).
82  field bit VOP3_OPSEL = 0;
83
84  // Is it possible for this instruction to be atomic?
85  field bit maybeAtomic = 0;
86
87  // This bit indicates that this is a VI instruction which is renamed
88  // in GFX9. Required for correct mapping from pseudo to MC.
89  field bit renamedInGFX9 = 0;
90
91  // This bit indicates that this has a floating point result type, so
92  // the clamp modifier has floating point semantics.
93  field bit FPClamp = 0;
94
95  // This bit indicates that instruction may support integer clamping
96  // which depends on GPU features.
97  field bit IntClamp = 0;
98
99  // This field indicates that the clamp applies to the low component
100  // of a packed output register.
101  field bit ClampLo = 0;
102
103  // This field indicates that the clamp applies to the high component
104  // of a packed output register.
105  field bit ClampHi = 0;
106
107  // This bit indicates that this is a packed VOP3P instruction
108  field bit IsPacked = 0;
109
110  // This bit indicates that this is a D16 buffer instruction.
111  field bit D16Buf = 0;
112
113  // This field indicates that FLAT instruction accesses FLAT_GLBL or
114  // FLAT_SCRATCH segment. Must be 0 for non-FLAT instructions.
115  field bit IsNonFlatSeg = 0;
116
117  // This bit indicates that this uses the floating point double precision
118  // rounding mode flags
119  field bit FPDPRounding = 0;
120
121  // Instruction is FP atomic.
122  field bit FPAtomic = 0;
123
124  // These need to be kept in sync with the enum in SIInstrFlags.
125  let TSFlags{0} = SALU;
126  let TSFlags{1} = VALU;
127
128  let TSFlags{2} = SOP1;
129  let TSFlags{3} = SOP2;
130  let TSFlags{4} = SOPC;
131  let TSFlags{5} = SOPK;
132  let TSFlags{6} = SOPP;
133
134  let TSFlags{7} = VOP1;
135  let TSFlags{8} = VOP2;
136  let TSFlags{9} = VOPC;
137  let TSFlags{10} = VOP3;
138  let TSFlags{12} = VOP3P;
139
140  let TSFlags{13} = VINTRP;
141  let TSFlags{14} = SDWA;
142  let TSFlags{15} = DPP;
143
144  let TSFlags{16} = MUBUF;
145  let TSFlags{17} = MTBUF;
146  let TSFlags{18} = SMRD;
147  let TSFlags{19} = MIMG;
148  let TSFlags{20} = EXP;
149  let TSFlags{21} = FLAT;
150  let TSFlags{22} = DS;
151
152  let TSFlags{23} = VGPRSpill;
153  let TSFlags{24} = SGPRSpill;
154
155  let TSFlags{32} = VM_CNT;
156  let TSFlags{33} = EXP_CNT;
157  let TSFlags{34} = LGKM_CNT;
158
159  let TSFlags{35} = WQM;
160  let TSFlags{36} = DisableWQM;
161  let TSFlags{37} = Gather4;
162
163  let TSFlags{38} = SOPKZext;
164  let TSFlags{39} = ScalarStore;
165  let TSFlags{40} = FixedSize;
166  let TSFlags{41} = VOPAsmPrefer32Bit;
167  let TSFlags{42} = VOP3_OPSEL;
168
169  let TSFlags{43} = maybeAtomic;
170  let TSFlags{44} = renamedInGFX9;
171
172  let TSFlags{45} = FPClamp;
173  let TSFlags{46} = IntClamp;
174  let TSFlags{47} = ClampLo;
175  let TSFlags{48} = ClampHi;
176
177  let TSFlags{49} = IsPacked;
178
179  let TSFlags{50} = D16Buf;
180
181  let TSFlags{51} = IsNonFlatSeg;
182
183  let TSFlags{52} = FPDPRounding;
184
185  let TSFlags{53} = FPAtomic;
186
187  let SchedRW = [Write32Bit];
188
189  field bits<1> DisableSIDecoder = 0;
190  field bits<1> DisableVIDecoder = 0;
191  field bits<1> DisableDecoder = 0;
192
193  let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);
194  let AsmVariantName = AMDGPUAsmVariants.Default;
195
196  // Avoid changing source registers in a way that violates constant bus read limitations.
197  let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0))))));
198}
199
200class PseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
201  : InstSI<outs, ins, asm, pattern> {
202  let isPseudo = 1;
203  let isCodeGenOnly = 1;
204}
205
206class SPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
207  : PseudoInstSI<outs, ins, pattern, asm> {
208  let SALU = 1;
209}
210
211class VPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
212  : PseudoInstSI<outs, ins, pattern, asm> {
213  let VALU = 1;
214  let Uses = [EXEC];
215}
216
217class CFPseudoInstSI<dag outs, dag ins, list<dag> pattern = [],
218  bit UseExec = 0, bit DefExec = 0> :
219  SPseudoInstSI<outs, ins, pattern> {
220
221  let Uses = !if(UseExec, [EXEC], []);
222  let Defs = !if(DefExec, [EXEC, SCC], [SCC]);
223  let mayLoad = 0;
224  let mayStore = 0;
225  let hasSideEffects = 0;
226}
227
228class Enc32 {
229  field bits<32> Inst;
230  int Size = 4;
231}
232
233class Enc64 {
234  field bits<64> Inst;
235  int Size = 8;
236}
237
238class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
239
240class VINTRPe <bits<2> op> : Enc32 {
241  bits<8> vdst;
242  bits<8> vsrc;
243  bits<2> attrchan;
244  bits<6> attr;
245
246  let Inst{7-0} = vsrc;
247  let Inst{9-8} = attrchan;
248  let Inst{15-10} = attr;
249  let Inst{17-16} = op;
250  let Inst{25-18} = vdst;
251  let Inst{31-26} = 0x32; // encoding
252}
253
254class MIMGe : Enc64 {
255  bits<8> vdata;
256  bits<4> dmask;
257  bits<1> unorm;
258  bits<1> glc;
259  bits<1> r128;
260  bits<1> tfe;
261  bits<1> lwe;
262  bits<1> slc;
263  bit d16;
264  bits<7> srsrc;
265  bits<7> ssamp;
266
267  let Inst{11-8} = dmask;
268  let Inst{12} = unorm;
269  let Inst{13} = glc;
270  let Inst{15} = r128;
271  let Inst{16} = tfe;
272  let Inst{17} = lwe;
273  let Inst{25} = slc;
274  let Inst{31-26} = 0x3c;
275  let Inst{47-40} = vdata;
276  let Inst{52-48} = srsrc{6-2};
277  let Inst{57-53} = ssamp{6-2};
278  let Inst{63} = d16;
279}
280
281class MIMGe_gfx6789 <bits<7> op> : MIMGe {
282  bits<8> vaddr;
283  bits<1> da;
284
285  let Inst{14} = da;
286  let Inst{24-18} = op;
287  let Inst{39-32} = vaddr;
288}
289
290class MIMGe_gfx10 <bits<8> op> : MIMGe {
291  bits<8> vaddr0;
292  bits<3> dim;
293  bits<2> nsa;
294  bits<1> dlc;
295  bits<1> a16 = 0; // TODO: this should be an operand
296
297  let Inst{0} = op{7};
298  let Inst{2-1} = nsa;
299  let Inst{5-3} = dim;
300  let Inst{7} = dlc;
301  let Inst{24-18} = op{6-0};
302  let Inst{39-32} = vaddr0;
303  let Inst{62} = a16;
304}
305
306class EXPe : Enc64 {
307  bits<4> en;
308  bits<6> tgt;
309  bits<1> compr;
310  bits<1> done;
311  bits<1> vm;
312  bits<8> src0;
313  bits<8> src1;
314  bits<8> src2;
315  bits<8> src3;
316
317  let Inst{3-0} = en;
318  let Inst{9-4} = tgt;
319  let Inst{10} = compr;
320  let Inst{11} = done;
321  let Inst{12} = vm;
322  let Inst{31-26} = 0x3e;
323  let Inst{39-32} = src0;
324  let Inst{47-40} = src1;
325  let Inst{55-48} = src2;
326  let Inst{63-56} = src3;
327}
328
329let Uses = [EXEC] in {
330
331class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
332    InstSI <outs, ins, asm, pattern> {
333  let VINTRP = 1;
334  // VINTRP instructions read parameter values from LDS, but these parameter
335  // values are stored outside of the LDS memory that is allocated to the
336  // shader for general purpose use.
337  //
338  // While it may be possible for ds_read/ds_write instructions to access
339  // the parameter values in LDS, this would essentially be an out-of-bounds
340  // memory access which we consider to be undefined behavior.
341  //
342  // So even though these instructions read memory, this memory is outside the
343  // addressable memory space for the shader, and we consider these instructions
344  // to be readnone.
345  let mayLoad = 0;
346  let mayStore = 0;
347  let hasSideEffects = 0;
348  let VALU = 1;
349}
350
351class EXPCommon<dag outs, dag ins, string asm, list<dag> pattern> :
352  InstSI<outs, ins, asm, pattern> {
353  let EXP = 1;
354  let EXP_CNT = 1;
355  let mayLoad = 0; // Set to 1 if done bit is set.
356  let mayStore = 1;
357  let UseNamedOperandTable = 1;
358  let Uses = [EXEC];
359  let SchedRW = [WriteExport];
360}
361
362} // End Uses = [EXEC]
363