1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief SI DAG Lowering interface definition 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 16 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 17 18 #include "AMDGPUISelLowering.h" 19 #include "SIInstrInfo.h" 20 21 namespace llvm { 22 23 class SITargetLowering final : public AMDGPUTargetLowering { 24 SDValue LowerParameterPtr(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, 25 unsigned Offset) const; 26 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, 27 SDValue Chain, unsigned Offset, bool Signed) const; 28 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 29 SelectionDAG &DAG) const override; 30 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, 31 MVT VT, unsigned Offset) const; 32 33 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 34 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 35 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 36 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 37 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 38 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const; 39 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const; 40 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const; 41 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const; 42 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; 43 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const; 44 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 45 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 46 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 47 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 48 49 /// \brief Converts \p Op, which must be of floating point type, to the 50 /// floating point type \p VT, by either extending or truncating it. 51 SDValue getFPExtOrFPTrunc(SelectionDAG &DAG, 52 SDValue Op, 53 const SDLoc &DL, 54 EVT VT) const; 55 56 /// \brief Custom lowering for ISD::FP_ROUND for MVT::f16. 57 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 58 59 SDValue getSegmentAperture(unsigned AS, SelectionDAG &DAG) const; 60 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const; 61 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const; 62 63 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 64 65 SDValue performUCharToFloatCombine(SDNode *N, 66 DAGCombinerInfo &DCI) const; 67 SDValue performSHLPtrCombine(SDNode *N, 68 unsigned AS, 69 DAGCombinerInfo &DCI) const; 70 71 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL, 72 unsigned Opc, SDValue LHS, 73 const ConstantSDNode *CRHS) const; 74 75 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; 76 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; 77 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const; 78 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; 79 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const; 80 81 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const; 82 83 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; 84 85 bool isLegalFlatAddressingMode(const AddrMode &AM) const; 86 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 87 88 bool isCFIntrinsic(const SDNode *Intr) const; 89 90 void createDebuggerPrologueStackObjects(MachineFunction &MF) const; 91 92 /// \returns True if fixup needs to be emitted for given global value \p GV, 93 /// false otherwise. 94 bool shouldEmitFixup(const GlobalValue *GV) const; 95 96 /// \returns True if GOT relocation needs to be emitted for given global value 97 /// \p GV, false otherwise. 98 bool shouldEmitGOTReloc(const GlobalValue *GV) const; 99 100 /// \returns True if PC-relative relocation needs to be emitted for given 101 /// global value \p GV, false otherwise. 102 bool shouldEmitPCReloc(const GlobalValue *GV) const; 103 104 public: 105 SITargetLowering(const TargetMachine &tm, const SISubtarget &STI); 106 107 const SISubtarget *getSubtarget() const; 108 109 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 110 unsigned IntrinsicID) const override; 111 112 bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 113 EVT /*VT*/) const override; 114 115 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 116 unsigned AS) const override; 117 118 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, 119 unsigned Align, 120 bool *IsFast) const override; 121 122 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 123 unsigned SrcAlign, bool IsMemset, 124 bool ZeroMemset, 125 bool MemcpyStrSrc, 126 MachineFunction &MF) const override; 127 128 bool isMemOpUniform(const SDNode *N) const; 129 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const; 130 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 131 bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 132 133 TargetLoweringBase::LegalizeTypeAction 134 getPreferredVectorAction(EVT VT) const override; 135 136 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 137 Type *Ty) const override; 138 139 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override; 140 141 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 142 143 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 144 bool isVarArg, 145 const SmallVectorImpl<ISD::InputArg> &Ins, 146 const SDLoc &DL, SelectionDAG &DAG, 147 SmallVectorImpl<SDValue> &InVals) const override; 148 149 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 150 const SmallVectorImpl<ISD::OutputArg> &Outs, 151 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 152 SelectionDAG &DAG) const override; 153 154 unsigned getRegisterByName(const char* RegName, EVT VT, 155 SelectionDAG &DAG) const override; 156 157 MachineBasicBlock *splitKillBlock(MachineInstr &MI, 158 MachineBasicBlock *BB) const; 159 160 MachineBasicBlock * 161 EmitInstrWithCustomInserter(MachineInstr &MI, 162 MachineBasicBlock *BB) const override; 163 bool enableAggressiveFMAFusion(EVT VT) const override; 164 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 165 EVT VT) const override; 166 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; 167 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 168 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 169 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 170 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 171 void AdjustInstrPostInstrSelection(MachineInstr &MI, 172 SDNode *Node) const override; 173 174 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, 175 unsigned Reg, EVT VT) const override; 176 void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; 177 178 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, 179 SDValue Ptr) const; 180 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, 181 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const; 182 std::pair<unsigned, const TargetRegisterClass *> 183 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 184 StringRef Constraint, MVT VT) const override; 185 ConstraintType getConstraintType(StringRef Constraint) const override; 186 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, 187 SDValue V) const; 188 }; 189 190 } // End namespace llvm 191 192 #endif 193