1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief SI DAG Lowering interface definition 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 16 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 17 18 #include "AMDGPUISelLowering.h" 19 #include "SIInstrInfo.h" 20 21 namespace llvm { 22 23 class SITargetLowering final : public AMDGPUTargetLowering { 24 SDValue LowerParameterPtr(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, 25 unsigned Offset) const; 26 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, 27 SDValue Chain, unsigned Offset, bool Signed, 28 const ISD::InputArg *Arg = nullptr) const; 29 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 30 SelectionDAG &DAG) const override; 31 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, 32 MVT VT, unsigned Offset) const; 33 34 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 35 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 36 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 37 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 38 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 39 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const; 40 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const; 41 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const; 42 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const; 43 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const; 44 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; 45 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const; 46 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 47 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 48 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 49 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 50 51 /// \brief Converts \p Op, which must be of floating point type, to the 52 /// floating point type \p VT, by either extending or truncating it. 53 SDValue getFPExtOrFPTrunc(SelectionDAG &DAG, 54 SDValue Op, 55 const SDLoc &DL, 56 EVT VT) const; 57 58 /// \brief Custom lowering for ISD::FP_ROUND for MVT::f16. 59 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 60 61 SDValue getSegmentAperture(unsigned AS, SelectionDAG &DAG) const; 62 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const; 63 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 64 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 65 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const; 66 67 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 68 69 SDValue performUCharToFloatCombine(SDNode *N, 70 DAGCombinerInfo &DCI) const; 71 SDValue performSHLPtrCombine(SDNode *N, 72 unsigned AS, 73 DAGCombinerInfo &DCI) const; 74 75 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const; 76 77 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL, 78 unsigned Opc, SDValue LHS, 79 const ConstantSDNode *CRHS) const; 80 81 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; 82 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; 83 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const; 84 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; 85 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const; 86 87 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 88 SDValue Op0, SDValue Op1) const; 89 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 90 SDValue Op0, SDValue Op1, bool Signed) const; 91 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const; 92 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const; 93 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const; 94 95 unsigned getFusedOpcode(const SelectionDAG &DAG, 96 const SDNode *N0, const SDNode *N1) const; 97 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 98 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 99 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; 100 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const; 101 102 bool isLegalFlatAddressingMode(const AddrMode &AM) const; 103 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 104 105 bool isCFIntrinsic(const SDNode *Intr) const; 106 107 void createDebuggerPrologueStackObjects(MachineFunction &MF) const; 108 109 /// \returns True if fixup needs to be emitted for given global value \p GV, 110 /// false otherwise. 111 bool shouldEmitFixup(const GlobalValue *GV) const; 112 113 /// \returns True if GOT relocation needs to be emitted for given global value 114 /// \p GV, false otherwise. 115 bool shouldEmitGOTReloc(const GlobalValue *GV) const; 116 117 /// \returns True if PC-relative relocation needs to be emitted for given 118 /// global value \p GV, false otherwise. 119 bool shouldEmitPCReloc(const GlobalValue *GV) const; 120 121 public: 122 SITargetLowering(const TargetMachine &tm, const SISubtarget &STI); 123 124 const SISubtarget *getSubtarget() const; 125 126 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 127 unsigned IntrinsicID) const override; 128 129 bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 130 EVT /*VT*/) const override; 131 132 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 133 unsigned AS) const override; 134 135 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, 136 unsigned Align, 137 bool *IsFast) const override; 138 139 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 140 unsigned SrcAlign, bool IsMemset, 141 bool ZeroMemset, 142 bool MemcpyStrSrc, 143 MachineFunction &MF) const override; 144 145 bool isMemOpUniform(const SDNode *N) const; 146 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const; 147 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 148 bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 149 150 TargetLoweringBase::LegalizeTypeAction 151 getPreferredVectorAction(EVT VT) const override; 152 153 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 154 Type *Ty) const override; 155 156 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override; 157 158 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 159 160 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 161 bool isVarArg, 162 const SmallVectorImpl<ISD::InputArg> &Ins, 163 const SDLoc &DL, SelectionDAG &DAG, 164 SmallVectorImpl<SDValue> &InVals) const override; 165 166 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 167 const SmallVectorImpl<ISD::OutputArg> &Outs, 168 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 169 SelectionDAG &DAG) const override; 170 171 unsigned getRegisterByName(const char* RegName, EVT VT, 172 SelectionDAG &DAG) const override; 173 174 MachineBasicBlock *splitKillBlock(MachineInstr &MI, 175 MachineBasicBlock *BB) const; 176 177 MachineBasicBlock * 178 EmitInstrWithCustomInserter(MachineInstr &MI, 179 MachineBasicBlock *BB) const override; 180 bool enableAggressiveFMAFusion(EVT VT) const override; 181 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 182 EVT VT) const override; 183 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; 184 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 185 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 186 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 187 SelectionDAG &DAG) const override; 188 189 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 190 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 191 void AdjustInstrPostInstrSelection(MachineInstr &MI, 192 SDNode *Node) const override; 193 194 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, 195 unsigned Reg, EVT VT) const override; 196 void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; 197 198 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, 199 SDValue Ptr) const; 200 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, 201 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const; 202 std::pair<unsigned, const TargetRegisterClass *> 203 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 204 StringRef Constraint, MVT VT) const override; 205 ConstraintType getConstraintType(StringRef Constraint) const override; 206 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, 207 SDValue V) const; 208 }; 209 210 } // End namespace llvm 211 212 #endif 213