1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief SI DAG Lowering interface definition 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 16 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 17 18 #include "AMDGPUISelLowering.h" 19 #include "SIInstrInfo.h" 20 21 namespace llvm { 22 23 class SITargetLowering final : public AMDGPUTargetLowering { 24 SDValue LowerParameterPtr(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, 25 unsigned Offset) const; 26 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, 27 SDValue Chain, unsigned Offset, bool Signed, 28 const ISD::InputArg *Arg = nullptr) const; 29 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 30 SelectionDAG &DAG) const override; 31 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, 32 MVT VT, unsigned Offset) const; 33 34 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 35 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 36 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 37 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 38 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 39 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const; 40 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const; 41 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const; 42 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const; 43 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const; 44 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; 45 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const; 46 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 47 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 48 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 49 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 50 51 /// \brief Converts \p Op, which must be of floating point type, to the 52 /// floating point type \p VT, by either extending or truncating it. 53 SDValue getFPExtOrFPTrunc(SelectionDAG &DAG, 54 SDValue Op, 55 const SDLoc &DL, 56 EVT VT) const; 57 58 /// \brief Custom lowering for ISD::FP_ROUND for MVT::f16. 59 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 60 61 SDValue getSegmentAperture(unsigned AS, SelectionDAG &DAG) const; 62 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const; 63 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const; 64 65 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 66 67 SDValue performUCharToFloatCombine(SDNode *N, 68 DAGCombinerInfo &DCI) const; 69 SDValue performSHLPtrCombine(SDNode *N, 70 unsigned AS, 71 DAGCombinerInfo &DCI) const; 72 73 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const; 74 75 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL, 76 unsigned Opc, SDValue LHS, 77 const ConstantSDNode *CRHS) const; 78 79 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; 80 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; 81 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const; 82 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; 83 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const; 84 85 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const; 86 87 unsigned getFusedOpcode(const SelectionDAG &DAG, 88 const SDNode *N0, const SDNode *N1) const; 89 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 90 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 91 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; 92 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const; 93 94 bool isLegalFlatAddressingMode(const AddrMode &AM) const; 95 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 96 97 bool isCFIntrinsic(const SDNode *Intr) const; 98 99 void createDebuggerPrologueStackObjects(MachineFunction &MF) const; 100 101 /// \returns True if fixup needs to be emitted for given global value \p GV, 102 /// false otherwise. 103 bool shouldEmitFixup(const GlobalValue *GV) const; 104 105 /// \returns True if GOT relocation needs to be emitted for given global value 106 /// \p GV, false otherwise. 107 bool shouldEmitGOTReloc(const GlobalValue *GV) const; 108 109 /// \returns True if PC-relative relocation needs to be emitted for given 110 /// global value \p GV, false otherwise. 111 bool shouldEmitPCReloc(const GlobalValue *GV) const; 112 113 public: 114 SITargetLowering(const TargetMachine &tm, const SISubtarget &STI); 115 116 const SISubtarget *getSubtarget() const; 117 118 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 119 unsigned IntrinsicID) const override; 120 121 bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 122 EVT /*VT*/) const override; 123 124 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 125 unsigned AS) const override; 126 127 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, 128 unsigned Align, 129 bool *IsFast) const override; 130 131 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 132 unsigned SrcAlign, bool IsMemset, 133 bool ZeroMemset, 134 bool MemcpyStrSrc, 135 MachineFunction &MF) const override; 136 137 bool isMemOpUniform(const SDNode *N) const; 138 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const; 139 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 140 bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 141 142 TargetLoweringBase::LegalizeTypeAction 143 getPreferredVectorAction(EVT VT) const override; 144 145 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 146 Type *Ty) const override; 147 148 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override; 149 150 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 151 152 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 153 bool isVarArg, 154 const SmallVectorImpl<ISD::InputArg> &Ins, 155 const SDLoc &DL, SelectionDAG &DAG, 156 SmallVectorImpl<SDValue> &InVals) const override; 157 158 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 159 const SmallVectorImpl<ISD::OutputArg> &Outs, 160 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 161 SelectionDAG &DAG) const override; 162 163 unsigned getRegisterByName(const char* RegName, EVT VT, 164 SelectionDAG &DAG) const override; 165 166 MachineBasicBlock *splitKillBlock(MachineInstr &MI, 167 MachineBasicBlock *BB) const; 168 169 MachineBasicBlock * 170 EmitInstrWithCustomInserter(MachineInstr &MI, 171 MachineBasicBlock *BB) const override; 172 bool enableAggressiveFMAFusion(EVT VT) const override; 173 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 174 EVT VT) const override; 175 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; 176 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 177 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 178 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 179 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 180 void AdjustInstrPostInstrSelection(MachineInstr &MI, 181 SDNode *Node) const override; 182 183 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, 184 unsigned Reg, EVT VT) const override; 185 void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; 186 187 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, 188 SDValue Ptr) const; 189 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, 190 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const; 191 std::pair<unsigned, const TargetRegisterClass *> 192 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 193 StringRef Constraint, MVT VT) const override; 194 ConstraintType getConstraintType(StringRef Constraint) const override; 195 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, 196 SDValue V) const; 197 }; 198 199 } // End namespace llvm 200 201 #endif 202