1 //===-- SIFixVGPRCopies.cpp - Fix VGPR Copies after regalloc --------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// Add implicit use of exec to vector register copies. 11 /// 12 //===----------------------------------------------------------------------===// 13 14 #include "AMDGPU.h" 15 #include "AMDGPUSubtarget.h" 16 #include "llvm/CodeGen/MachineFunctionPass.h" 17 18 using namespace llvm; 19 20 #define DEBUG_TYPE "si-fix-vgpr-copies" 21 22 namespace { 23 24 class SIFixVGPRCopies : public MachineFunctionPass { 25 public: 26 static char ID; 27 28 public: 29 SIFixVGPRCopies() : MachineFunctionPass(ID) { 30 initializeSIFixVGPRCopiesPass(*PassRegistry::getPassRegistry()); 31 } 32 33 bool runOnMachineFunction(MachineFunction &MF) override; 34 35 StringRef getPassName() const override { return "SI Fix VGPR copies"; } 36 }; 37 38 } // End anonymous namespace. 39 40 INITIALIZE_PASS(SIFixVGPRCopies, DEBUG_TYPE, "SI Fix VGPR copies", false, false) 41 42 char SIFixVGPRCopies::ID = 0; 43 44 char &llvm::SIFixVGPRCopiesID = SIFixVGPRCopies::ID; 45 46 bool SIFixVGPRCopies::runOnMachineFunction(MachineFunction &MF) { 47 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); 48 const SIRegisterInfo *TRI = ST.getRegisterInfo(); 49 const SIInstrInfo *TII = ST.getInstrInfo(); 50 bool Changed = false; 51 52 for (MachineBasicBlock &MBB : MF) { 53 for (MachineInstr &MI : MBB) { 54 switch (MI.getOpcode()) { 55 case AMDGPU::COPY: 56 if (TII->isVGPRCopy(MI) && !MI.readsRegister(AMDGPU::EXEC, TRI)) { 57 MI.addOperand(MF, 58 MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); 59 LLVM_DEBUG(dbgs() << "Add exec use to " << MI); 60 Changed = true; 61 } 62 break; 63 default: 64 break; 65 } 66 } 67 } 68 69 return Changed; 70 } 71