1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #include "llvm/MC/MCInstrDesc.h" 12 13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 14 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 15 16 namespace SIInstrFlags { 17 // This needs to be kept in sync with the field bits in InstSI. 18 enum { 19 SALU = 1 << 3, 20 VALU = 1 << 4, 21 22 SOP1 = 1 << 5, 23 SOP2 = 1 << 6, 24 SOPC = 1 << 7, 25 SOPK = 1 << 8, 26 SOPP = 1 << 9, 27 28 VOP1 = 1 << 10, 29 VOP2 = 1 << 11, 30 VOP3 = 1 << 12, 31 VOPC = 1 << 13, 32 SDWA = 1 << 14, 33 DPP = 1 << 15, 34 35 MUBUF = 1 << 16, 36 MTBUF = 1 << 17, 37 SMRD = 1 << 18, 38 DS = 1 << 19, 39 MIMG = 1 << 20, 40 FLAT = 1 << 21, 41 WQM = 1 << 22, 42 VGPRSpill = 1 << 23, 43 VOPAsmPrefer32Bit = 1 << 24 44 }; 45 } 46 47 namespace llvm { 48 namespace AMDGPU { 49 enum OperandType { 50 /// Operand with register or 32-bit immediate 51 OPERAND_REG_IMM32 = MCOI::OPERAND_FIRST_TARGET, 52 /// Operand with register or inline constant 53 OPERAND_REG_INLINE_C 54 }; 55 } 56 } 57 58 namespace SIInstrFlags { 59 enum Flags { 60 // First 4 bits are the instruction encoding 61 VM_CNT = 1 << 0, 62 EXP_CNT = 1 << 1, 63 LGKM_CNT = 1 << 2 64 }; 65 66 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. 67 // The result is true if any of these tests are true. 68 enum ClassFlags { 69 S_NAN = 1 << 0, // Signaling NaN 70 Q_NAN = 1 << 1, // Quiet NaN 71 N_INFINITY = 1 << 2, // Negative infinity 72 N_NORMAL = 1 << 3, // Negative normal 73 N_SUBNORMAL = 1 << 4, // Negative subnormal 74 N_ZERO = 1 << 5, // Negative zero 75 P_ZERO = 1 << 6, // Positive zero 76 P_SUBNORMAL = 1 << 7, // Positive subnormal 77 P_NORMAL = 1 << 8, // Positive normal 78 P_INFINITY = 1 << 9 // Positive infinity 79 }; 80 } 81 82 // Input operand modifiers bit-masks 83 // NEG and SEXT share same bit-mask because they can't be set simultaneously. 84 namespace SISrcMods { 85 enum { 86 NEG = 1 << 0, // Floating-point negate modifier 87 ABS = 1 << 1, // Floating-point absolute modifier 88 SEXT = 1 << 0 // Integer sign-extend modifier 89 }; 90 } 91 92 namespace SIOutMods { 93 enum { 94 NONE = 0, 95 MUL2 = 1, 96 MUL4 = 2, 97 DIV2 = 3 98 }; 99 } 100 101 namespace llvm { 102 namespace AMDGPU { 103 namespace EncValues { // Encoding values of enum9/8/7 operands 104 105 enum { 106 SGPR_MIN = 0, 107 SGPR_MAX = 101, 108 TTMP_MIN = 112, 109 TTMP_MAX = 123, 110 INLINE_INTEGER_C_MIN = 128, 111 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64 112 INLINE_INTEGER_C_MAX = 208, 113 INLINE_FLOATING_C_MIN = 240, 114 INLINE_FLOATING_C_MAX = 248, 115 LITERAL_CONST = 255, 116 VGPR_MIN = 256, 117 VGPR_MAX = 511 118 }; 119 120 } // namespace EncValues 121 } // namespace AMDGPU 122 } // namespace llvm 123 124 namespace llvm { 125 namespace AMDGPU { 126 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns. 127 128 enum Id { // Message ID, width(4) [3:0]. 129 ID_UNKNOWN_ = -1, 130 ID_INTERRUPT = 1, 131 ID_GS, 132 ID_GS_DONE, 133 ID_SYSMSG = 15, 134 ID_GAPS_LAST_, // Indicate that sequence has gaps. 135 ID_GAPS_FIRST_ = ID_INTERRUPT, 136 ID_SHIFT_ = 0, 137 ID_WIDTH_ = 4, 138 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 139 }; 140 141 enum Op { // Both GS and SYS operation IDs. 142 OP_UNKNOWN_ = -1, 143 OP_SHIFT_ = 4, 144 // width(2) [5:4] 145 OP_GS_NOP = 0, 146 OP_GS_CUT, 147 OP_GS_EMIT, 148 OP_GS_EMIT_CUT, 149 OP_GS_LAST_, 150 OP_GS_FIRST_ = OP_GS_NOP, 151 OP_GS_WIDTH_ = 2, 152 OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_), 153 // width(3) [6:4] 154 OP_SYS_ECC_ERR_INTERRUPT = 1, 155 OP_SYS_REG_RD, 156 OP_SYS_HOST_TRAP_ACK, 157 OP_SYS_TTRACE_PC, 158 OP_SYS_LAST_, 159 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT, 160 OP_SYS_WIDTH_ = 3, 161 OP_SYS_MASK_ = (((1 << OP_SYS_WIDTH_) - 1) << OP_SHIFT_) 162 }; 163 164 enum StreamId { // Stream ID, (2) [9:8]. 165 STREAM_ID_DEFAULT_ = 0, 166 STREAM_ID_LAST_ = 4, 167 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_, 168 STREAM_ID_SHIFT_ = 8, 169 STREAM_ID_WIDTH_= 2, 170 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_) 171 }; 172 173 } // namespace SendMsg 174 175 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns. 176 177 enum Id { // HwRegCode, (6) [5:0] 178 ID_UNKNOWN_ = -1, 179 ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined. 180 ID_SYMBOLIC_LAST_ = 8, 181 ID_SHIFT_ = 0, 182 ID_WIDTH_ = 6, 183 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 184 }; 185 186 enum Offset { // Offset, (5) [10:6] 187 OFFSET_DEFAULT_ = 0, 188 OFFSET_SHIFT_ = 6, 189 OFFSET_WIDTH_ = 5, 190 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_) 191 }; 192 193 enum WidthMinusOne { // WidthMinusOne, (5) [15:11] 194 WIDTH_M1_DEFAULT_ = 31, 195 WIDTH_M1_SHIFT_ = 11, 196 WIDTH_M1_WIDTH_ = 5, 197 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_) 198 }; 199 200 } // namespace Hwreg 201 } // namespace AMDGPU 202 } // namespace llvm 203 204 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 205 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C 206 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) 207 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 208 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 209 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 210 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) 211 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) 212 213 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C 214 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) 215 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 216 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE 217 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) 218 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) 219 #define C_00B84C_USER_SGPR 0xFFFFFFC1 220 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) 221 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) 222 #define C_00B84C_TGID_X_EN 0xFFFFFF7F 223 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) 224 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) 225 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF 226 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) 227 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) 228 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF 229 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) 230 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) 231 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF 232 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) 233 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) 234 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF 235 /* CIK */ 236 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) 237 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) 238 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF 239 /* */ 240 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) 241 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) 242 #define C_00B84C_LDS_SIZE 0xFF007FFF 243 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) 244 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) 245 #define C_00B84C_EXCP_EN 246 247 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC 248 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 249 250 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 251 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) 252 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) 253 #define C_00B848_VGPRS 0xFFFFFFC0 254 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) 255 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) 256 #define C_00B848_SGPRS 0xFFFFFC3F 257 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) 258 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) 259 #define C_00B848_PRIORITY 0xFFFFF3FF 260 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) 261 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 262 #define C_00B848_FLOAT_MODE 0xFFF00FFF 263 #define S_00B848_PRIV(x) (((x) & 0x1) << 20) 264 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1) 265 #define C_00B848_PRIV 0xFFEFFFFF 266 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) 267 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) 268 #define C_00B848_DX10_CLAMP 0xFFDFFFFF 269 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) 270 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) 271 #define C_00B848_DEBUG_MODE 0xFFBFFFFF 272 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) 273 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) 274 #define C_00B848_IEEE_MODE 0xFF7FFFFF 275 276 277 // Helpers for setting FLOAT_MODE 278 #define FP_ROUND_ROUND_TO_NEAREST 0 279 #define FP_ROUND_ROUND_TO_INF 1 280 #define FP_ROUND_ROUND_TO_NEGINF 2 281 #define FP_ROUND_ROUND_TO_ZERO 3 282 283 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double 284 // precision. 285 #define FP_ROUND_MODE_SP(x) ((x) & 0x3) 286 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2) 287 288 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0 289 #define FP_DENORM_FLUSH_OUT 1 290 #define FP_DENORM_FLUSH_IN 2 291 #define FP_DENORM_FLUSH_NONE 3 292 293 294 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double 295 // precision. 296 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4) 297 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6) 298 299 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 300 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12) 301 302 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 303 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) 304 305 306 #endif 307