1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #include "llvm/MC/MCInstrDesc.h" 12 13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 14 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 15 16 namespace SIInstrFlags { 17 // This needs to be kept in sync with the field bits in InstSI. 18 enum { 19 SALU = 1 << 3, 20 VALU = 1 << 4, 21 22 SOP1 = 1 << 5, 23 SOP2 = 1 << 6, 24 SOPC = 1 << 7, 25 SOPK = 1 << 8, 26 SOPP = 1 << 9, 27 28 VOP1 = 1 << 10, 29 VOP2 = 1 << 11, 30 VOP3 = 1 << 12, 31 VOPC = 1 << 13, 32 DPP = 1 << 14, 33 34 MUBUF = 1 << 15, 35 MTBUF = 1 << 16, 36 SMRD = 1 << 17, 37 DS = 1 << 18, 38 MIMG = 1 << 19, 39 FLAT = 1 << 20, 40 WQM = 1 << 21, 41 VGPRSpill = 1 << 22, 42 VOPAsmPrefer32Bit = 1 << 23 43 }; 44 } 45 46 namespace llvm { 47 namespace AMDGPU { 48 enum OperandType { 49 /// Operand with register or 32-bit immediate 50 OPERAND_REG_IMM32 = llvm::MCOI::OPERAND_FIRST_TARGET, 51 /// Operand with register or inline constant 52 OPERAND_REG_INLINE_C 53 }; 54 } 55 } 56 57 namespace SIInstrFlags { 58 enum Flags { 59 // First 4 bits are the instruction encoding 60 VM_CNT = 1 << 0, 61 EXP_CNT = 1 << 1, 62 LGKM_CNT = 1 << 2 63 }; 64 65 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. 66 // The result is true if any of these tests are true. 67 enum ClassFlags { 68 S_NAN = 1 << 0, // Signaling NaN 69 Q_NAN = 1 << 1, // Quiet NaN 70 N_INFINITY = 1 << 2, // Negative infinity 71 N_NORMAL = 1 << 3, // Negative normal 72 N_SUBNORMAL = 1 << 4, // Negative subnormal 73 N_ZERO = 1 << 5, // Negative zero 74 P_ZERO = 1 << 6, // Positive zero 75 P_SUBNORMAL = 1 << 7, // Positive subnormal 76 P_NORMAL = 1 << 8, // Positive normal 77 P_INFINITY = 1 << 9 // Positive infinity 78 }; 79 } 80 81 namespace SISrcMods { 82 enum { 83 NEG = 1 << 0, 84 ABS = 1 << 1 85 }; 86 } 87 88 namespace SIOutMods { 89 enum { 90 NONE = 0, 91 MUL2 = 1, 92 MUL4 = 2, 93 DIV2 = 3 94 }; 95 } 96 97 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 98 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C 99 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) 100 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 101 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 102 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 103 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) 104 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) 105 106 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C 107 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) 108 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 109 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE 110 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) 111 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) 112 #define C_00B84C_USER_SGPR 0xFFFFFFC1 113 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) 114 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) 115 #define C_00B84C_TGID_X_EN 0xFFFFFF7F 116 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) 117 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) 118 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF 119 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) 120 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) 121 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF 122 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) 123 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) 124 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF 125 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) 126 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) 127 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF 128 /* CIK */ 129 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) 130 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) 131 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF 132 /* */ 133 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) 134 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) 135 #define C_00B84C_LDS_SIZE 0xFF007FFF 136 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) 137 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) 138 #define C_00B84C_EXCP_EN 139 140 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC 141 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 142 143 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 144 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) 145 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) 146 #define C_00B848_VGPRS 0xFFFFFFC0 147 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) 148 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) 149 #define C_00B848_SGPRS 0xFFFFFC3F 150 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) 151 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) 152 #define C_00B848_PRIORITY 0xFFFFF3FF 153 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) 154 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 155 #define C_00B848_FLOAT_MODE 0xFFF00FFF 156 #define S_00B848_PRIV(x) (((x) & 0x1) << 20) 157 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1) 158 #define C_00B848_PRIV 0xFFEFFFFF 159 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) 160 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) 161 #define C_00B848_DX10_CLAMP 0xFFDFFFFF 162 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) 163 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) 164 #define C_00B848_DEBUG_MODE 0xFFBFFFFF 165 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) 166 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) 167 #define C_00B848_IEEE_MODE 0xFF7FFFFF 168 169 170 // Helpers for setting FLOAT_MODE 171 #define FP_ROUND_ROUND_TO_NEAREST 0 172 #define FP_ROUND_ROUND_TO_INF 1 173 #define FP_ROUND_ROUND_TO_NEGINF 2 174 #define FP_ROUND_ROUND_TO_ZERO 3 175 176 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double 177 // precision. 178 #define FP_ROUND_MODE_SP(x) ((x) & 0x3) 179 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2) 180 181 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0 182 #define FP_DENORM_FLUSH_OUT 1 183 #define FP_DENORM_FLUSH_IN 2 184 #define FP_DENORM_FLUSH_NONE 3 185 186 187 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double 188 // precision. 189 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4) 190 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6) 191 192 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 193 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12) 194 195 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 196 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) 197 198 199 #endif 200