1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 /// \file 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 11 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 12 13 #include "llvm/MC/MCInstrDesc.h" 14 15 namespace llvm { 16 17 // This needs to be kept in sync with the field bits in SIRegisterClass. 18 enum SIRCFlags : uint8_t { 19 // For vector registers. 20 HasVGPR = 1 << 0, 21 HasAGPR = 1 << 1, 22 HasSGPR = 1 << 2 23 }; // enum SIRCFlags 24 25 namespace SIInstrFlags { 26 // This needs to be kept in sync with the field bits in InstSI. 27 enum : uint64_t { 28 // Low bits - basic encoding information. 29 SALU = 1 << 0, 30 VALU = 1 << 1, 31 32 // SALU instruction formats. 33 SOP1 = 1 << 2, 34 SOP2 = 1 << 3, 35 SOPC = 1 << 4, 36 SOPK = 1 << 5, 37 SOPP = 1 << 6, 38 39 // VALU instruction formats. 40 VOP1 = 1 << 7, 41 VOP2 = 1 << 8, 42 VOPC = 1 << 9, 43 44 // TODO: Should this be spilt into VOP3 a and b? 45 VOP3 = 1 << 10, 46 VOP3P = 1 << 12, 47 48 VINTRP = 1 << 13, 49 SDWA = 1 << 14, 50 DPP = 1 << 15, 51 TRANS = 1 << 16, 52 53 // Memory instruction formats. 54 MUBUF = 1 << 17, 55 MTBUF = 1 << 18, 56 SMRD = 1 << 19, 57 MIMG = 1 << 20, 58 EXP = 1 << 21, 59 FLAT = 1 << 22, 60 DS = 1 << 23, 61 62 // Pseudo instruction formats. 63 VGPRSpill = 1 << 24, 64 SGPRSpill = 1 << 25, 65 66 // LDSDIR instruction format. 67 LDSDIR = 1 << 26, 68 69 // VINTERP instruction format. 70 VINTERP = 1 << 27, 71 72 // High bits - other information. 73 VM_CNT = UINT64_C(1) << 32, 74 EXP_CNT = UINT64_C(1) << 33, 75 LGKM_CNT = UINT64_C(1) << 34, 76 77 WQM = UINT64_C(1) << 35, 78 DisableWQM = UINT64_C(1) << 36, 79 Gather4 = UINT64_C(1) << 37, 80 SOPK_ZEXT = UINT64_C(1) << 38, 81 SCALAR_STORE = UINT64_C(1) << 39, 82 FIXED_SIZE = UINT64_C(1) << 40, 83 VOPAsmPrefer32Bit = UINT64_C(1) << 41, 84 VOP3_OPSEL = UINT64_C(1) << 42, 85 maybeAtomic = UINT64_C(1) << 43, 86 renamedInGFX9 = UINT64_C(1) << 44, 87 88 // Is a clamp on FP type. 89 FPClamp = UINT64_C(1) << 45, 90 91 // Is an integer clamp 92 IntClamp = UINT64_C(1) << 46, 93 94 // Clamps lo component of register. 95 ClampLo = UINT64_C(1) << 47, 96 97 // Clamps hi component of register. 98 // ClampLo and ClampHi set for packed clamp. 99 ClampHi = UINT64_C(1) << 48, 100 101 // Is a packed VOP3P instruction. 102 IsPacked = UINT64_C(1) << 49, 103 104 // Is a D16 buffer instruction. 105 D16Buf = UINT64_C(1) << 50, 106 107 // FLAT instruction accesses FLAT_GLBL segment. 108 FlatGlobal = UINT64_C(1) << 51, 109 110 // Uses floating point double precision rounding mode 111 FPDPRounding = UINT64_C(1) << 52, 112 113 // Instruction is FP atomic. 114 FPAtomic = UINT64_C(1) << 53, 115 116 // Is a MFMA instruction. 117 IsMAI = UINT64_C(1) << 54, 118 119 // Is a DOT instruction. 120 IsDOT = UINT64_C(1) << 55, 121 122 // FLAT instruction accesses FLAT_SCRATCH segment. 123 FlatScratch = UINT64_C(1) << 56, 124 125 // Atomic without return. 126 IsAtomicNoRet = UINT64_C(1) << 57, 127 128 // Atomic with return. 129 IsAtomicRet = UINT64_C(1) << 58 130 }; 131 132 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. 133 // The result is true if any of these tests are true. 134 enum ClassFlags : unsigned { 135 S_NAN = 1 << 0, // Signaling NaN 136 Q_NAN = 1 << 1, // Quiet NaN 137 N_INFINITY = 1 << 2, // Negative infinity 138 N_NORMAL = 1 << 3, // Negative normal 139 N_SUBNORMAL = 1 << 4, // Negative subnormal 140 N_ZERO = 1 << 5, // Negative zero 141 P_ZERO = 1 << 6, // Positive zero 142 P_SUBNORMAL = 1 << 7, // Positive subnormal 143 P_NORMAL = 1 << 8, // Positive normal 144 P_INFINITY = 1 << 9 // Positive infinity 145 }; 146 } 147 148 namespace AMDGPU { 149 enum OperandType : unsigned { 150 /// Operands with register or 32-bit immediate 151 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, 152 OPERAND_REG_IMM_INT64, 153 OPERAND_REG_IMM_INT16, 154 OPERAND_REG_IMM_FP32, 155 OPERAND_REG_IMM_FP64, 156 OPERAND_REG_IMM_FP16, 157 OPERAND_REG_IMM_FP16_DEFERRED, 158 OPERAND_REG_IMM_FP32_DEFERRED, 159 OPERAND_REG_IMM_V2FP16, 160 OPERAND_REG_IMM_V2INT16, 161 OPERAND_REG_IMM_V2INT32, 162 OPERAND_REG_IMM_V2FP32, 163 164 /// Operands with register or inline constant 165 OPERAND_REG_INLINE_C_INT16, 166 OPERAND_REG_INLINE_C_INT32, 167 OPERAND_REG_INLINE_C_INT64, 168 OPERAND_REG_INLINE_C_FP16, 169 OPERAND_REG_INLINE_C_FP32, 170 OPERAND_REG_INLINE_C_FP64, 171 OPERAND_REG_INLINE_C_V2INT16, 172 OPERAND_REG_INLINE_C_V2FP16, 173 OPERAND_REG_INLINE_C_V2INT32, 174 OPERAND_REG_INLINE_C_V2FP32, 175 176 /// Operand with 32-bit immediate that uses the constant bus. 177 OPERAND_KIMM32, 178 OPERAND_KIMM16, 179 180 /// Operands with an AccVGPR register or inline constant 181 OPERAND_REG_INLINE_AC_INT16, 182 OPERAND_REG_INLINE_AC_INT32, 183 OPERAND_REG_INLINE_AC_FP16, 184 OPERAND_REG_INLINE_AC_FP32, 185 OPERAND_REG_INLINE_AC_FP64, 186 OPERAND_REG_INLINE_AC_V2INT16, 187 OPERAND_REG_INLINE_AC_V2FP16, 188 OPERAND_REG_INLINE_AC_V2INT32, 189 OPERAND_REG_INLINE_AC_V2FP32, 190 191 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, 192 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32, 193 194 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16, 195 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2FP32, 196 197 OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16, 198 OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2FP32, 199 200 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32, 201 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST, 202 203 // Operand for source modifiers for VOP instructions 204 OPERAND_INPUT_MODS, 205 206 // Operand for SDWA instructions 207 OPERAND_SDWA_VOPC_DST 208 209 }; 210 } 211 212 // Input operand modifiers bit-masks 213 // NEG and SEXT share same bit-mask because they can't be set simultaneously. 214 namespace SISrcMods { 215 enum : unsigned { 216 NEG = 1 << 0, // Floating-point negate modifier 217 ABS = 1 << 1, // Floating-point absolute modifier 218 SEXT = 1 << 0, // Integer sign-extend modifier 219 NEG_HI = ABS, // Floating-point negate high packed component modifier. 220 OP_SEL_0 = 1 << 2, 221 OP_SEL_1 = 1 << 3, 222 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1) 223 }; 224 } 225 226 namespace SIOutMods { 227 enum : unsigned { 228 NONE = 0, 229 MUL2 = 1, 230 MUL4 = 2, 231 DIV2 = 3 232 }; 233 } 234 235 namespace AMDGPU { 236 namespace VGPRIndexMode { 237 238 enum Id : unsigned { // id of symbolic names 239 ID_SRC0 = 0, 240 ID_SRC1, 241 ID_SRC2, 242 ID_DST, 243 244 ID_MIN = ID_SRC0, 245 ID_MAX = ID_DST 246 }; 247 248 enum EncBits : unsigned { 249 OFF = 0, 250 SRC0_ENABLE = 1 << ID_SRC0, 251 SRC1_ENABLE = 1 << ID_SRC1, 252 SRC2_ENABLE = 1 << ID_SRC2, 253 DST_ENABLE = 1 << ID_DST, 254 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE, 255 UNDEF = 0xFFFF 256 }; 257 258 } // namespace VGPRIndexMode 259 } // namespace AMDGPU 260 261 namespace AMDGPUAsmVariants { 262 enum : unsigned { 263 DEFAULT = 0, 264 VOP3 = 1, 265 SDWA = 2, 266 SDWA9 = 3, 267 DPP = 4, 268 VOP3_DPP = 5 269 }; 270 } // namespace AMDGPUAsmVariants 271 272 namespace AMDGPU { 273 namespace EncValues { // Encoding values of enum9/8/7 operands 274 275 enum : unsigned { 276 SGPR_MIN = 0, 277 SGPR_MAX_SI = 101, 278 SGPR_MAX_GFX10 = 105, 279 TTMP_VI_MIN = 112, 280 TTMP_VI_MAX = 123, 281 TTMP_GFX9PLUS_MIN = 108, 282 TTMP_GFX9PLUS_MAX = 123, 283 INLINE_INTEGER_C_MIN = 128, 284 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64 285 INLINE_INTEGER_C_MAX = 208, 286 INLINE_FLOATING_C_MIN = 240, 287 INLINE_FLOATING_C_MAX = 248, 288 LITERAL_CONST = 255, 289 VGPR_MIN = 256, 290 VGPR_MAX = 511, 291 IS_VGPR = 256 // Indicates VGPR or AGPR 292 }; 293 294 } // namespace EncValues 295 } // namespace AMDGPU 296 297 namespace AMDGPU { 298 namespace CPol { 299 300 enum CPol { 301 GLC = 1, 302 SLC = 2, 303 DLC = 4, 304 SCC = 16, 305 SC0 = GLC, 306 SC1 = SCC, 307 NT = SLC, 308 ALL = GLC | SLC | DLC | SCC 309 }; 310 311 } // namespace CPol 312 313 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns. 314 315 enum Id { // Message ID, width(4) [3:0]. 316 ID_INTERRUPT = 1, 317 318 ID_GS_PreGFX11 = 2, // replaced in GFX11 319 ID_GS_DONE_PreGFX11 = 3, // replaced in GFX11 320 321 ID_HS_TESSFACTOR_GFX11Plus = 2, // reused in GFX11 322 ID_DEALLOC_VGPRS_GFX11Plus = 3, // reused in GFX11 323 324 ID_SAVEWAVE = 4, // added in GFX8, removed in GFX11 325 ID_STALL_WAVE_GEN = 5, // added in GFX9 326 ID_HALT_WAVES = 6, // added in GFX9 327 ID_ORDERED_PS_DONE = 7, // added in GFX9 328 ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10 329 ID_GS_ALLOC_REQ = 9, // added in GFX9 330 ID_GET_DOORBELL = 10, // added in GFX9, removed in GFX11 331 ID_GET_DDID = 11, // added in GFX10, removed in GFX11 332 ID_SYSMSG = 15, 333 334 ID_RTN_GET_DOORBELL = 128, 335 ID_RTN_GET_DDID = 129, 336 ID_RTN_GET_TMA = 130, 337 ID_RTN_GET_REALTIME = 131, 338 ID_RTN_SAVE_WAVE = 132, 339 ID_RTN_GET_TBA = 133, 340 341 ID_MASK_PreGFX11_ = 0xF, 342 ID_MASK_GFX11Plus_ = 0xFF 343 }; 344 345 enum Op { // Both GS and SYS operation IDs. 346 OP_UNKNOWN_ = -1, 347 OP_SHIFT_ = 4, 348 OP_NONE_ = 0, 349 // Bits used for operation encoding 350 OP_WIDTH_ = 3, 351 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_), 352 // GS operations are encoded in bits 5:4 353 OP_GS_NOP = 0, 354 OP_GS_CUT = 1, 355 OP_GS_EMIT = 2, 356 OP_GS_EMIT_CUT = 3, 357 OP_GS_LAST_, 358 OP_GS_FIRST_ = OP_GS_NOP, 359 // SYS operations are encoded in bits 6:4 360 OP_SYS_ECC_ERR_INTERRUPT = 1, 361 OP_SYS_REG_RD = 2, 362 OP_SYS_HOST_TRAP_ACK = 3, 363 OP_SYS_TTRACE_PC = 4, 364 OP_SYS_LAST_, 365 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT, 366 }; 367 368 enum StreamId : unsigned { // Stream ID, (2) [9:8]. 369 STREAM_ID_NONE_ = 0, 370 STREAM_ID_DEFAULT_ = 0, 371 STREAM_ID_LAST_ = 4, 372 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_, 373 STREAM_ID_SHIFT_ = 8, 374 STREAM_ID_WIDTH_= 2, 375 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_) 376 }; 377 378 } // namespace SendMsg 379 380 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns. 381 382 enum Id { // HwRegCode, (6) [5:0] 383 ID_MODE = 1, 384 ID_STATUS = 2, 385 ID_TRAPSTS = 3, 386 ID_HW_ID = 4, 387 ID_GPR_ALLOC = 5, 388 ID_LDS_ALLOC = 6, 389 ID_IB_STS = 7, 390 ID_MEM_BASES = 15, 391 ID_TBA_LO = 16, 392 ID_TBA_HI = 17, 393 ID_TMA_LO = 18, 394 ID_TMA_HI = 19, 395 ID_XCC_ID = 20, 396 ID_SQ_PERF_SNAPSHOT_DATA = 21, 397 ID_SQ_PERF_SNAPSHOT_DATA1 = 22, 398 ID_SQ_PERF_SNAPSHOT_PC_LO = 23, 399 ID_SQ_PERF_SNAPSHOT_PC_HI = 24, 400 ID_FLAT_SCR_LO = 20, 401 ID_FLAT_SCR_HI = 21, 402 ID_XNACK_MASK = 22, 403 ID_HW_ID1 = 23, 404 ID_HW_ID2 = 24, 405 ID_POPS_PACKER = 25, 406 ID_SHADER_CYCLES = 29, 407 408 ID_SHIFT_ = 0, 409 ID_WIDTH_ = 6, 410 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 411 }; 412 413 enum Offset : unsigned { // Offset, (5) [10:6] 414 OFFSET_DEFAULT_ = 0, 415 OFFSET_SHIFT_ = 6, 416 OFFSET_WIDTH_ = 5, 417 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_), 418 419 OFFSET_MEM_VIOL = 8, 420 421 OFFSET_SRC_SHARED_BASE = 16, 422 OFFSET_SRC_PRIVATE_BASE = 0 423 }; 424 425 enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11] 426 WIDTH_M1_DEFAULT_ = 31, 427 WIDTH_M1_SHIFT_ = 11, 428 WIDTH_M1_WIDTH_ = 5, 429 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_), 430 431 WIDTH_M1_SRC_SHARED_BASE = 15, 432 WIDTH_M1_SRC_PRIVATE_BASE = 15 433 }; 434 435 // Some values from WidthMinusOne mapped into Width domain. 436 enum Width : unsigned { 437 WIDTH_DEFAULT_ = WIDTH_M1_DEFAULT_ + 1, 438 }; 439 440 enum ModeRegisterMasks : uint32_t { 441 FP_ROUND_MASK = 0xf << 0, // Bits 0..3 442 FP_DENORM_MASK = 0xf << 4, // Bits 4..7 443 DX10_CLAMP_MASK = 1 << 8, 444 IEEE_MODE_MASK = 1 << 9, 445 LOD_CLAMP_MASK = 1 << 10, 446 DEBUG_MASK = 1 << 11, 447 448 // EXCP_EN fields. 449 EXCP_EN_INVALID_MASK = 1 << 12, 450 EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13, 451 EXCP_EN_FLOAT_DIV0_MASK = 1 << 14, 452 EXCP_EN_OVERFLOW_MASK = 1 << 15, 453 EXCP_EN_UNDERFLOW_MASK = 1 << 16, 454 EXCP_EN_INEXACT_MASK = 1 << 17, 455 EXCP_EN_INT_DIV0_MASK = 1 << 18, 456 457 GPR_IDX_EN_MASK = 1 << 27, 458 VSKIP_MASK = 1 << 28, 459 CSP_MASK = 0x7u << 29 // Bits 29..31 460 }; 461 462 } // namespace Hwreg 463 464 namespace MTBUFFormat { 465 466 enum DataFormat : int64_t { 467 DFMT_INVALID = 0, 468 DFMT_8, 469 DFMT_16, 470 DFMT_8_8, 471 DFMT_32, 472 DFMT_16_16, 473 DFMT_10_11_11, 474 DFMT_11_11_10, 475 DFMT_10_10_10_2, 476 DFMT_2_10_10_10, 477 DFMT_8_8_8_8, 478 DFMT_32_32, 479 DFMT_16_16_16_16, 480 DFMT_32_32_32, 481 DFMT_32_32_32_32, 482 DFMT_RESERVED_15, 483 484 DFMT_MIN = DFMT_INVALID, 485 DFMT_MAX = DFMT_RESERVED_15, 486 487 DFMT_UNDEF = -1, 488 DFMT_DEFAULT = DFMT_8, 489 490 DFMT_SHIFT = 0, 491 DFMT_MASK = 0xF 492 }; 493 494 enum NumFormat : int64_t { 495 NFMT_UNORM = 0, 496 NFMT_SNORM, 497 NFMT_USCALED, 498 NFMT_SSCALED, 499 NFMT_UINT, 500 NFMT_SINT, 501 NFMT_RESERVED_6, // VI and GFX9 502 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only 503 NFMT_FLOAT, 504 505 NFMT_MIN = NFMT_UNORM, 506 NFMT_MAX = NFMT_FLOAT, 507 508 NFMT_UNDEF = -1, 509 NFMT_DEFAULT = NFMT_UNORM, 510 511 NFMT_SHIFT = 4, 512 NFMT_MASK = 7 513 }; 514 515 enum MergedFormat : int64_t { 516 DFMT_NFMT_UNDEF = -1, 517 DFMT_NFMT_DEFAULT = ((DFMT_DEFAULT & DFMT_MASK) << DFMT_SHIFT) | 518 ((NFMT_DEFAULT & NFMT_MASK) << NFMT_SHIFT), 519 520 521 DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT), 522 523 DFMT_NFMT_MAX = DFMT_NFMT_MASK 524 }; 525 526 enum UnifiedFormatCommon : int64_t { 527 UFMT_MAX = 127, 528 UFMT_UNDEF = -1, 529 UFMT_DEFAULT = 1 530 }; 531 532 } // namespace MTBUFFormat 533 534 namespace UfmtGFX10 { 535 enum UnifiedFormat : int64_t { 536 UFMT_INVALID = 0, 537 538 UFMT_8_UNORM, 539 UFMT_8_SNORM, 540 UFMT_8_USCALED, 541 UFMT_8_SSCALED, 542 UFMT_8_UINT, 543 UFMT_8_SINT, 544 545 UFMT_16_UNORM, 546 UFMT_16_SNORM, 547 UFMT_16_USCALED, 548 UFMT_16_SSCALED, 549 UFMT_16_UINT, 550 UFMT_16_SINT, 551 UFMT_16_FLOAT, 552 553 UFMT_8_8_UNORM, 554 UFMT_8_8_SNORM, 555 UFMT_8_8_USCALED, 556 UFMT_8_8_SSCALED, 557 UFMT_8_8_UINT, 558 UFMT_8_8_SINT, 559 560 UFMT_32_UINT, 561 UFMT_32_SINT, 562 UFMT_32_FLOAT, 563 564 UFMT_16_16_UNORM, 565 UFMT_16_16_SNORM, 566 UFMT_16_16_USCALED, 567 UFMT_16_16_SSCALED, 568 UFMT_16_16_UINT, 569 UFMT_16_16_SINT, 570 UFMT_16_16_FLOAT, 571 572 UFMT_10_11_11_UNORM, 573 UFMT_10_11_11_SNORM, 574 UFMT_10_11_11_USCALED, 575 UFMT_10_11_11_SSCALED, 576 UFMT_10_11_11_UINT, 577 UFMT_10_11_11_SINT, 578 UFMT_10_11_11_FLOAT, 579 580 UFMT_11_11_10_UNORM, 581 UFMT_11_11_10_SNORM, 582 UFMT_11_11_10_USCALED, 583 UFMT_11_11_10_SSCALED, 584 UFMT_11_11_10_UINT, 585 UFMT_11_11_10_SINT, 586 UFMT_11_11_10_FLOAT, 587 588 UFMT_10_10_10_2_UNORM, 589 UFMT_10_10_10_2_SNORM, 590 UFMT_10_10_10_2_USCALED, 591 UFMT_10_10_10_2_SSCALED, 592 UFMT_10_10_10_2_UINT, 593 UFMT_10_10_10_2_SINT, 594 595 UFMT_2_10_10_10_UNORM, 596 UFMT_2_10_10_10_SNORM, 597 UFMT_2_10_10_10_USCALED, 598 UFMT_2_10_10_10_SSCALED, 599 UFMT_2_10_10_10_UINT, 600 UFMT_2_10_10_10_SINT, 601 602 UFMT_8_8_8_8_UNORM, 603 UFMT_8_8_8_8_SNORM, 604 UFMT_8_8_8_8_USCALED, 605 UFMT_8_8_8_8_SSCALED, 606 UFMT_8_8_8_8_UINT, 607 UFMT_8_8_8_8_SINT, 608 609 UFMT_32_32_UINT, 610 UFMT_32_32_SINT, 611 UFMT_32_32_FLOAT, 612 613 UFMT_16_16_16_16_UNORM, 614 UFMT_16_16_16_16_SNORM, 615 UFMT_16_16_16_16_USCALED, 616 UFMT_16_16_16_16_SSCALED, 617 UFMT_16_16_16_16_UINT, 618 UFMT_16_16_16_16_SINT, 619 UFMT_16_16_16_16_FLOAT, 620 621 UFMT_32_32_32_UINT, 622 UFMT_32_32_32_SINT, 623 UFMT_32_32_32_FLOAT, 624 UFMT_32_32_32_32_UINT, 625 UFMT_32_32_32_32_SINT, 626 UFMT_32_32_32_32_FLOAT, 627 628 UFMT_FIRST = UFMT_INVALID, 629 UFMT_LAST = UFMT_32_32_32_32_FLOAT, 630 }; 631 632 } // namespace UfmtGFX10 633 634 namespace UfmtGFX11 { 635 enum UnifiedFormat : int64_t { 636 UFMT_INVALID = 0, 637 638 UFMT_8_UNORM, 639 UFMT_8_SNORM, 640 UFMT_8_USCALED, 641 UFMT_8_SSCALED, 642 UFMT_8_UINT, 643 UFMT_8_SINT, 644 645 UFMT_16_UNORM, 646 UFMT_16_SNORM, 647 UFMT_16_USCALED, 648 UFMT_16_SSCALED, 649 UFMT_16_UINT, 650 UFMT_16_SINT, 651 UFMT_16_FLOAT, 652 653 UFMT_8_8_UNORM, 654 UFMT_8_8_SNORM, 655 UFMT_8_8_USCALED, 656 UFMT_8_8_SSCALED, 657 UFMT_8_8_UINT, 658 UFMT_8_8_SINT, 659 660 UFMT_32_UINT, 661 UFMT_32_SINT, 662 UFMT_32_FLOAT, 663 664 UFMT_16_16_UNORM, 665 UFMT_16_16_SNORM, 666 UFMT_16_16_USCALED, 667 UFMT_16_16_SSCALED, 668 UFMT_16_16_UINT, 669 UFMT_16_16_SINT, 670 UFMT_16_16_FLOAT, 671 672 UFMT_10_11_11_FLOAT, 673 674 UFMT_11_11_10_FLOAT, 675 676 UFMT_10_10_10_2_UNORM, 677 UFMT_10_10_10_2_SNORM, 678 UFMT_10_10_10_2_UINT, 679 UFMT_10_10_10_2_SINT, 680 681 UFMT_2_10_10_10_UNORM, 682 UFMT_2_10_10_10_SNORM, 683 UFMT_2_10_10_10_USCALED, 684 UFMT_2_10_10_10_SSCALED, 685 UFMT_2_10_10_10_UINT, 686 UFMT_2_10_10_10_SINT, 687 688 UFMT_8_8_8_8_UNORM, 689 UFMT_8_8_8_8_SNORM, 690 UFMT_8_8_8_8_USCALED, 691 UFMT_8_8_8_8_SSCALED, 692 UFMT_8_8_8_8_UINT, 693 UFMT_8_8_8_8_SINT, 694 695 UFMT_32_32_UINT, 696 UFMT_32_32_SINT, 697 UFMT_32_32_FLOAT, 698 699 UFMT_16_16_16_16_UNORM, 700 UFMT_16_16_16_16_SNORM, 701 UFMT_16_16_16_16_USCALED, 702 UFMT_16_16_16_16_SSCALED, 703 UFMT_16_16_16_16_UINT, 704 UFMT_16_16_16_16_SINT, 705 UFMT_16_16_16_16_FLOAT, 706 707 UFMT_32_32_32_UINT, 708 UFMT_32_32_32_SINT, 709 UFMT_32_32_32_FLOAT, 710 UFMT_32_32_32_32_UINT, 711 UFMT_32_32_32_32_SINT, 712 UFMT_32_32_32_32_FLOAT, 713 714 UFMT_FIRST = UFMT_INVALID, 715 UFMT_LAST = UFMT_32_32_32_32_FLOAT, 716 }; 717 718 } // namespace UfmtGFX11 719 720 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32. 721 722 enum Id : unsigned { // id of symbolic names 723 ID_QUAD_PERM = 0, 724 ID_BITMASK_PERM, 725 ID_SWAP, 726 ID_REVERSE, 727 ID_BROADCAST 728 }; 729 730 enum EncBits : unsigned { 731 732 // swizzle mode encodings 733 734 QUAD_PERM_ENC = 0x8000, 735 QUAD_PERM_ENC_MASK = 0xFF00, 736 737 BITMASK_PERM_ENC = 0x0000, 738 BITMASK_PERM_ENC_MASK = 0x8000, 739 740 // QUAD_PERM encodings 741 742 LANE_MASK = 0x3, 743 LANE_MAX = LANE_MASK, 744 LANE_SHIFT = 2, 745 LANE_NUM = 4, 746 747 // BITMASK_PERM encodings 748 749 BITMASK_MASK = 0x1F, 750 BITMASK_MAX = BITMASK_MASK, 751 BITMASK_WIDTH = 5, 752 753 BITMASK_AND_SHIFT = 0, 754 BITMASK_OR_SHIFT = 5, 755 BITMASK_XOR_SHIFT = 10 756 }; 757 758 } // namespace Swizzle 759 760 namespace SDWA { 761 762 enum SdwaSel : unsigned { 763 BYTE_0 = 0, 764 BYTE_1 = 1, 765 BYTE_2 = 2, 766 BYTE_3 = 3, 767 WORD_0 = 4, 768 WORD_1 = 5, 769 DWORD = 6, 770 }; 771 772 enum DstUnused : unsigned { 773 UNUSED_PAD = 0, 774 UNUSED_SEXT = 1, 775 UNUSED_PRESERVE = 2, 776 }; 777 778 enum SDWA9EncValues : unsigned { 779 SRC_SGPR_MASK = 0x100, 780 SRC_VGPR_MASK = 0xFF, 781 VOPC_DST_VCC_MASK = 0x80, 782 VOPC_DST_SGPR_MASK = 0x7F, 783 784 SRC_VGPR_MIN = 0, 785 SRC_VGPR_MAX = 255, 786 SRC_SGPR_MIN = 256, 787 SRC_SGPR_MAX_SI = 357, 788 SRC_SGPR_MAX_GFX10 = 361, 789 SRC_TTMP_MIN = 364, 790 SRC_TTMP_MAX = 379, 791 }; 792 793 } // namespace SDWA 794 795 namespace DPP { 796 797 // clang-format off 798 enum DppCtrl : unsigned { 799 QUAD_PERM_FIRST = 0, 800 QUAD_PERM_ID = 0xE4, // identity permutation 801 QUAD_PERM_LAST = 0xFF, 802 DPP_UNUSED1 = 0x100, 803 ROW_SHL0 = 0x100, 804 ROW_SHL_FIRST = 0x101, 805 ROW_SHL_LAST = 0x10F, 806 DPP_UNUSED2 = 0x110, 807 ROW_SHR0 = 0x110, 808 ROW_SHR_FIRST = 0x111, 809 ROW_SHR_LAST = 0x11F, 810 DPP_UNUSED3 = 0x120, 811 ROW_ROR0 = 0x120, 812 ROW_ROR_FIRST = 0x121, 813 ROW_ROR_LAST = 0x12F, 814 WAVE_SHL1 = 0x130, 815 DPP_UNUSED4_FIRST = 0x131, 816 DPP_UNUSED4_LAST = 0x133, 817 WAVE_ROL1 = 0x134, 818 DPP_UNUSED5_FIRST = 0x135, 819 DPP_UNUSED5_LAST = 0x137, 820 WAVE_SHR1 = 0x138, 821 DPP_UNUSED6_FIRST = 0x139, 822 DPP_UNUSED6_LAST = 0x13B, 823 WAVE_ROR1 = 0x13C, 824 DPP_UNUSED7_FIRST = 0x13D, 825 DPP_UNUSED7_LAST = 0x13F, 826 ROW_MIRROR = 0x140, 827 ROW_HALF_MIRROR = 0x141, 828 BCAST15 = 0x142, 829 BCAST31 = 0x143, 830 DPP_UNUSED8_FIRST = 0x144, 831 DPP_UNUSED8_LAST = 0x14F, 832 ROW_NEWBCAST_FIRST= 0x150, 833 ROW_NEWBCAST_LAST = 0x15F, 834 ROW_SHARE0 = 0x150, 835 ROW_SHARE_FIRST = 0x150, 836 ROW_SHARE_LAST = 0x15F, 837 ROW_XMASK0 = 0x160, 838 ROW_XMASK_FIRST = 0x160, 839 ROW_XMASK_LAST = 0x16F, 840 DPP_LAST = ROW_XMASK_LAST 841 }; 842 // clang-format on 843 844 enum DppFiMode { 845 DPP_FI_0 = 0, 846 DPP_FI_1 = 1, 847 DPP8_FI_0 = 0xE9, 848 DPP8_FI_1 = 0xEA, 849 }; 850 851 } // namespace DPP 852 853 namespace Exp { 854 855 enum Target : unsigned { 856 ET_MRT0 = 0, 857 ET_MRT7 = 7, 858 ET_MRTZ = 8, 859 ET_NULL = 9, // Pre-GFX11 860 ET_POS0 = 12, 861 ET_POS3 = 15, 862 ET_POS4 = 16, // GFX10+ 863 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget 864 ET_PRIM = 20, // GFX10+ 865 ET_DUAL_SRC_BLEND0 = 21, // GFX11+ 866 ET_DUAL_SRC_BLEND1 = 22, // GFX11+ 867 ET_PARAM0 = 32, // Pre-GFX11 868 ET_PARAM31 = 63, // Pre-GFX11 869 870 ET_NULL_MAX_IDX = 0, 871 ET_MRTZ_MAX_IDX = 0, 872 ET_PRIM_MAX_IDX = 0, 873 ET_MRT_MAX_IDX = 7, 874 ET_POS_MAX_IDX = 4, 875 ET_DUAL_SRC_BLEND_MAX_IDX = 1, 876 ET_PARAM_MAX_IDX = 31, 877 878 ET_INVALID = 255, 879 }; 880 881 } // namespace Exp 882 883 namespace VOP3PEncoding { 884 885 enum OpSel : uint64_t { 886 OP_SEL_HI_0 = UINT64_C(1) << 59, 887 OP_SEL_HI_1 = UINT64_C(1) << 60, 888 OP_SEL_HI_2 = UINT64_C(1) << 14, 889 }; 890 891 } // namespace VOP3PEncoding 892 893 namespace ImplicitArg { 894 // Implicit kernel argument offset for code object version 5. 895 enum Offset_COV5 : unsigned { 896 HOSTCALL_PTR_OFFSET = 80, 897 MULTIGRID_SYNC_ARG_OFFSET = 88, 898 HEAP_PTR_OFFSET = 96, 899 PRIVATE_BASE_OFFSET = 192, 900 SHARED_BASE_OFFSET = 196, 901 QUEUE_PTR_OFFSET = 200, 902 }; 903 904 } // namespace ImplicitArg 905 } // namespace AMDGPU 906 907 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 908 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) 909 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) 910 #define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25) 911 #define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1) 912 #define C_00B028_MEM_ORDERED 0xFDFFFFFF 913 914 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C 915 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) 916 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 917 #define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27) 918 #define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1) 919 #define C_00B128_MEM_ORDERED 0xF7FFFFFF 920 921 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 922 #define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27) 923 #define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1) 924 #define C_00B228_WGP_MODE 0xF7FFFFFF 925 #define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25) 926 #define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1) 927 #define C_00B228_MEM_ORDERED 0xFDFFFFFF 928 929 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328 930 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428 931 #define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26) 932 #define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1) 933 #define C_00B428_WGP_MODE 0xFBFFFFFF 934 #define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24) 935 #define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1) 936 #define C_00B428_MEM_ORDERED 0xFEFFFFFF 937 938 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528 939 940 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C 941 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) 942 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 943 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE 944 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) 945 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) 946 #define C_00B84C_USER_SGPR 0xFFFFFFC1 947 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6) 948 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1) 949 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF 950 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) 951 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) 952 #define C_00B84C_TGID_X_EN 0xFFFFFF7F 953 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) 954 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) 955 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF 956 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) 957 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) 958 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF 959 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) 960 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) 961 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF 962 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) 963 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) 964 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF 965 /* CIK */ 966 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) 967 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) 968 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF 969 /* */ 970 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) 971 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) 972 #define C_00B84C_LDS_SIZE 0xFF007FFF 973 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) 974 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) 975 #define C_00B84C_EXCP_EN 976 977 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC 978 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 979 980 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 981 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) 982 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) 983 #define C_00B848_VGPRS 0xFFFFFFC0 984 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) 985 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) 986 #define C_00B848_SGPRS 0xFFFFFC3F 987 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) 988 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) 989 #define C_00B848_PRIORITY 0xFFFFF3FF 990 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) 991 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 992 #define C_00B848_FLOAT_MODE 0xFFF00FFF 993 #define S_00B848_PRIV(x) (((x) & 0x1) << 20) 994 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1) 995 #define C_00B848_PRIV 0xFFEFFFFF 996 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) 997 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) 998 #define C_00B848_DX10_CLAMP 0xFFDFFFFF 999 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) 1000 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) 1001 #define C_00B848_DEBUG_MODE 0xFFBFFFFF 1002 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) 1003 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) 1004 #define C_00B848_IEEE_MODE 0xFF7FFFFF 1005 #define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29) 1006 #define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1) 1007 #define C_00B848_WGP_MODE 0xDFFFFFFF 1008 #define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30) 1009 #define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1) 1010 #define C_00B848_MEM_ORDERED 0xBFFFFFFF 1011 #define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31) 1012 #define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1) 1013 #define C_00B848_FWD_PROGRESS 0x7FFFFFFF 1014 1015 1016 // Helpers for setting FLOAT_MODE 1017 #define FP_ROUND_ROUND_TO_NEAREST 0 1018 #define FP_ROUND_ROUND_TO_INF 1 1019 #define FP_ROUND_ROUND_TO_NEGINF 2 1020 #define FP_ROUND_ROUND_TO_ZERO 3 1021 1022 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double 1023 // precision. 1024 #define FP_ROUND_MODE_SP(x) ((x) & 0x3) 1025 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2) 1026 1027 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0 1028 #define FP_DENORM_FLUSH_OUT 1 1029 #define FP_DENORM_FLUSH_IN 2 1030 #define FP_DENORM_FLUSH_NONE 3 1031 1032 1033 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double 1034 // precision. 1035 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4) 1036 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6) 1037 1038 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 1039 #define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12) 1040 #define S_00B860_WAVESIZE_GFX11Plus(x) (((x) & 0x7FFF) << 12) 1041 1042 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 1043 #define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12) 1044 #define S_0286E8_WAVESIZE_GFX11Plus(x) (((x) & 0x7FFF) << 12) 1045 1046 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54 1047 #define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21) 1048 #define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22) 1049 #define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23) 1050 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8 1051 #define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15) 1052 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800 1053 #define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15) 1054 1055 #define R_SPILLED_SGPRS 0x4 1056 #define R_SPILLED_VGPRS 0x8 1057 } // End namespace llvm 1058 1059 #endif 1060