1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 /// \file 8 //===----------------------------------------------------------------------===// 9 10 #include "llvm/MC/MCInstrDesc.h" 11 12 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 13 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 14 15 namespace llvm { 16 17 namespace SIInstrFlags { 18 // This needs to be kept in sync with the field bits in InstSI. 19 enum : uint64_t { 20 // Low bits - basic encoding information. 21 SALU = 1 << 0, 22 VALU = 1 << 1, 23 24 // SALU instruction formats. 25 SOP1 = 1 << 2, 26 SOP2 = 1 << 3, 27 SOPC = 1 << 4, 28 SOPK = 1 << 5, 29 SOPP = 1 << 6, 30 31 // VALU instruction formats. 32 VOP1 = 1 << 7, 33 VOP2 = 1 << 8, 34 VOPC = 1 << 9, 35 36 // TODO: Should this be spilt into VOP3 a and b? 37 VOP3 = 1 << 10, 38 VOP3P = 1 << 12, 39 40 VINTRP = 1 << 13, 41 SDWA = 1 << 14, 42 DPP = 1 << 15, 43 TRANS = 1 << 16, 44 45 // Memory instruction formats. 46 MUBUF = 1 << 17, 47 MTBUF = 1 << 18, 48 SMRD = 1 << 19, 49 MIMG = 1 << 20, 50 EXP = 1 << 21, 51 FLAT = 1 << 22, 52 DS = 1 << 23, 53 54 // Pseudo instruction formats. 55 VGPRSpill = 1 << 24, 56 SGPRSpill = 1 << 25, 57 58 // High bits - other information. 59 VM_CNT = UINT64_C(1) << 32, 60 EXP_CNT = UINT64_C(1) << 33, 61 LGKM_CNT = UINT64_C(1) << 34, 62 63 WQM = UINT64_C(1) << 35, 64 DisableWQM = UINT64_C(1) << 36, 65 Gather4 = UINT64_C(1) << 37, 66 SOPK_ZEXT = UINT64_C(1) << 38, 67 SCALAR_STORE = UINT64_C(1) << 39, 68 FIXED_SIZE = UINT64_C(1) << 40, 69 VOPAsmPrefer32Bit = UINT64_C(1) << 41, 70 VOP3_OPSEL = UINT64_C(1) << 42, 71 maybeAtomic = UINT64_C(1) << 43, 72 renamedInGFX9 = UINT64_C(1) << 44, 73 74 // Is a clamp on FP type. 75 FPClamp = UINT64_C(1) << 45, 76 77 // Is an integer clamp 78 IntClamp = UINT64_C(1) << 46, 79 80 // Clamps lo component of register. 81 ClampLo = UINT64_C(1) << 47, 82 83 // Clamps hi component of register. 84 // ClampLo and ClampHi set for packed clamp. 85 ClampHi = UINT64_C(1) << 48, 86 87 // Is a packed VOP3P instruction. 88 IsPacked = UINT64_C(1) << 49, 89 90 // Is a D16 buffer instruction. 91 D16Buf = UINT64_C(1) << 50, 92 93 // FLAT instruction accesses FLAT_GLBL segment. 94 IsFlatGlobal = UINT64_C(1) << 51, 95 96 // Uses floating point double precision rounding mode 97 FPDPRounding = UINT64_C(1) << 52, 98 99 // Instruction is FP atomic. 100 FPAtomic = UINT64_C(1) << 53, 101 102 // Is a MFMA instruction. 103 IsMAI = UINT64_C(1) << 54, 104 105 // Is a DOT instruction. 106 IsDOT = UINT64_C(1) << 55, 107 108 // FLAT instruction accesses FLAT_SCRATCH segment. 109 IsFlatScratch = UINT64_C(1) << 56, 110 111 // Atomic without return. 112 IsAtomicNoRet = UINT64_C(1) << 57, 113 114 // Atomic with return. 115 IsAtomicRet = UINT64_C(1) << 58 116 }; 117 118 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. 119 // The result is true if any of these tests are true. 120 enum ClassFlags : unsigned { 121 S_NAN = 1 << 0, // Signaling NaN 122 Q_NAN = 1 << 1, // Quiet NaN 123 N_INFINITY = 1 << 2, // Negative infinity 124 N_NORMAL = 1 << 3, // Negative normal 125 N_SUBNORMAL = 1 << 4, // Negative subnormal 126 N_ZERO = 1 << 5, // Negative zero 127 P_ZERO = 1 << 6, // Positive zero 128 P_SUBNORMAL = 1 << 7, // Positive subnormal 129 P_NORMAL = 1 << 8, // Positive normal 130 P_INFINITY = 1 << 9 // Positive infinity 131 }; 132 } 133 134 namespace AMDGPU { 135 enum OperandType : unsigned { 136 /// Operands with register or 32-bit immediate 137 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, 138 OPERAND_REG_IMM_INT64, 139 OPERAND_REG_IMM_INT16, 140 OPERAND_REG_IMM_FP32, 141 OPERAND_REG_IMM_FP64, 142 OPERAND_REG_IMM_FP16, 143 OPERAND_REG_IMM_V2FP16, 144 OPERAND_REG_IMM_V2INT16, 145 OPERAND_REG_IMM_V2INT32, 146 OPERAND_REG_IMM_V2FP32, 147 148 /// Operands with register or inline constant 149 OPERAND_REG_INLINE_C_INT16, 150 OPERAND_REG_INLINE_C_INT32, 151 OPERAND_REG_INLINE_C_INT64, 152 OPERAND_REG_INLINE_C_FP16, 153 OPERAND_REG_INLINE_C_FP32, 154 OPERAND_REG_INLINE_C_FP64, 155 OPERAND_REG_INLINE_C_V2INT16, 156 OPERAND_REG_INLINE_C_V2FP16, 157 OPERAND_REG_INLINE_C_V2INT32, 158 OPERAND_REG_INLINE_C_V2FP32, 159 160 /// Operands with an AccVGPR register or inline constant 161 OPERAND_REG_INLINE_AC_INT16, 162 OPERAND_REG_INLINE_AC_INT32, 163 OPERAND_REG_INLINE_AC_FP16, 164 OPERAND_REG_INLINE_AC_FP32, 165 OPERAND_REG_INLINE_AC_FP64, 166 OPERAND_REG_INLINE_AC_V2INT16, 167 OPERAND_REG_INLINE_AC_V2FP16, 168 OPERAND_REG_INLINE_AC_V2INT32, 169 OPERAND_REG_INLINE_AC_V2FP32, 170 171 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, 172 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32, 173 174 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16, 175 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2FP32, 176 177 OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16, 178 OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2FP32, 179 180 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32, 181 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST, 182 183 // Operand for source modifiers for VOP instructions 184 OPERAND_INPUT_MODS, 185 186 // Operand for SDWA instructions 187 OPERAND_SDWA_VOPC_DST, 188 189 /// Operand with 32-bit immediate that uses the constant bus. 190 OPERAND_KIMM32, 191 OPERAND_KIMM16 192 }; 193 } 194 195 // Input operand modifiers bit-masks 196 // NEG and SEXT share same bit-mask because they can't be set simultaneously. 197 namespace SISrcMods { 198 enum : unsigned { 199 NEG = 1 << 0, // Floating-point negate modifier 200 ABS = 1 << 1, // Floating-point absolute modifier 201 SEXT = 1 << 0, // Integer sign-extend modifier 202 NEG_HI = ABS, // Floating-point negate high packed component modifier. 203 OP_SEL_0 = 1 << 2, 204 OP_SEL_1 = 1 << 3, 205 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1) 206 }; 207 } 208 209 namespace SIOutMods { 210 enum : unsigned { 211 NONE = 0, 212 MUL2 = 1, 213 MUL4 = 2, 214 DIV2 = 3 215 }; 216 } 217 218 namespace AMDGPU { 219 namespace VGPRIndexMode { 220 221 enum Id : unsigned { // id of symbolic names 222 ID_SRC0 = 0, 223 ID_SRC1, 224 ID_SRC2, 225 ID_DST, 226 227 ID_MIN = ID_SRC0, 228 ID_MAX = ID_DST 229 }; 230 231 enum EncBits : unsigned { 232 OFF = 0, 233 SRC0_ENABLE = 1 << ID_SRC0, 234 SRC1_ENABLE = 1 << ID_SRC1, 235 SRC2_ENABLE = 1 << ID_SRC2, 236 DST_ENABLE = 1 << ID_DST, 237 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE, 238 UNDEF = 0xFFFF 239 }; 240 241 } // namespace VGPRIndexMode 242 } // namespace AMDGPU 243 244 namespace AMDGPUAsmVariants { 245 enum : unsigned { 246 DEFAULT = 0, 247 VOP3 = 1, 248 SDWA = 2, 249 SDWA9 = 3, 250 DPP = 4 251 }; 252 } 253 254 namespace AMDGPU { 255 namespace EncValues { // Encoding values of enum9/8/7 operands 256 257 enum : unsigned { 258 SGPR_MIN = 0, 259 SGPR_MAX_SI = 101, 260 SGPR_MAX_GFX10 = 105, 261 TTMP_VI_MIN = 112, 262 TTMP_VI_MAX = 123, 263 TTMP_GFX9PLUS_MIN = 108, 264 TTMP_GFX9PLUS_MAX = 123, 265 INLINE_INTEGER_C_MIN = 128, 266 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64 267 INLINE_INTEGER_C_MAX = 208, 268 INLINE_FLOATING_C_MIN = 240, 269 INLINE_FLOATING_C_MAX = 248, 270 LITERAL_CONST = 255, 271 VGPR_MIN = 256, 272 VGPR_MAX = 511 273 }; 274 275 } // namespace EncValues 276 } // namespace AMDGPU 277 278 namespace AMDGPU { 279 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns. 280 281 enum Id { // Message ID, width(4) [3:0]. 282 ID_UNKNOWN_ = -1, 283 ID_INTERRUPT = 1, 284 ID_GS, 285 ID_GS_DONE, 286 ID_GS_ALLOC_REQ = 9, 287 ID_GET_DOORBELL = 10, 288 ID_SYSMSG = 15, 289 ID_GAPS_LAST_, // Indicate that sequence has gaps. 290 ID_GAPS_FIRST_ = ID_INTERRUPT, 291 ID_SHIFT_ = 0, 292 ID_WIDTH_ = 4, 293 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 294 }; 295 296 enum Op { // Both GS and SYS operation IDs. 297 OP_UNKNOWN_ = -1, 298 OP_SHIFT_ = 4, 299 OP_NONE_ = 0, 300 // Bits used for operation encoding 301 OP_WIDTH_ = 3, 302 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_), 303 // GS operations are encoded in bits 5:4 304 OP_GS_NOP = 0, 305 OP_GS_CUT, 306 OP_GS_EMIT, 307 OP_GS_EMIT_CUT, 308 OP_GS_LAST_, 309 OP_GS_FIRST_ = OP_GS_NOP, 310 // SYS operations are encoded in bits 6:4 311 OP_SYS_ECC_ERR_INTERRUPT = 1, 312 OP_SYS_REG_RD, 313 OP_SYS_HOST_TRAP_ACK, 314 OP_SYS_TTRACE_PC, 315 OP_SYS_LAST_, 316 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT, 317 }; 318 319 enum StreamId : unsigned { // Stream ID, (2) [9:8]. 320 STREAM_ID_NONE_ = 0, 321 STREAM_ID_DEFAULT_ = 0, 322 STREAM_ID_LAST_ = 4, 323 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_, 324 STREAM_ID_SHIFT_ = 8, 325 STREAM_ID_WIDTH_= 2, 326 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_) 327 }; 328 329 } // namespace SendMsg 330 331 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns. 332 333 enum Id { // HwRegCode, (6) [5:0] 334 ID_UNKNOWN_ = -1, 335 ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined. 336 ID_MODE = 1, 337 ID_STATUS = 2, 338 ID_TRAPSTS = 3, 339 ID_HW_ID = 4, 340 ID_GPR_ALLOC = 5, 341 ID_LDS_ALLOC = 6, 342 ID_IB_STS = 7, 343 ID_MEM_BASES = 15, 344 ID_SYMBOLIC_FIRST_GFX9_ = ID_MEM_BASES, 345 ID_TBA_LO = 16, 346 ID_SYMBOLIC_FIRST_GFX10_ = ID_TBA_LO, 347 ID_TBA_HI = 17, 348 ID_TMA_LO = 18, 349 ID_TMA_HI = 19, 350 ID_FLAT_SCR_LO = 20, 351 ID_FLAT_SCR_HI = 21, 352 ID_XNACK_MASK = 22, 353 ID_POPS_PACKER = 25, 354 ID_SHADER_CYCLES = 29, 355 ID_SYMBOLIC_FIRST_GFX1030_ = ID_SHADER_CYCLES, 356 ID_SYMBOLIC_LAST_ = 30, 357 ID_SHIFT_ = 0, 358 ID_WIDTH_ = 6, 359 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 360 }; 361 362 enum Offset : unsigned { // Offset, (5) [10:6] 363 OFFSET_DEFAULT_ = 0, 364 OFFSET_SHIFT_ = 6, 365 OFFSET_WIDTH_ = 5, 366 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_), 367 368 OFFSET_MEM_VIOL = 8, 369 370 OFFSET_SRC_SHARED_BASE = 16, 371 OFFSET_SRC_PRIVATE_BASE = 0 372 }; 373 374 enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11] 375 WIDTH_M1_DEFAULT_ = 31, 376 WIDTH_M1_SHIFT_ = 11, 377 WIDTH_M1_WIDTH_ = 5, 378 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_), 379 380 WIDTH_M1_SRC_SHARED_BASE = 15, 381 WIDTH_M1_SRC_PRIVATE_BASE = 15 382 }; 383 384 // Some values from WidthMinusOne mapped into Width domain. 385 enum Width : unsigned { 386 WIDTH_DEFAULT_ = WIDTH_M1_DEFAULT_ + 1, 387 }; 388 389 enum ModeRegisterMasks : uint32_t { 390 FP_ROUND_MASK = 0xf << 0, // Bits 0..3 391 FP_DENORM_MASK = 0xf << 4, // Bits 4..7 392 DX10_CLAMP_MASK = 1 << 8, 393 IEEE_MODE_MASK = 1 << 9, 394 LOD_CLAMP_MASK = 1 << 10, 395 DEBUG_MASK = 1 << 11, 396 397 // EXCP_EN fields. 398 EXCP_EN_INVALID_MASK = 1 << 12, 399 EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13, 400 EXCP_EN_FLOAT_DIV0_MASK = 1 << 14, 401 EXCP_EN_OVERFLOW_MASK = 1 << 15, 402 EXCP_EN_UNDERFLOW_MASK = 1 << 16, 403 EXCP_EN_INEXACT_MASK = 1 << 17, 404 EXCP_EN_INT_DIV0_MASK = 1 << 18, 405 406 GPR_IDX_EN_MASK = 1 << 27, 407 VSKIP_MASK = 1 << 28, 408 CSP_MASK = 0x7u << 29 // Bits 29..31 409 }; 410 411 } // namespace Hwreg 412 413 namespace MTBUFFormat { 414 415 enum DataFormat : int64_t { 416 DFMT_INVALID = 0, 417 DFMT_8, 418 DFMT_16, 419 DFMT_8_8, 420 DFMT_32, 421 DFMT_16_16, 422 DFMT_10_11_11, 423 DFMT_11_11_10, 424 DFMT_10_10_10_2, 425 DFMT_2_10_10_10, 426 DFMT_8_8_8_8, 427 DFMT_32_32, 428 DFMT_16_16_16_16, 429 DFMT_32_32_32, 430 DFMT_32_32_32_32, 431 DFMT_RESERVED_15, 432 433 DFMT_MIN = DFMT_INVALID, 434 DFMT_MAX = DFMT_RESERVED_15, 435 436 DFMT_UNDEF = -1, 437 DFMT_DEFAULT = DFMT_8, 438 439 DFMT_SHIFT = 0, 440 DFMT_MASK = 0xF 441 }; 442 443 enum NumFormat : int64_t { 444 NFMT_UNORM = 0, 445 NFMT_SNORM, 446 NFMT_USCALED, 447 NFMT_SSCALED, 448 NFMT_UINT, 449 NFMT_SINT, 450 NFMT_RESERVED_6, // VI and GFX9 451 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only 452 NFMT_FLOAT, 453 454 NFMT_MIN = NFMT_UNORM, 455 NFMT_MAX = NFMT_FLOAT, 456 457 NFMT_UNDEF = -1, 458 NFMT_DEFAULT = NFMT_UNORM, 459 460 NFMT_SHIFT = 4, 461 NFMT_MASK = 7 462 }; 463 464 enum MergedFormat : int64_t { 465 DFMT_NFMT_UNDEF = -1, 466 DFMT_NFMT_DEFAULT = ((DFMT_DEFAULT & DFMT_MASK) << DFMT_SHIFT) | 467 ((NFMT_DEFAULT & NFMT_MASK) << NFMT_SHIFT), 468 469 470 DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT), 471 472 DFMT_NFMT_MAX = DFMT_NFMT_MASK 473 }; 474 475 enum UnifiedFormat : int64_t { 476 UFMT_INVALID = 0, 477 478 UFMT_8_UNORM, 479 UFMT_8_SNORM, 480 UFMT_8_USCALED, 481 UFMT_8_SSCALED, 482 UFMT_8_UINT, 483 UFMT_8_SINT, 484 485 UFMT_16_UNORM, 486 UFMT_16_SNORM, 487 UFMT_16_USCALED, 488 UFMT_16_SSCALED, 489 UFMT_16_UINT, 490 UFMT_16_SINT, 491 UFMT_16_FLOAT, 492 493 UFMT_8_8_UNORM, 494 UFMT_8_8_SNORM, 495 UFMT_8_8_USCALED, 496 UFMT_8_8_SSCALED, 497 UFMT_8_8_UINT, 498 UFMT_8_8_SINT, 499 500 UFMT_32_UINT, 501 UFMT_32_SINT, 502 UFMT_32_FLOAT, 503 504 UFMT_16_16_UNORM, 505 UFMT_16_16_SNORM, 506 UFMT_16_16_USCALED, 507 UFMT_16_16_SSCALED, 508 UFMT_16_16_UINT, 509 UFMT_16_16_SINT, 510 UFMT_16_16_FLOAT, 511 512 UFMT_10_11_11_UNORM, 513 UFMT_10_11_11_SNORM, 514 UFMT_10_11_11_USCALED, 515 UFMT_10_11_11_SSCALED, 516 UFMT_10_11_11_UINT, 517 UFMT_10_11_11_SINT, 518 UFMT_10_11_11_FLOAT, 519 520 UFMT_11_11_10_UNORM, 521 UFMT_11_11_10_SNORM, 522 UFMT_11_11_10_USCALED, 523 UFMT_11_11_10_SSCALED, 524 UFMT_11_11_10_UINT, 525 UFMT_11_11_10_SINT, 526 UFMT_11_11_10_FLOAT, 527 528 UFMT_10_10_10_2_UNORM, 529 UFMT_10_10_10_2_SNORM, 530 UFMT_10_10_10_2_USCALED, 531 UFMT_10_10_10_2_SSCALED, 532 UFMT_10_10_10_2_UINT, 533 UFMT_10_10_10_2_SINT, 534 535 UFMT_2_10_10_10_UNORM, 536 UFMT_2_10_10_10_SNORM, 537 UFMT_2_10_10_10_USCALED, 538 UFMT_2_10_10_10_SSCALED, 539 UFMT_2_10_10_10_UINT, 540 UFMT_2_10_10_10_SINT, 541 542 UFMT_8_8_8_8_UNORM, 543 UFMT_8_8_8_8_SNORM, 544 UFMT_8_8_8_8_USCALED, 545 UFMT_8_8_8_8_SSCALED, 546 UFMT_8_8_8_8_UINT, 547 UFMT_8_8_8_8_SINT, 548 549 UFMT_32_32_UINT, 550 UFMT_32_32_SINT, 551 UFMT_32_32_FLOAT, 552 553 UFMT_16_16_16_16_UNORM, 554 UFMT_16_16_16_16_SNORM, 555 UFMT_16_16_16_16_USCALED, 556 UFMT_16_16_16_16_SSCALED, 557 UFMT_16_16_16_16_UINT, 558 UFMT_16_16_16_16_SINT, 559 UFMT_16_16_16_16_FLOAT, 560 561 UFMT_32_32_32_UINT, 562 UFMT_32_32_32_SINT, 563 UFMT_32_32_32_FLOAT, 564 UFMT_32_32_32_32_UINT, 565 UFMT_32_32_32_32_SINT, 566 UFMT_32_32_32_32_FLOAT, 567 568 UFMT_FIRST = UFMT_INVALID, 569 UFMT_LAST = UFMT_32_32_32_32_FLOAT, 570 571 UFMT_MAX = 127, 572 573 UFMT_UNDEF = -1, 574 UFMT_DEFAULT = UFMT_8_UNORM 575 }; 576 577 } // namespace MTBUFFormat 578 579 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32. 580 581 enum Id : unsigned { // id of symbolic names 582 ID_QUAD_PERM = 0, 583 ID_BITMASK_PERM, 584 ID_SWAP, 585 ID_REVERSE, 586 ID_BROADCAST 587 }; 588 589 enum EncBits : unsigned { 590 591 // swizzle mode encodings 592 593 QUAD_PERM_ENC = 0x8000, 594 QUAD_PERM_ENC_MASK = 0xFF00, 595 596 BITMASK_PERM_ENC = 0x0000, 597 BITMASK_PERM_ENC_MASK = 0x8000, 598 599 // QUAD_PERM encodings 600 601 LANE_MASK = 0x3, 602 LANE_MAX = LANE_MASK, 603 LANE_SHIFT = 2, 604 LANE_NUM = 4, 605 606 // BITMASK_PERM encodings 607 608 BITMASK_MASK = 0x1F, 609 BITMASK_MAX = BITMASK_MASK, 610 BITMASK_WIDTH = 5, 611 612 BITMASK_AND_SHIFT = 0, 613 BITMASK_OR_SHIFT = 5, 614 BITMASK_XOR_SHIFT = 10 615 }; 616 617 } // namespace Swizzle 618 619 namespace SDWA { 620 621 enum SdwaSel : unsigned { 622 BYTE_0 = 0, 623 BYTE_1 = 1, 624 BYTE_2 = 2, 625 BYTE_3 = 3, 626 WORD_0 = 4, 627 WORD_1 = 5, 628 DWORD = 6, 629 }; 630 631 enum DstUnused : unsigned { 632 UNUSED_PAD = 0, 633 UNUSED_SEXT = 1, 634 UNUSED_PRESERVE = 2, 635 }; 636 637 enum SDWA9EncValues : unsigned { 638 SRC_SGPR_MASK = 0x100, 639 SRC_VGPR_MASK = 0xFF, 640 VOPC_DST_VCC_MASK = 0x80, 641 VOPC_DST_SGPR_MASK = 0x7F, 642 643 SRC_VGPR_MIN = 0, 644 SRC_VGPR_MAX = 255, 645 SRC_SGPR_MIN = 256, 646 SRC_SGPR_MAX_SI = 357, 647 SRC_SGPR_MAX_GFX10 = 361, 648 SRC_TTMP_MIN = 364, 649 SRC_TTMP_MAX = 379, 650 }; 651 652 } // namespace SDWA 653 654 namespace DPP { 655 656 enum DppCtrl : unsigned { 657 QUAD_PERM_FIRST = 0, 658 QUAD_PERM_ID = 0xE4, // identity permutation 659 QUAD_PERM_LAST = 0xFF, 660 DPP_UNUSED1 = 0x100, 661 ROW_SHL0 = 0x100, 662 ROW_SHL_FIRST = 0x101, 663 ROW_SHL_LAST = 0x10F, 664 DPP_UNUSED2 = 0x110, 665 ROW_SHR0 = 0x110, 666 ROW_SHR_FIRST = 0x111, 667 ROW_SHR_LAST = 0x11F, 668 DPP_UNUSED3 = 0x120, 669 ROW_ROR0 = 0x120, 670 ROW_ROR_FIRST = 0x121, 671 ROW_ROR_LAST = 0x12F, 672 WAVE_SHL1 = 0x130, 673 DPP_UNUSED4_FIRST = 0x131, 674 DPP_UNUSED4_LAST = 0x133, 675 WAVE_ROL1 = 0x134, 676 DPP_UNUSED5_FIRST = 0x135, 677 DPP_UNUSED5_LAST = 0x137, 678 WAVE_SHR1 = 0x138, 679 DPP_UNUSED6_FIRST = 0x139, 680 DPP_UNUSED6_LAST = 0x13B, 681 WAVE_ROR1 = 0x13C, 682 DPP_UNUSED7_FIRST = 0x13D, 683 DPP_UNUSED7_LAST = 0x13F, 684 ROW_MIRROR = 0x140, 685 ROW_HALF_MIRROR = 0x141, 686 BCAST15 = 0x142, 687 BCAST31 = 0x143, 688 DPP_UNUSED8_FIRST = 0x144, 689 DPP_UNUSED8_LAST = 0x14F, 690 ROW_NEWBCAST_FIRST= 0x150, 691 ROW_NEWBCAST_LAST = 0x15F, 692 ROW_SHARE_FIRST = 0x150, 693 ROW_SHARE_LAST = 0x15F, 694 ROW_XMASK_FIRST = 0x160, 695 ROW_XMASK_LAST = 0x16F, 696 DPP_LAST = ROW_XMASK_LAST 697 }; 698 699 enum DppFiMode { 700 DPP_FI_0 = 0, 701 DPP_FI_1 = 1, 702 DPP8_FI_0 = 0xE9, 703 DPP8_FI_1 = 0xEA, 704 }; 705 706 } // namespace DPP 707 708 namespace Exp { 709 710 enum Target : unsigned { 711 ET_MRT0 = 0, 712 ET_MRT7 = 7, 713 ET_MRTZ = 8, 714 ET_NULL = 9, 715 ET_POS0 = 12, 716 ET_POS3 = 15, 717 ET_POS4 = 16, // GFX10+ 718 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget 719 ET_PRIM = 20, // GFX10+ 720 ET_PARAM0 = 32, 721 ET_PARAM31 = 63, 722 723 ET_NULL_MAX_IDX = 0, 724 ET_MRTZ_MAX_IDX = 0, 725 ET_PRIM_MAX_IDX = 0, 726 ET_MRT_MAX_IDX = 7, 727 ET_POS_MAX_IDX = 4, 728 ET_PARAM_MAX_IDX = 31, 729 730 ET_INVALID = 255, 731 }; 732 733 } // namespace Exp 734 } // namespace AMDGPU 735 736 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 737 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) 738 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) 739 #define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25) 740 #define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1) 741 #define C_00B028_MEM_ORDERED 0xFDFFFFFF 742 743 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C 744 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) 745 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 746 #define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27) 747 #define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1) 748 #define C_00B128_MEM_ORDERED 0xF7FFFFFF 749 750 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 751 #define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27) 752 #define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1) 753 #define C_00B228_WGP_MODE 0xF7FFFFFF 754 #define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25) 755 #define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1) 756 #define C_00B228_MEM_ORDERED 0xFDFFFFFF 757 758 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328 759 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428 760 #define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26) 761 #define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1) 762 #define C_00B428_WGP_MODE 0xFBFFFFFF 763 #define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24) 764 #define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1) 765 #define C_00B428_MEM_ORDERED 0xFEFFFFFF 766 767 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528 768 769 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C 770 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) 771 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 772 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE 773 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) 774 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) 775 #define C_00B84C_USER_SGPR 0xFFFFFFC1 776 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6) 777 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1) 778 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF 779 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) 780 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) 781 #define C_00B84C_TGID_X_EN 0xFFFFFF7F 782 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) 783 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) 784 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF 785 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) 786 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) 787 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF 788 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) 789 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) 790 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF 791 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) 792 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) 793 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF 794 /* CIK */ 795 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) 796 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) 797 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF 798 /* */ 799 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) 800 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) 801 #define C_00B84C_LDS_SIZE 0xFF007FFF 802 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) 803 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) 804 #define C_00B84C_EXCP_EN 805 806 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC 807 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 808 809 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 810 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) 811 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) 812 #define C_00B848_VGPRS 0xFFFFFFC0 813 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) 814 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) 815 #define C_00B848_SGPRS 0xFFFFFC3F 816 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) 817 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) 818 #define C_00B848_PRIORITY 0xFFFFF3FF 819 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) 820 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 821 #define C_00B848_FLOAT_MODE 0xFFF00FFF 822 #define S_00B848_PRIV(x) (((x) & 0x1) << 20) 823 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1) 824 #define C_00B848_PRIV 0xFFEFFFFF 825 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) 826 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) 827 #define C_00B848_DX10_CLAMP 0xFFDFFFFF 828 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) 829 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) 830 #define C_00B848_DEBUG_MODE 0xFFBFFFFF 831 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) 832 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) 833 #define C_00B848_IEEE_MODE 0xFF7FFFFF 834 #define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29) 835 #define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1) 836 #define C_00B848_WGP_MODE 0xDFFFFFFF 837 #define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30) 838 #define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1) 839 #define C_00B848_MEM_ORDERED 0xBFFFFFFF 840 #define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31) 841 #define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1) 842 #define C_00B848_FWD_PROGRESS 0x7FFFFFFF 843 844 845 // Helpers for setting FLOAT_MODE 846 #define FP_ROUND_ROUND_TO_NEAREST 0 847 #define FP_ROUND_ROUND_TO_INF 1 848 #define FP_ROUND_ROUND_TO_NEGINF 2 849 #define FP_ROUND_ROUND_TO_ZERO 3 850 851 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double 852 // precision. 853 #define FP_ROUND_MODE_SP(x) ((x) & 0x3) 854 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2) 855 856 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0 857 #define FP_DENORM_FLUSH_OUT 1 858 #define FP_DENORM_FLUSH_IN 2 859 #define FP_DENORM_FLUSH_NONE 3 860 861 862 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double 863 // precision. 864 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4) 865 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6) 866 867 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 868 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12) 869 870 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 871 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) 872 873 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54 874 #define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21) 875 #define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22) 876 #define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23) 877 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8 878 #define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15) 879 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800 880 #define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15) 881 882 #define R_SPILLED_SGPRS 0x4 883 #define R_SPILLED_VGPRS 0x8 884 } // End namespace llvm 885 886 #endif 887