1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 /// \file 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 11 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 12 13 #include "llvm/MC/MCInstrDesc.h" 14 15 namespace llvm { 16 17 // This needs to be kept in sync with the field bits in SIRegisterClass. 18 enum SIRCFlags : uint8_t { 19 // For vector registers. 20 HasVGPR = 1 << 0, 21 HasAGPR = 1 << 1 22 }; // enum SIRCFlags 23 24 namespace SIInstrFlags { 25 // This needs to be kept in sync with the field bits in InstSI. 26 enum : uint64_t { 27 // Low bits - basic encoding information. 28 SALU = 1 << 0, 29 VALU = 1 << 1, 30 31 // SALU instruction formats. 32 SOP1 = 1 << 2, 33 SOP2 = 1 << 3, 34 SOPC = 1 << 4, 35 SOPK = 1 << 5, 36 SOPP = 1 << 6, 37 38 // VALU instruction formats. 39 VOP1 = 1 << 7, 40 VOP2 = 1 << 8, 41 VOPC = 1 << 9, 42 43 // TODO: Should this be spilt into VOP3 a and b? 44 VOP3 = 1 << 10, 45 VOP3P = 1 << 12, 46 47 VINTRP = 1 << 13, 48 SDWA = 1 << 14, 49 DPP = 1 << 15, 50 TRANS = 1 << 16, 51 52 // Memory instruction formats. 53 MUBUF = 1 << 17, 54 MTBUF = 1 << 18, 55 SMRD = 1 << 19, 56 MIMG = 1 << 20, 57 EXP = 1 << 21, 58 FLAT = 1 << 22, 59 DS = 1 << 23, 60 61 // Pseudo instruction formats. 62 VGPRSpill = 1 << 24, 63 SGPRSpill = 1 << 25, 64 65 // High bits - other information. 66 VM_CNT = UINT64_C(1) << 32, 67 EXP_CNT = UINT64_C(1) << 33, 68 LGKM_CNT = UINT64_C(1) << 34, 69 70 WQM = UINT64_C(1) << 35, 71 DisableWQM = UINT64_C(1) << 36, 72 Gather4 = UINT64_C(1) << 37, 73 SOPK_ZEXT = UINT64_C(1) << 38, 74 SCALAR_STORE = UINT64_C(1) << 39, 75 FIXED_SIZE = UINT64_C(1) << 40, 76 VOPAsmPrefer32Bit = UINT64_C(1) << 41, 77 VOP3_OPSEL = UINT64_C(1) << 42, 78 maybeAtomic = UINT64_C(1) << 43, 79 renamedInGFX9 = UINT64_C(1) << 44, 80 81 // Is a clamp on FP type. 82 FPClamp = UINT64_C(1) << 45, 83 84 // Is an integer clamp 85 IntClamp = UINT64_C(1) << 46, 86 87 // Clamps lo component of register. 88 ClampLo = UINT64_C(1) << 47, 89 90 // Clamps hi component of register. 91 // ClampLo and ClampHi set for packed clamp. 92 ClampHi = UINT64_C(1) << 48, 93 94 // Is a packed VOP3P instruction. 95 IsPacked = UINT64_C(1) << 49, 96 97 // Is a D16 buffer instruction. 98 D16Buf = UINT64_C(1) << 50, 99 100 // FLAT instruction accesses FLAT_GLBL segment. 101 FlatGlobal = UINT64_C(1) << 51, 102 103 // Uses floating point double precision rounding mode 104 FPDPRounding = UINT64_C(1) << 52, 105 106 // Instruction is FP atomic. 107 FPAtomic = UINT64_C(1) << 53, 108 109 // Is a MFMA instruction. 110 IsMAI = UINT64_C(1) << 54, 111 112 // Is a DOT instruction. 113 IsDOT = UINT64_C(1) << 55, 114 115 // FLAT instruction accesses FLAT_SCRATCH segment. 116 FlatScratch = UINT64_C(1) << 56, 117 118 // Atomic without return. 119 IsAtomicNoRet = UINT64_C(1) << 57, 120 121 // Atomic with return. 122 IsAtomicRet = UINT64_C(1) << 58 123 }; 124 125 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. 126 // The result is true if any of these tests are true. 127 enum ClassFlags : unsigned { 128 S_NAN = 1 << 0, // Signaling NaN 129 Q_NAN = 1 << 1, // Quiet NaN 130 N_INFINITY = 1 << 2, // Negative infinity 131 N_NORMAL = 1 << 3, // Negative normal 132 N_SUBNORMAL = 1 << 4, // Negative subnormal 133 N_ZERO = 1 << 5, // Negative zero 134 P_ZERO = 1 << 6, // Positive zero 135 P_SUBNORMAL = 1 << 7, // Positive subnormal 136 P_NORMAL = 1 << 8, // Positive normal 137 P_INFINITY = 1 << 9 // Positive infinity 138 }; 139 } 140 141 namespace AMDGPU { 142 enum OperandType : unsigned { 143 /// Operands with register or 32-bit immediate 144 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, 145 OPERAND_REG_IMM_INT64, 146 OPERAND_REG_IMM_INT16, 147 OPERAND_REG_IMM_FP32, 148 OPERAND_REG_IMM_FP64, 149 OPERAND_REG_IMM_FP16, 150 OPERAND_REG_IMM_V2FP16, 151 OPERAND_REG_IMM_V2INT16, 152 OPERAND_REG_IMM_V2INT32, 153 OPERAND_REG_IMM_V2FP32, 154 155 /// Operands with register or inline constant 156 OPERAND_REG_INLINE_C_INT16, 157 OPERAND_REG_INLINE_C_INT32, 158 OPERAND_REG_INLINE_C_INT64, 159 OPERAND_REG_INLINE_C_FP16, 160 OPERAND_REG_INLINE_C_FP32, 161 OPERAND_REG_INLINE_C_FP64, 162 OPERAND_REG_INLINE_C_V2INT16, 163 OPERAND_REG_INLINE_C_V2FP16, 164 OPERAND_REG_INLINE_C_V2INT32, 165 OPERAND_REG_INLINE_C_V2FP32, 166 167 /// Operands with an AccVGPR register or inline constant 168 OPERAND_REG_INLINE_AC_INT16, 169 OPERAND_REG_INLINE_AC_INT32, 170 OPERAND_REG_INLINE_AC_FP16, 171 OPERAND_REG_INLINE_AC_FP32, 172 OPERAND_REG_INLINE_AC_FP64, 173 OPERAND_REG_INLINE_AC_V2INT16, 174 OPERAND_REG_INLINE_AC_V2FP16, 175 OPERAND_REG_INLINE_AC_V2INT32, 176 OPERAND_REG_INLINE_AC_V2FP32, 177 178 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, 179 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32, 180 181 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16, 182 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2FP32, 183 184 OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16, 185 OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2FP32, 186 187 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32, 188 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST, 189 190 // Operand for source modifiers for VOP instructions 191 OPERAND_INPUT_MODS, 192 193 // Operand for SDWA instructions 194 OPERAND_SDWA_VOPC_DST, 195 196 /// Operand with 32-bit immediate that uses the constant bus. 197 OPERAND_KIMM32, 198 OPERAND_KIMM16 199 }; 200 } 201 202 // Input operand modifiers bit-masks 203 // NEG and SEXT share same bit-mask because they can't be set simultaneously. 204 namespace SISrcMods { 205 enum : unsigned { 206 NEG = 1 << 0, // Floating-point negate modifier 207 ABS = 1 << 1, // Floating-point absolute modifier 208 SEXT = 1 << 0, // Integer sign-extend modifier 209 NEG_HI = ABS, // Floating-point negate high packed component modifier. 210 OP_SEL_0 = 1 << 2, 211 OP_SEL_1 = 1 << 3, 212 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1) 213 }; 214 } 215 216 namespace SIOutMods { 217 enum : unsigned { 218 NONE = 0, 219 MUL2 = 1, 220 MUL4 = 2, 221 DIV2 = 3 222 }; 223 } 224 225 namespace AMDGPU { 226 namespace VGPRIndexMode { 227 228 enum Id : unsigned { // id of symbolic names 229 ID_SRC0 = 0, 230 ID_SRC1, 231 ID_SRC2, 232 ID_DST, 233 234 ID_MIN = ID_SRC0, 235 ID_MAX = ID_DST 236 }; 237 238 enum EncBits : unsigned { 239 OFF = 0, 240 SRC0_ENABLE = 1 << ID_SRC0, 241 SRC1_ENABLE = 1 << ID_SRC1, 242 SRC2_ENABLE = 1 << ID_SRC2, 243 DST_ENABLE = 1 << ID_DST, 244 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE, 245 UNDEF = 0xFFFF 246 }; 247 248 } // namespace VGPRIndexMode 249 } // namespace AMDGPU 250 251 namespace AMDGPUAsmVariants { 252 enum : unsigned { 253 DEFAULT = 0, 254 VOP3 = 1, 255 SDWA = 2, 256 SDWA9 = 3, 257 DPP = 4 258 }; 259 } 260 261 namespace AMDGPU { 262 namespace EncValues { // Encoding values of enum9/8/7 operands 263 264 enum : unsigned { 265 SGPR_MIN = 0, 266 SGPR_MAX_SI = 101, 267 SGPR_MAX_GFX10 = 105, 268 TTMP_VI_MIN = 112, 269 TTMP_VI_MAX = 123, 270 TTMP_GFX9PLUS_MIN = 108, 271 TTMP_GFX9PLUS_MAX = 123, 272 INLINE_INTEGER_C_MIN = 128, 273 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64 274 INLINE_INTEGER_C_MAX = 208, 275 INLINE_FLOATING_C_MIN = 240, 276 INLINE_FLOATING_C_MAX = 248, 277 LITERAL_CONST = 255, 278 VGPR_MIN = 256, 279 VGPR_MAX = 511 280 }; 281 282 } // namespace EncValues 283 } // namespace AMDGPU 284 285 namespace AMDGPU { 286 namespace CPol { 287 288 enum CPol { 289 GLC = 1, 290 SLC = 2, 291 DLC = 4, 292 SCC = 16, 293 ALL = GLC | SLC | DLC | SCC 294 }; 295 296 } // namespace CPol 297 298 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns. 299 300 enum Id { // Message ID, width(4) [3:0]. 301 ID_UNKNOWN_ = -1, 302 ID_INTERRUPT = 1, 303 ID_GS = 2, 304 ID_GS_DONE = 3, 305 ID_SAVEWAVE = 4, // added in GFX8 306 ID_STALL_WAVE_GEN = 5, // added in GFX9 307 ID_HALT_WAVES = 6, // added in GFX9 308 ID_ORDERED_PS_DONE = 7, // added in GFX9 309 ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10 310 ID_GS_ALLOC_REQ = 9, // added in GFX9 311 ID_GET_DOORBELL = 10, // added in GFX9 312 ID_GET_DDID = 11, // added in GFX10 313 ID_SYSMSG = 15, 314 ID_GAPS_LAST_, // Indicate that sequence has gaps. 315 ID_GAPS_FIRST_ = ID_INTERRUPT, 316 ID_SHIFT_ = 0, 317 ID_WIDTH_ = 4, 318 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 319 }; 320 321 enum Op { // Both GS and SYS operation IDs. 322 OP_UNKNOWN_ = -1, 323 OP_SHIFT_ = 4, 324 OP_NONE_ = 0, 325 // Bits used for operation encoding 326 OP_WIDTH_ = 3, 327 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_), 328 // GS operations are encoded in bits 5:4 329 OP_GS_NOP = 0, 330 OP_GS_CUT = 1, 331 OP_GS_EMIT = 2, 332 OP_GS_EMIT_CUT = 3, 333 OP_GS_LAST_, 334 OP_GS_FIRST_ = OP_GS_NOP, 335 // SYS operations are encoded in bits 6:4 336 OP_SYS_ECC_ERR_INTERRUPT = 1, 337 OP_SYS_REG_RD = 2, 338 OP_SYS_HOST_TRAP_ACK = 3, 339 OP_SYS_TTRACE_PC = 4, 340 OP_SYS_LAST_, 341 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT, 342 }; 343 344 enum StreamId : unsigned { // Stream ID, (2) [9:8]. 345 STREAM_ID_NONE_ = 0, 346 STREAM_ID_DEFAULT_ = 0, 347 STREAM_ID_LAST_ = 4, 348 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_, 349 STREAM_ID_SHIFT_ = 8, 350 STREAM_ID_WIDTH_= 2, 351 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_) 352 }; 353 354 } // namespace SendMsg 355 356 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns. 357 358 enum Id { // HwRegCode, (6) [5:0] 359 ID_UNKNOWN_ = -1, 360 ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined. 361 ID_MODE = 1, 362 ID_STATUS = 2, 363 ID_TRAPSTS = 3, 364 ID_HW_ID = 4, 365 ID_GPR_ALLOC = 5, 366 ID_LDS_ALLOC = 6, 367 ID_IB_STS = 7, 368 ID_MEM_BASES = 15, 369 ID_SYMBOLIC_FIRST_GFX9_ = ID_MEM_BASES, 370 ID_TBA_LO = 16, 371 ID_SYMBOLIC_FIRST_GFX10_ = ID_TBA_LO, 372 ID_TBA_HI = 17, 373 ID_TMA_LO = 18, 374 ID_TMA_HI = 19, 375 ID_FLAT_SCR_LO = 20, 376 ID_FLAT_SCR_HI = 21, 377 ID_XNACK_MASK = 22, 378 ID_POPS_PACKER = 25, 379 ID_SHADER_CYCLES = 29, 380 ID_SYMBOLIC_FIRST_GFX1030_ = ID_SHADER_CYCLES, 381 ID_SYMBOLIC_LAST_ = 30, 382 ID_SHIFT_ = 0, 383 ID_WIDTH_ = 6, 384 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 385 }; 386 387 enum Offset : unsigned { // Offset, (5) [10:6] 388 OFFSET_DEFAULT_ = 0, 389 OFFSET_SHIFT_ = 6, 390 OFFSET_WIDTH_ = 5, 391 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_), 392 393 OFFSET_MEM_VIOL = 8, 394 395 OFFSET_SRC_SHARED_BASE = 16, 396 OFFSET_SRC_PRIVATE_BASE = 0 397 }; 398 399 enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11] 400 WIDTH_M1_DEFAULT_ = 31, 401 WIDTH_M1_SHIFT_ = 11, 402 WIDTH_M1_WIDTH_ = 5, 403 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_), 404 405 WIDTH_M1_SRC_SHARED_BASE = 15, 406 WIDTH_M1_SRC_PRIVATE_BASE = 15 407 }; 408 409 // Some values from WidthMinusOne mapped into Width domain. 410 enum Width : unsigned { 411 WIDTH_DEFAULT_ = WIDTH_M1_DEFAULT_ + 1, 412 }; 413 414 enum ModeRegisterMasks : uint32_t { 415 FP_ROUND_MASK = 0xf << 0, // Bits 0..3 416 FP_DENORM_MASK = 0xf << 4, // Bits 4..7 417 DX10_CLAMP_MASK = 1 << 8, 418 IEEE_MODE_MASK = 1 << 9, 419 LOD_CLAMP_MASK = 1 << 10, 420 DEBUG_MASK = 1 << 11, 421 422 // EXCP_EN fields. 423 EXCP_EN_INVALID_MASK = 1 << 12, 424 EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13, 425 EXCP_EN_FLOAT_DIV0_MASK = 1 << 14, 426 EXCP_EN_OVERFLOW_MASK = 1 << 15, 427 EXCP_EN_UNDERFLOW_MASK = 1 << 16, 428 EXCP_EN_INEXACT_MASK = 1 << 17, 429 EXCP_EN_INT_DIV0_MASK = 1 << 18, 430 431 GPR_IDX_EN_MASK = 1 << 27, 432 VSKIP_MASK = 1 << 28, 433 CSP_MASK = 0x7u << 29 // Bits 29..31 434 }; 435 436 } // namespace Hwreg 437 438 namespace MTBUFFormat { 439 440 enum DataFormat : int64_t { 441 DFMT_INVALID = 0, 442 DFMT_8, 443 DFMT_16, 444 DFMT_8_8, 445 DFMT_32, 446 DFMT_16_16, 447 DFMT_10_11_11, 448 DFMT_11_11_10, 449 DFMT_10_10_10_2, 450 DFMT_2_10_10_10, 451 DFMT_8_8_8_8, 452 DFMT_32_32, 453 DFMT_16_16_16_16, 454 DFMT_32_32_32, 455 DFMT_32_32_32_32, 456 DFMT_RESERVED_15, 457 458 DFMT_MIN = DFMT_INVALID, 459 DFMT_MAX = DFMT_RESERVED_15, 460 461 DFMT_UNDEF = -1, 462 DFMT_DEFAULT = DFMT_8, 463 464 DFMT_SHIFT = 0, 465 DFMT_MASK = 0xF 466 }; 467 468 enum NumFormat : int64_t { 469 NFMT_UNORM = 0, 470 NFMT_SNORM, 471 NFMT_USCALED, 472 NFMT_SSCALED, 473 NFMT_UINT, 474 NFMT_SINT, 475 NFMT_RESERVED_6, // VI and GFX9 476 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only 477 NFMT_FLOAT, 478 479 NFMT_MIN = NFMT_UNORM, 480 NFMT_MAX = NFMT_FLOAT, 481 482 NFMT_UNDEF = -1, 483 NFMT_DEFAULT = NFMT_UNORM, 484 485 NFMT_SHIFT = 4, 486 NFMT_MASK = 7 487 }; 488 489 enum MergedFormat : int64_t { 490 DFMT_NFMT_UNDEF = -1, 491 DFMT_NFMT_DEFAULT = ((DFMT_DEFAULT & DFMT_MASK) << DFMT_SHIFT) | 492 ((NFMT_DEFAULT & NFMT_MASK) << NFMT_SHIFT), 493 494 495 DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT), 496 497 DFMT_NFMT_MAX = DFMT_NFMT_MASK 498 }; 499 500 enum UnifiedFormat : int64_t { 501 UFMT_INVALID = 0, 502 503 UFMT_8_UNORM, 504 UFMT_8_SNORM, 505 UFMT_8_USCALED, 506 UFMT_8_SSCALED, 507 UFMT_8_UINT, 508 UFMT_8_SINT, 509 510 UFMT_16_UNORM, 511 UFMT_16_SNORM, 512 UFMT_16_USCALED, 513 UFMT_16_SSCALED, 514 UFMT_16_UINT, 515 UFMT_16_SINT, 516 UFMT_16_FLOAT, 517 518 UFMT_8_8_UNORM, 519 UFMT_8_8_SNORM, 520 UFMT_8_8_USCALED, 521 UFMT_8_8_SSCALED, 522 UFMT_8_8_UINT, 523 UFMT_8_8_SINT, 524 525 UFMT_32_UINT, 526 UFMT_32_SINT, 527 UFMT_32_FLOAT, 528 529 UFMT_16_16_UNORM, 530 UFMT_16_16_SNORM, 531 UFMT_16_16_USCALED, 532 UFMT_16_16_SSCALED, 533 UFMT_16_16_UINT, 534 UFMT_16_16_SINT, 535 UFMT_16_16_FLOAT, 536 537 UFMT_10_11_11_UNORM, 538 UFMT_10_11_11_SNORM, 539 UFMT_10_11_11_USCALED, 540 UFMT_10_11_11_SSCALED, 541 UFMT_10_11_11_UINT, 542 UFMT_10_11_11_SINT, 543 UFMT_10_11_11_FLOAT, 544 545 UFMT_11_11_10_UNORM, 546 UFMT_11_11_10_SNORM, 547 UFMT_11_11_10_USCALED, 548 UFMT_11_11_10_SSCALED, 549 UFMT_11_11_10_UINT, 550 UFMT_11_11_10_SINT, 551 UFMT_11_11_10_FLOAT, 552 553 UFMT_10_10_10_2_UNORM, 554 UFMT_10_10_10_2_SNORM, 555 UFMT_10_10_10_2_USCALED, 556 UFMT_10_10_10_2_SSCALED, 557 UFMT_10_10_10_2_UINT, 558 UFMT_10_10_10_2_SINT, 559 560 UFMT_2_10_10_10_UNORM, 561 UFMT_2_10_10_10_SNORM, 562 UFMT_2_10_10_10_USCALED, 563 UFMT_2_10_10_10_SSCALED, 564 UFMT_2_10_10_10_UINT, 565 UFMT_2_10_10_10_SINT, 566 567 UFMT_8_8_8_8_UNORM, 568 UFMT_8_8_8_8_SNORM, 569 UFMT_8_8_8_8_USCALED, 570 UFMT_8_8_8_8_SSCALED, 571 UFMT_8_8_8_8_UINT, 572 UFMT_8_8_8_8_SINT, 573 574 UFMT_32_32_UINT, 575 UFMT_32_32_SINT, 576 UFMT_32_32_FLOAT, 577 578 UFMT_16_16_16_16_UNORM, 579 UFMT_16_16_16_16_SNORM, 580 UFMT_16_16_16_16_USCALED, 581 UFMT_16_16_16_16_SSCALED, 582 UFMT_16_16_16_16_UINT, 583 UFMT_16_16_16_16_SINT, 584 UFMT_16_16_16_16_FLOAT, 585 586 UFMT_32_32_32_UINT, 587 UFMT_32_32_32_SINT, 588 UFMT_32_32_32_FLOAT, 589 UFMT_32_32_32_32_UINT, 590 UFMT_32_32_32_32_SINT, 591 UFMT_32_32_32_32_FLOAT, 592 593 UFMT_FIRST = UFMT_INVALID, 594 UFMT_LAST = UFMT_32_32_32_32_FLOAT, 595 596 UFMT_MAX = 127, 597 598 UFMT_UNDEF = -1, 599 UFMT_DEFAULT = UFMT_8_UNORM 600 }; 601 602 } // namespace MTBUFFormat 603 604 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32. 605 606 enum Id : unsigned { // id of symbolic names 607 ID_QUAD_PERM = 0, 608 ID_BITMASK_PERM, 609 ID_SWAP, 610 ID_REVERSE, 611 ID_BROADCAST 612 }; 613 614 enum EncBits : unsigned { 615 616 // swizzle mode encodings 617 618 QUAD_PERM_ENC = 0x8000, 619 QUAD_PERM_ENC_MASK = 0xFF00, 620 621 BITMASK_PERM_ENC = 0x0000, 622 BITMASK_PERM_ENC_MASK = 0x8000, 623 624 // QUAD_PERM encodings 625 626 LANE_MASK = 0x3, 627 LANE_MAX = LANE_MASK, 628 LANE_SHIFT = 2, 629 LANE_NUM = 4, 630 631 // BITMASK_PERM encodings 632 633 BITMASK_MASK = 0x1F, 634 BITMASK_MAX = BITMASK_MASK, 635 BITMASK_WIDTH = 5, 636 637 BITMASK_AND_SHIFT = 0, 638 BITMASK_OR_SHIFT = 5, 639 BITMASK_XOR_SHIFT = 10 640 }; 641 642 } // namespace Swizzle 643 644 namespace SDWA { 645 646 enum SdwaSel : unsigned { 647 BYTE_0 = 0, 648 BYTE_1 = 1, 649 BYTE_2 = 2, 650 BYTE_3 = 3, 651 WORD_0 = 4, 652 WORD_1 = 5, 653 DWORD = 6, 654 }; 655 656 enum DstUnused : unsigned { 657 UNUSED_PAD = 0, 658 UNUSED_SEXT = 1, 659 UNUSED_PRESERVE = 2, 660 }; 661 662 enum SDWA9EncValues : unsigned { 663 SRC_SGPR_MASK = 0x100, 664 SRC_VGPR_MASK = 0xFF, 665 VOPC_DST_VCC_MASK = 0x80, 666 VOPC_DST_SGPR_MASK = 0x7F, 667 668 SRC_VGPR_MIN = 0, 669 SRC_VGPR_MAX = 255, 670 SRC_SGPR_MIN = 256, 671 SRC_SGPR_MAX_SI = 357, 672 SRC_SGPR_MAX_GFX10 = 361, 673 SRC_TTMP_MIN = 364, 674 SRC_TTMP_MAX = 379, 675 }; 676 677 } // namespace SDWA 678 679 namespace DPP { 680 681 // clang-format off 682 enum DppCtrl : unsigned { 683 QUAD_PERM_FIRST = 0, 684 QUAD_PERM_ID = 0xE4, // identity permutation 685 QUAD_PERM_LAST = 0xFF, 686 DPP_UNUSED1 = 0x100, 687 ROW_SHL0 = 0x100, 688 ROW_SHL_FIRST = 0x101, 689 ROW_SHL_LAST = 0x10F, 690 DPP_UNUSED2 = 0x110, 691 ROW_SHR0 = 0x110, 692 ROW_SHR_FIRST = 0x111, 693 ROW_SHR_LAST = 0x11F, 694 DPP_UNUSED3 = 0x120, 695 ROW_ROR0 = 0x120, 696 ROW_ROR_FIRST = 0x121, 697 ROW_ROR_LAST = 0x12F, 698 WAVE_SHL1 = 0x130, 699 DPP_UNUSED4_FIRST = 0x131, 700 DPP_UNUSED4_LAST = 0x133, 701 WAVE_ROL1 = 0x134, 702 DPP_UNUSED5_FIRST = 0x135, 703 DPP_UNUSED5_LAST = 0x137, 704 WAVE_SHR1 = 0x138, 705 DPP_UNUSED6_FIRST = 0x139, 706 DPP_UNUSED6_LAST = 0x13B, 707 WAVE_ROR1 = 0x13C, 708 DPP_UNUSED7_FIRST = 0x13D, 709 DPP_UNUSED7_LAST = 0x13F, 710 ROW_MIRROR = 0x140, 711 ROW_HALF_MIRROR = 0x141, 712 BCAST15 = 0x142, 713 BCAST31 = 0x143, 714 DPP_UNUSED8_FIRST = 0x144, 715 DPP_UNUSED8_LAST = 0x14F, 716 ROW_NEWBCAST_FIRST= 0x150, 717 ROW_NEWBCAST_LAST = 0x15F, 718 ROW_SHARE0 = 0x150, 719 ROW_SHARE_FIRST = 0x150, 720 ROW_SHARE_LAST = 0x15F, 721 ROW_XMASK0 = 0x160, 722 ROW_XMASK_FIRST = 0x160, 723 ROW_XMASK_LAST = 0x16F, 724 DPP_LAST = ROW_XMASK_LAST 725 }; 726 // clang-format on 727 728 enum DppFiMode { 729 DPP_FI_0 = 0, 730 DPP_FI_1 = 1, 731 DPP8_FI_0 = 0xE9, 732 DPP8_FI_1 = 0xEA, 733 }; 734 735 } // namespace DPP 736 737 namespace Exp { 738 739 enum Target : unsigned { 740 ET_MRT0 = 0, 741 ET_MRT7 = 7, 742 ET_MRTZ = 8, 743 ET_NULL = 9, 744 ET_POS0 = 12, 745 ET_POS3 = 15, 746 ET_POS4 = 16, // GFX10+ 747 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget 748 ET_PRIM = 20, // GFX10+ 749 ET_PARAM0 = 32, 750 ET_PARAM31 = 63, 751 752 ET_NULL_MAX_IDX = 0, 753 ET_MRTZ_MAX_IDX = 0, 754 ET_PRIM_MAX_IDX = 0, 755 ET_MRT_MAX_IDX = 7, 756 ET_POS_MAX_IDX = 4, 757 ET_PARAM_MAX_IDX = 31, 758 759 ET_INVALID = 255, 760 }; 761 762 } // namespace Exp 763 764 namespace VOP3PEncoding { 765 766 enum OpSel : uint64_t { 767 OP_SEL_HI_0 = UINT64_C(1) << 59, 768 OP_SEL_HI_1 = UINT64_C(1) << 60, 769 OP_SEL_HI_2 = UINT64_C(1) << 14, 770 }; 771 772 } // namespace VOP3PEncoding 773 774 } // namespace AMDGPU 775 776 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 777 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) 778 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) 779 #define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25) 780 #define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1) 781 #define C_00B028_MEM_ORDERED 0xFDFFFFFF 782 783 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C 784 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) 785 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 786 #define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27) 787 #define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1) 788 #define C_00B128_MEM_ORDERED 0xF7FFFFFF 789 790 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 791 #define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27) 792 #define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1) 793 #define C_00B228_WGP_MODE 0xF7FFFFFF 794 #define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25) 795 #define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1) 796 #define C_00B228_MEM_ORDERED 0xFDFFFFFF 797 798 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328 799 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428 800 #define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26) 801 #define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1) 802 #define C_00B428_WGP_MODE 0xFBFFFFFF 803 #define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24) 804 #define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1) 805 #define C_00B428_MEM_ORDERED 0xFEFFFFFF 806 807 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528 808 809 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C 810 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) 811 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 812 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE 813 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) 814 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) 815 #define C_00B84C_USER_SGPR 0xFFFFFFC1 816 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6) 817 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1) 818 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF 819 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) 820 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) 821 #define C_00B84C_TGID_X_EN 0xFFFFFF7F 822 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) 823 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) 824 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF 825 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) 826 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) 827 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF 828 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) 829 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) 830 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF 831 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) 832 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) 833 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF 834 /* CIK */ 835 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) 836 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) 837 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF 838 /* */ 839 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) 840 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) 841 #define C_00B84C_LDS_SIZE 0xFF007FFF 842 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) 843 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) 844 #define C_00B84C_EXCP_EN 845 846 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC 847 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 848 849 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 850 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) 851 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) 852 #define C_00B848_VGPRS 0xFFFFFFC0 853 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) 854 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) 855 #define C_00B848_SGPRS 0xFFFFFC3F 856 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) 857 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) 858 #define C_00B848_PRIORITY 0xFFFFF3FF 859 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) 860 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 861 #define C_00B848_FLOAT_MODE 0xFFF00FFF 862 #define S_00B848_PRIV(x) (((x) & 0x1) << 20) 863 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1) 864 #define C_00B848_PRIV 0xFFEFFFFF 865 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) 866 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) 867 #define C_00B848_DX10_CLAMP 0xFFDFFFFF 868 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) 869 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) 870 #define C_00B848_DEBUG_MODE 0xFFBFFFFF 871 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) 872 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) 873 #define C_00B848_IEEE_MODE 0xFF7FFFFF 874 #define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29) 875 #define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1) 876 #define C_00B848_WGP_MODE 0xDFFFFFFF 877 #define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30) 878 #define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1) 879 #define C_00B848_MEM_ORDERED 0xBFFFFFFF 880 #define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31) 881 #define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1) 882 #define C_00B848_FWD_PROGRESS 0x7FFFFFFF 883 884 885 // Helpers for setting FLOAT_MODE 886 #define FP_ROUND_ROUND_TO_NEAREST 0 887 #define FP_ROUND_ROUND_TO_INF 1 888 #define FP_ROUND_ROUND_TO_NEGINF 2 889 #define FP_ROUND_ROUND_TO_ZERO 3 890 891 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double 892 // precision. 893 #define FP_ROUND_MODE_SP(x) ((x) & 0x3) 894 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2) 895 896 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0 897 #define FP_DENORM_FLUSH_OUT 1 898 #define FP_DENORM_FLUSH_IN 2 899 #define FP_DENORM_FLUSH_NONE 3 900 901 902 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double 903 // precision. 904 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4) 905 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6) 906 907 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 908 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12) 909 910 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 911 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) 912 913 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54 914 #define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21) 915 #define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22) 916 #define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23) 917 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8 918 #define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15) 919 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800 920 #define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15) 921 922 #define R_SPILLED_SGPRS 0x4 923 #define R_SPILLED_VGPRS 0x8 924 } // End namespace llvm 925 926 #endif 927