1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #include "llvm/MC/MCInstrDesc.h" 12 13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 14 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 15 16 namespace llvm { 17 18 namespace SIInstrFlags { 19 // This needs to be kept in sync with the field bits in InstSI. 20 enum : uint64_t { 21 // Low bits - basic encoding information. 22 SALU = 1 << 0, 23 VALU = 1 << 1, 24 25 // SALU instruction formats. 26 SOP1 = 1 << 2, 27 SOP2 = 1 << 3, 28 SOPC = 1 << 4, 29 SOPK = 1 << 5, 30 SOPP = 1 << 6, 31 32 // VALU instruction formats. 33 VOP1 = 1 << 7, 34 VOP2 = 1 << 8, 35 VOPC = 1 << 9, 36 37 // TODO: Should this be spilt into VOP3 a and b? 38 VOP3 = 1 << 10, 39 VOP3P = 1 << 12, 40 41 VINTRP = 1 << 13, 42 SDWA = 1 << 14, 43 DPP = 1 << 15, 44 45 // Memory instruction formats. 46 MUBUF = 1 << 16, 47 MTBUF = 1 << 17, 48 SMRD = 1 << 18, 49 MIMG = 1 << 19, 50 EXP = 1 << 20, 51 FLAT = 1 << 21, 52 DS = 1 << 22, 53 54 // Pseudo instruction formats. 55 VGPRSpill = 1 << 23, 56 SGPRSpill = 1 << 24, 57 58 // High bits - other information. 59 VM_CNT = UINT64_C(1) << 32, 60 EXP_CNT = UINT64_C(1) << 33, 61 LGKM_CNT = UINT64_C(1) << 34, 62 63 WQM = UINT64_C(1) << 35, 64 DisableWQM = UINT64_C(1) << 36, 65 Gather4 = UINT64_C(1) << 37, 66 SOPK_ZEXT = UINT64_C(1) << 38, 67 SCALAR_STORE = UINT64_C(1) << 39, 68 FIXED_SIZE = UINT64_C(1) << 40, 69 VOPAsmPrefer32Bit = UINT64_C(1) << 41, 70 HasFPClamp = UINT64_C(1) << 42 71 }; 72 73 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. 74 // The result is true if any of these tests are true. 75 enum ClassFlags { 76 S_NAN = 1 << 0, // Signaling NaN 77 Q_NAN = 1 << 1, // Quiet NaN 78 N_INFINITY = 1 << 2, // Negative infinity 79 N_NORMAL = 1 << 3, // Negative normal 80 N_SUBNORMAL = 1 << 4, // Negative subnormal 81 N_ZERO = 1 << 5, // Negative zero 82 P_ZERO = 1 << 6, // Positive zero 83 P_SUBNORMAL = 1 << 7, // Positive subnormal 84 P_NORMAL = 1 << 8, // Positive normal 85 P_INFINITY = 1 << 9 // Positive infinity 86 }; 87 } 88 89 namespace AMDGPU { 90 enum OperandType { 91 /// Operands with register or 32-bit immediate 92 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, 93 OPERAND_REG_IMM_INT64, 94 OPERAND_REG_IMM_INT16, 95 OPERAND_REG_IMM_FP32, 96 OPERAND_REG_IMM_FP64, 97 OPERAND_REG_IMM_FP16, 98 99 /// Operands with register or inline constant 100 OPERAND_REG_INLINE_C_INT16, 101 OPERAND_REG_INLINE_C_INT32, 102 OPERAND_REG_INLINE_C_INT64, 103 OPERAND_REG_INLINE_C_FP16, 104 OPERAND_REG_INLINE_C_FP32, 105 OPERAND_REG_INLINE_C_FP64, 106 OPERAND_REG_INLINE_C_V2FP16, 107 OPERAND_REG_INLINE_C_V2INT16, 108 109 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, 110 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_FP16, 111 112 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16, 113 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_C_V2INT16, 114 115 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32, 116 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST, 117 118 // Operand for source modifiers for VOP instructions 119 OPERAND_INPUT_MODS, 120 121 /// Operand with 32-bit immediate that uses the constant bus. 122 OPERAND_KIMM32, 123 OPERAND_KIMM16 124 }; 125 } 126 127 // Input operand modifiers bit-masks 128 // NEG and SEXT share same bit-mask because they can't be set simultaneously. 129 namespace SISrcMods { 130 enum { 131 NEG = 1 << 0, // Floating-point negate modifier 132 ABS = 1 << 1, // Floating-point absolute modifier 133 SEXT = 1 << 0, // Integer sign-extend modifier 134 NEG_HI = ABS, // Floating-point negate high packed component modifier. 135 OP_SEL_0 = 1 << 2, 136 OP_SEL_1 = 1 << 3 137 }; 138 } 139 140 namespace SIOutMods { 141 enum { 142 NONE = 0, 143 MUL2 = 1, 144 MUL4 = 2, 145 DIV2 = 3 146 }; 147 } 148 149 namespace VGPRIndexMode { 150 enum { 151 SRC0_ENABLE = 1 << 0, 152 SRC1_ENABLE = 1 << 1, 153 SRC2_ENABLE = 1 << 2, 154 DST_ENABLE = 1 << 3 155 }; 156 } 157 158 namespace AMDGPUAsmVariants { 159 enum { 160 DEFAULT = 0, 161 VOP3 = 1, 162 SDWA = 2, 163 DPP = 3 164 }; 165 } 166 167 namespace AMDGPU { 168 namespace EncValues { // Encoding values of enum9/8/7 operands 169 170 enum { 171 SGPR_MIN = 0, 172 SGPR_MAX = 101, 173 TTMP_MIN = 112, 174 TTMP_MAX = 123, 175 INLINE_INTEGER_C_MIN = 128, 176 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64 177 INLINE_INTEGER_C_MAX = 208, 178 INLINE_FLOATING_C_MIN = 240, 179 INLINE_FLOATING_C_MAX = 248, 180 LITERAL_CONST = 255, 181 VGPR_MIN = 256, 182 VGPR_MAX = 511 183 }; 184 185 } // namespace EncValues 186 } // namespace AMDGPU 187 188 namespace AMDGPU { 189 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns. 190 191 enum Id { // Message ID, width(4) [3:0]. 192 ID_UNKNOWN_ = -1, 193 ID_INTERRUPT = 1, 194 ID_GS, 195 ID_GS_DONE, 196 ID_SYSMSG = 15, 197 ID_GAPS_LAST_, // Indicate that sequence has gaps. 198 ID_GAPS_FIRST_ = ID_INTERRUPT, 199 ID_SHIFT_ = 0, 200 ID_WIDTH_ = 4, 201 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 202 }; 203 204 enum Op { // Both GS and SYS operation IDs. 205 OP_UNKNOWN_ = -1, 206 OP_SHIFT_ = 4, 207 // width(2) [5:4] 208 OP_GS_NOP = 0, 209 OP_GS_CUT, 210 OP_GS_EMIT, 211 OP_GS_EMIT_CUT, 212 OP_GS_LAST_, 213 OP_GS_FIRST_ = OP_GS_NOP, 214 OP_GS_WIDTH_ = 2, 215 OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_), 216 // width(3) [6:4] 217 OP_SYS_ECC_ERR_INTERRUPT = 1, 218 OP_SYS_REG_RD, 219 OP_SYS_HOST_TRAP_ACK, 220 OP_SYS_TTRACE_PC, 221 OP_SYS_LAST_, 222 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT, 223 OP_SYS_WIDTH_ = 3, 224 OP_SYS_MASK_ = (((1 << OP_SYS_WIDTH_) - 1) << OP_SHIFT_) 225 }; 226 227 enum StreamId { // Stream ID, (2) [9:8]. 228 STREAM_ID_DEFAULT_ = 0, 229 STREAM_ID_LAST_ = 4, 230 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_, 231 STREAM_ID_SHIFT_ = 8, 232 STREAM_ID_WIDTH_= 2, 233 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_) 234 }; 235 236 } // namespace SendMsg 237 238 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns. 239 240 enum Id { // HwRegCode, (6) [5:0] 241 ID_UNKNOWN_ = -1, 242 ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined. 243 ID_MODE = 1, 244 ID_STATUS = 2, 245 ID_TRAPSTS = 3, 246 ID_HW_ID = 4, 247 ID_GPR_ALLOC = 5, 248 ID_LDS_ALLOC = 6, 249 ID_IB_STS = 7, 250 ID_SYMBOLIC_LAST_ = 8, 251 ID_SHIFT_ = 0, 252 ID_WIDTH_ = 6, 253 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 254 }; 255 256 enum Offset { // Offset, (5) [10:6] 257 OFFSET_DEFAULT_ = 0, 258 OFFSET_SHIFT_ = 6, 259 OFFSET_WIDTH_ = 5, 260 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_) 261 }; 262 263 enum WidthMinusOne { // WidthMinusOne, (5) [15:11] 264 WIDTH_M1_DEFAULT_ = 31, 265 WIDTH_M1_SHIFT_ = 11, 266 WIDTH_M1_WIDTH_ = 5, 267 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_) 268 }; 269 270 } // namespace Hwreg 271 272 namespace SDWA { 273 274 enum SdwaSel { 275 BYTE_0 = 0, 276 BYTE_1 = 1, 277 BYTE_2 = 2, 278 BYTE_3 = 3, 279 WORD_0 = 4, 280 WORD_1 = 5, 281 DWORD = 6, 282 }; 283 284 enum DstUnused { 285 UNUSED_PAD = 0, 286 UNUSED_SEXT = 1, 287 UNUSED_PRESERVE = 2, 288 }; 289 290 } // namespace SDWA 291 } // namespace AMDGPU 292 293 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 294 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C 295 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) 296 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 297 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 298 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 299 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) 300 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) 301 302 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C 303 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) 304 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 305 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE 306 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) 307 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) 308 #define C_00B84C_USER_SGPR 0xFFFFFFC1 309 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6) 310 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1) 311 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF 312 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) 313 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) 314 #define C_00B84C_TGID_X_EN 0xFFFFFF7F 315 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) 316 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) 317 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF 318 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) 319 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) 320 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF 321 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) 322 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) 323 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF 324 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) 325 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) 326 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF 327 /* CIK */ 328 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) 329 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) 330 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF 331 /* */ 332 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) 333 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) 334 #define C_00B84C_LDS_SIZE 0xFF007FFF 335 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) 336 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) 337 #define C_00B84C_EXCP_EN 338 339 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC 340 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 341 342 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 343 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) 344 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) 345 #define C_00B848_VGPRS 0xFFFFFFC0 346 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) 347 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) 348 #define C_00B848_SGPRS 0xFFFFFC3F 349 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) 350 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) 351 #define C_00B848_PRIORITY 0xFFFFF3FF 352 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) 353 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 354 #define C_00B848_FLOAT_MODE 0xFFF00FFF 355 #define S_00B848_PRIV(x) (((x) & 0x1) << 20) 356 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1) 357 #define C_00B848_PRIV 0xFFEFFFFF 358 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) 359 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) 360 #define C_00B848_DX10_CLAMP 0xFFDFFFFF 361 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) 362 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) 363 #define C_00B848_DEBUG_MODE 0xFFBFFFFF 364 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) 365 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) 366 #define C_00B848_IEEE_MODE 0xFF7FFFFF 367 368 369 // Helpers for setting FLOAT_MODE 370 #define FP_ROUND_ROUND_TO_NEAREST 0 371 #define FP_ROUND_ROUND_TO_INF 1 372 #define FP_ROUND_ROUND_TO_NEGINF 2 373 #define FP_ROUND_ROUND_TO_ZERO 3 374 375 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double 376 // precision. 377 #define FP_ROUND_MODE_SP(x) ((x) & 0x3) 378 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2) 379 380 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0 381 #define FP_DENORM_FLUSH_OUT 1 382 #define FP_DENORM_FLUSH_IN 2 383 #define FP_DENORM_FLUSH_NONE 3 384 385 386 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double 387 // precision. 388 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4) 389 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6) 390 391 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 392 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12) 393 394 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 395 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) 396 397 #define R_SPILLED_SGPRS 0x4 398 #define R_SPILLED_VGPRS 0x8 399 } // End namespace llvm 400 401 #endif 402