1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #include "llvm/MC/MCInstrDesc.h" 12 13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 14 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 15 16 namespace SIInstrFlags { 17 // This needs to be kept in sync with the field bits in InstSI. 18 enum { 19 SALU = 1 << 3, 20 VALU = 1 << 4, 21 22 SOP1 = 1 << 5, 23 SOP2 = 1 << 6, 24 SOPC = 1 << 7, 25 SOPK = 1 << 8, 26 SOPP = 1 << 9, 27 28 VOP1 = 1 << 10, 29 VOP2 = 1 << 11, 30 VOP3 = 1 << 12, 31 VOPC = 1 << 13, 32 SDWA = 1 << 14, 33 DPP = 1 << 15, 34 35 MUBUF = 1 << 16, 36 MTBUF = 1 << 17, 37 SMRD = 1 << 18, 38 DS = 1 << 19, 39 MIMG = 1 << 20, 40 FLAT = 1 << 21, 41 WQM = 1 << 22, 42 VGPRSpill = 1 << 23, 43 VOPAsmPrefer32Bit = 1 << 24 44 }; 45 } 46 47 namespace llvm { 48 namespace AMDGPU { 49 enum OperandType { 50 /// Operand with register or 32-bit immediate 51 OPERAND_REG_IMM32 = MCOI::OPERAND_FIRST_TARGET, 52 /// Operand with register or inline constant 53 OPERAND_REG_INLINE_C, 54 55 /// Operand with 32-bit immediate that uses the constant bus. The standard 56 /// OPERAND_IMMEDIATE should be used for special immediates such as source 57 /// modifiers. 58 OPERAND_KIMM32 59 }; 60 } 61 } 62 63 namespace SIInstrFlags { 64 enum Flags { 65 // First 4 bits are the instruction encoding 66 VM_CNT = 1 << 0, 67 EXP_CNT = 1 << 1, 68 LGKM_CNT = 1 << 2 69 }; 70 71 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. 72 // The result is true if any of these tests are true. 73 enum ClassFlags { 74 S_NAN = 1 << 0, // Signaling NaN 75 Q_NAN = 1 << 1, // Quiet NaN 76 N_INFINITY = 1 << 2, // Negative infinity 77 N_NORMAL = 1 << 3, // Negative normal 78 N_SUBNORMAL = 1 << 4, // Negative subnormal 79 N_ZERO = 1 << 5, // Negative zero 80 P_ZERO = 1 << 6, // Positive zero 81 P_SUBNORMAL = 1 << 7, // Positive subnormal 82 P_NORMAL = 1 << 8, // Positive normal 83 P_INFINITY = 1 << 9 // Positive infinity 84 }; 85 } 86 87 // Input operand modifiers bit-masks 88 // NEG and SEXT share same bit-mask because they can't be set simultaneously. 89 namespace SISrcMods { 90 enum { 91 NEG = 1 << 0, // Floating-point negate modifier 92 ABS = 1 << 1, // Floating-point absolute modifier 93 SEXT = 1 << 0 // Integer sign-extend modifier 94 }; 95 } 96 97 namespace SIOutMods { 98 enum { 99 NONE = 0, 100 MUL2 = 1, 101 MUL4 = 2, 102 DIV2 = 3 103 }; 104 } 105 106 namespace llvm { 107 namespace AMDGPU { 108 namespace EncValues { // Encoding values of enum9/8/7 operands 109 110 enum { 111 SGPR_MIN = 0, 112 SGPR_MAX = 101, 113 TTMP_MIN = 112, 114 TTMP_MAX = 123, 115 INLINE_INTEGER_C_MIN = 128, 116 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64 117 INLINE_INTEGER_C_MAX = 208, 118 INLINE_FLOATING_C_MIN = 240, 119 INLINE_FLOATING_C_MAX = 248, 120 LITERAL_CONST = 255, 121 VGPR_MIN = 256, 122 VGPR_MAX = 511 123 }; 124 125 } // namespace EncValues 126 } // namespace AMDGPU 127 } // namespace llvm 128 129 namespace llvm { 130 namespace AMDGPU { 131 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns. 132 133 enum Id { // Message ID, width(4) [3:0]. 134 ID_UNKNOWN_ = -1, 135 ID_INTERRUPT = 1, 136 ID_GS, 137 ID_GS_DONE, 138 ID_SYSMSG = 15, 139 ID_GAPS_LAST_, // Indicate that sequence has gaps. 140 ID_GAPS_FIRST_ = ID_INTERRUPT, 141 ID_SHIFT_ = 0, 142 ID_WIDTH_ = 4, 143 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 144 }; 145 146 enum Op { // Both GS and SYS operation IDs. 147 OP_UNKNOWN_ = -1, 148 OP_SHIFT_ = 4, 149 // width(2) [5:4] 150 OP_GS_NOP = 0, 151 OP_GS_CUT, 152 OP_GS_EMIT, 153 OP_GS_EMIT_CUT, 154 OP_GS_LAST_, 155 OP_GS_FIRST_ = OP_GS_NOP, 156 OP_GS_WIDTH_ = 2, 157 OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_), 158 // width(3) [6:4] 159 OP_SYS_ECC_ERR_INTERRUPT = 1, 160 OP_SYS_REG_RD, 161 OP_SYS_HOST_TRAP_ACK, 162 OP_SYS_TTRACE_PC, 163 OP_SYS_LAST_, 164 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT, 165 OP_SYS_WIDTH_ = 3, 166 OP_SYS_MASK_ = (((1 << OP_SYS_WIDTH_) - 1) << OP_SHIFT_) 167 }; 168 169 enum StreamId { // Stream ID, (2) [9:8]. 170 STREAM_ID_DEFAULT_ = 0, 171 STREAM_ID_LAST_ = 4, 172 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_, 173 STREAM_ID_SHIFT_ = 8, 174 STREAM_ID_WIDTH_= 2, 175 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_) 176 }; 177 178 } // namespace SendMsg 179 180 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns. 181 182 enum Id { // HwRegCode, (6) [5:0] 183 ID_UNKNOWN_ = -1, 184 ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined. 185 ID_SYMBOLIC_LAST_ = 8, 186 ID_SHIFT_ = 0, 187 ID_WIDTH_ = 6, 188 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 189 }; 190 191 enum Offset { // Offset, (5) [10:6] 192 OFFSET_DEFAULT_ = 0, 193 OFFSET_SHIFT_ = 6, 194 OFFSET_WIDTH_ = 5, 195 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_) 196 }; 197 198 enum WidthMinusOne { // WidthMinusOne, (5) [15:11] 199 WIDTH_M1_DEFAULT_ = 31, 200 WIDTH_M1_SHIFT_ = 11, 201 WIDTH_M1_WIDTH_ = 5, 202 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_) 203 }; 204 205 } // namespace Hwreg 206 } // namespace AMDGPU 207 } // namespace llvm 208 209 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 210 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C 211 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) 212 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 213 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 214 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 215 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) 216 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) 217 218 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C 219 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) 220 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 221 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE 222 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) 223 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) 224 #define C_00B84C_USER_SGPR 0xFFFFFFC1 225 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) 226 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) 227 #define C_00B84C_TGID_X_EN 0xFFFFFF7F 228 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) 229 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) 230 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF 231 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) 232 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) 233 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF 234 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) 235 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) 236 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF 237 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) 238 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) 239 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF 240 /* CIK */ 241 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) 242 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) 243 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF 244 /* */ 245 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) 246 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) 247 #define C_00B84C_LDS_SIZE 0xFF007FFF 248 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) 249 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) 250 #define C_00B84C_EXCP_EN 251 252 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC 253 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 254 255 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 256 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) 257 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) 258 #define C_00B848_VGPRS 0xFFFFFFC0 259 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) 260 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) 261 #define C_00B848_SGPRS 0xFFFFFC3F 262 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) 263 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) 264 #define C_00B848_PRIORITY 0xFFFFF3FF 265 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) 266 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 267 #define C_00B848_FLOAT_MODE 0xFFF00FFF 268 #define S_00B848_PRIV(x) (((x) & 0x1) << 20) 269 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1) 270 #define C_00B848_PRIV 0xFFEFFFFF 271 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) 272 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) 273 #define C_00B848_DX10_CLAMP 0xFFDFFFFF 274 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) 275 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) 276 #define C_00B848_DEBUG_MODE 0xFFBFFFFF 277 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) 278 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) 279 #define C_00B848_IEEE_MODE 0xFF7FFFFF 280 281 282 // Helpers for setting FLOAT_MODE 283 #define FP_ROUND_ROUND_TO_NEAREST 0 284 #define FP_ROUND_ROUND_TO_INF 1 285 #define FP_ROUND_ROUND_TO_NEGINF 2 286 #define FP_ROUND_ROUND_TO_ZERO 3 287 288 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double 289 // precision. 290 #define FP_ROUND_MODE_SP(x) ((x) & 0x3) 291 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2) 292 293 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0 294 #define FP_DENORM_FLUSH_OUT 1 295 #define FP_DENORM_FLUSH_IN 2 296 #define FP_DENORM_FLUSH_NONE 3 297 298 299 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double 300 // precision. 301 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4) 302 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6) 303 304 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 305 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12) 306 307 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 308 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) 309 310 311 #endif 312