1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 /// \file 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 11 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 12 13 #include "llvm/MC/MCInstrDesc.h" 14 15 namespace llvm { 16 17 // This needs to be kept in sync with the field bits in SIRegisterClass. 18 enum SIRCFlags : uint8_t { 19 // For vector registers. 20 HasVGPR = 1 << 0, 21 HasAGPR = 1 << 1, 22 HasSGPR = 1 << 2 23 }; // enum SIRCFlags 24 25 namespace SIInstrFlags { 26 // This needs to be kept in sync with the field bits in InstSI. 27 enum : uint64_t { 28 // Low bits - basic encoding information. 29 SALU = 1 << 0, 30 VALU = 1 << 1, 31 32 // SALU instruction formats. 33 SOP1 = 1 << 2, 34 SOP2 = 1 << 3, 35 SOPC = 1 << 4, 36 SOPK = 1 << 5, 37 SOPP = 1 << 6, 38 39 // VALU instruction formats. 40 VOP1 = 1 << 7, 41 VOP2 = 1 << 8, 42 VOPC = 1 << 9, 43 44 // TODO: Should this be spilt into VOP3 a and b? 45 VOP3 = 1 << 10, 46 VOP3P = 1 << 12, 47 48 VINTRP = 1 << 13, 49 SDWA = 1 << 14, 50 DPP = 1 << 15, 51 TRANS = 1 << 16, 52 53 // Memory instruction formats. 54 MUBUF = 1 << 17, 55 MTBUF = 1 << 18, 56 SMRD = 1 << 19, 57 MIMG = 1 << 20, 58 EXP = 1 << 21, 59 FLAT = 1 << 22, 60 DS = 1 << 23, 61 62 // Pseudo instruction formats. 63 VGPRSpill = 1 << 24, 64 SGPRSpill = 1 << 25, 65 66 // High bits - other information. 67 VM_CNT = UINT64_C(1) << 32, 68 EXP_CNT = UINT64_C(1) << 33, 69 LGKM_CNT = UINT64_C(1) << 34, 70 71 WQM = UINT64_C(1) << 35, 72 DisableWQM = UINT64_C(1) << 36, 73 Gather4 = UINT64_C(1) << 37, 74 SOPK_ZEXT = UINT64_C(1) << 38, 75 SCALAR_STORE = UINT64_C(1) << 39, 76 FIXED_SIZE = UINT64_C(1) << 40, 77 VOPAsmPrefer32Bit = UINT64_C(1) << 41, 78 VOP3_OPSEL = UINT64_C(1) << 42, 79 maybeAtomic = UINT64_C(1) << 43, 80 renamedInGFX9 = UINT64_C(1) << 44, 81 82 // Is a clamp on FP type. 83 FPClamp = UINT64_C(1) << 45, 84 85 // Is an integer clamp 86 IntClamp = UINT64_C(1) << 46, 87 88 // Clamps lo component of register. 89 ClampLo = UINT64_C(1) << 47, 90 91 // Clamps hi component of register. 92 // ClampLo and ClampHi set for packed clamp. 93 ClampHi = UINT64_C(1) << 48, 94 95 // Is a packed VOP3P instruction. 96 IsPacked = UINT64_C(1) << 49, 97 98 // Is a D16 buffer instruction. 99 D16Buf = UINT64_C(1) << 50, 100 101 // FLAT instruction accesses FLAT_GLBL segment. 102 FlatGlobal = UINT64_C(1) << 51, 103 104 // Uses floating point double precision rounding mode 105 FPDPRounding = UINT64_C(1) << 52, 106 107 // Instruction is FP atomic. 108 FPAtomic = UINT64_C(1) << 53, 109 110 // Is a MFMA instruction. 111 IsMAI = UINT64_C(1) << 54, 112 113 // Is a DOT instruction. 114 IsDOT = UINT64_C(1) << 55, 115 116 // FLAT instruction accesses FLAT_SCRATCH segment. 117 FlatScratch = UINT64_C(1) << 56, 118 119 // Atomic without return. 120 IsAtomicNoRet = UINT64_C(1) << 57, 121 122 // Atomic with return. 123 IsAtomicRet = UINT64_C(1) << 58 124 }; 125 126 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. 127 // The result is true if any of these tests are true. 128 enum ClassFlags : unsigned { 129 S_NAN = 1 << 0, // Signaling NaN 130 Q_NAN = 1 << 1, // Quiet NaN 131 N_INFINITY = 1 << 2, // Negative infinity 132 N_NORMAL = 1 << 3, // Negative normal 133 N_SUBNORMAL = 1 << 4, // Negative subnormal 134 N_ZERO = 1 << 5, // Negative zero 135 P_ZERO = 1 << 6, // Positive zero 136 P_SUBNORMAL = 1 << 7, // Positive subnormal 137 P_NORMAL = 1 << 8, // Positive normal 138 P_INFINITY = 1 << 9 // Positive infinity 139 }; 140 } 141 142 namespace AMDGPU { 143 enum OperandType : unsigned { 144 /// Operands with register or 32-bit immediate 145 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, 146 OPERAND_REG_IMM_INT64, 147 OPERAND_REG_IMM_INT16, 148 OPERAND_REG_IMM_FP32, 149 OPERAND_REG_IMM_FP64, 150 OPERAND_REG_IMM_FP16, 151 OPERAND_REG_IMM_FP16_DEFERRED, 152 OPERAND_REG_IMM_FP32_DEFERRED, 153 OPERAND_REG_IMM_V2FP16, 154 OPERAND_REG_IMM_V2INT16, 155 OPERAND_REG_IMM_V2INT32, 156 OPERAND_REG_IMM_V2FP32, 157 158 /// Operands with register or inline constant 159 OPERAND_REG_INLINE_C_INT16, 160 OPERAND_REG_INLINE_C_INT32, 161 OPERAND_REG_INLINE_C_INT64, 162 OPERAND_REG_INLINE_C_FP16, 163 OPERAND_REG_INLINE_C_FP32, 164 OPERAND_REG_INLINE_C_FP64, 165 OPERAND_REG_INLINE_C_V2INT16, 166 OPERAND_REG_INLINE_C_V2FP16, 167 OPERAND_REG_INLINE_C_V2INT32, 168 OPERAND_REG_INLINE_C_V2FP32, 169 170 /// Operand with 32-bit immediate that uses the constant bus. 171 OPERAND_KIMM32, 172 OPERAND_KIMM16, 173 174 /// Operands with an AccVGPR register or inline constant 175 OPERAND_REG_INLINE_AC_INT16, 176 OPERAND_REG_INLINE_AC_INT32, 177 OPERAND_REG_INLINE_AC_FP16, 178 OPERAND_REG_INLINE_AC_FP32, 179 OPERAND_REG_INLINE_AC_FP64, 180 OPERAND_REG_INLINE_AC_V2INT16, 181 OPERAND_REG_INLINE_AC_V2FP16, 182 OPERAND_REG_INLINE_AC_V2INT32, 183 OPERAND_REG_INLINE_AC_V2FP32, 184 185 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, 186 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32, 187 188 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16, 189 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2FP32, 190 191 OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16, 192 OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2FP32, 193 194 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32, 195 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST, 196 197 // Operand for source modifiers for VOP instructions 198 OPERAND_INPUT_MODS, 199 200 // Operand for SDWA instructions 201 OPERAND_SDWA_VOPC_DST 202 203 }; 204 } 205 206 // Input operand modifiers bit-masks 207 // NEG and SEXT share same bit-mask because they can't be set simultaneously. 208 namespace SISrcMods { 209 enum : unsigned { 210 NEG = 1 << 0, // Floating-point negate modifier 211 ABS = 1 << 1, // Floating-point absolute modifier 212 SEXT = 1 << 0, // Integer sign-extend modifier 213 NEG_HI = ABS, // Floating-point negate high packed component modifier. 214 OP_SEL_0 = 1 << 2, 215 OP_SEL_1 = 1 << 3, 216 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1) 217 }; 218 } 219 220 namespace SIOutMods { 221 enum : unsigned { 222 NONE = 0, 223 MUL2 = 1, 224 MUL4 = 2, 225 DIV2 = 3 226 }; 227 } 228 229 namespace AMDGPU { 230 namespace VGPRIndexMode { 231 232 enum Id : unsigned { // id of symbolic names 233 ID_SRC0 = 0, 234 ID_SRC1, 235 ID_SRC2, 236 ID_DST, 237 238 ID_MIN = ID_SRC0, 239 ID_MAX = ID_DST 240 }; 241 242 enum EncBits : unsigned { 243 OFF = 0, 244 SRC0_ENABLE = 1 << ID_SRC0, 245 SRC1_ENABLE = 1 << ID_SRC1, 246 SRC2_ENABLE = 1 << ID_SRC2, 247 DST_ENABLE = 1 << ID_DST, 248 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE, 249 UNDEF = 0xFFFF 250 }; 251 252 } // namespace VGPRIndexMode 253 } // namespace AMDGPU 254 255 namespace AMDGPUAsmVariants { 256 enum : unsigned { 257 DEFAULT = 0, 258 VOP3 = 1, 259 SDWA = 2, 260 SDWA9 = 3, 261 DPP = 4 262 }; 263 } 264 265 namespace AMDGPU { 266 namespace EncValues { // Encoding values of enum9/8/7 operands 267 268 enum : unsigned { 269 SGPR_MIN = 0, 270 SGPR_MAX_SI = 101, 271 SGPR_MAX_GFX10 = 105, 272 TTMP_VI_MIN = 112, 273 TTMP_VI_MAX = 123, 274 TTMP_GFX9PLUS_MIN = 108, 275 TTMP_GFX9PLUS_MAX = 123, 276 INLINE_INTEGER_C_MIN = 128, 277 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64 278 INLINE_INTEGER_C_MAX = 208, 279 INLINE_FLOATING_C_MIN = 240, 280 INLINE_FLOATING_C_MAX = 248, 281 LITERAL_CONST = 255, 282 VGPR_MIN = 256, 283 VGPR_MAX = 511 284 }; 285 286 } // namespace EncValues 287 } // namespace AMDGPU 288 289 namespace AMDGPU { 290 namespace CPol { 291 292 enum CPol { 293 GLC = 1, 294 SLC = 2, 295 DLC = 4, 296 SCC = 16, 297 SC0 = GLC, 298 SC1 = SCC, 299 NT = SLC, 300 ALL = GLC | SLC | DLC | SCC 301 }; 302 303 } // namespace CPol 304 305 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns. 306 307 enum Id { // Message ID, width(4) [3:0]. 308 ID_UNKNOWN_ = -1, 309 ID_INTERRUPT = 1, 310 ID_GS = 2, 311 ID_GS_DONE = 3, 312 ID_SAVEWAVE = 4, // added in GFX8 313 ID_STALL_WAVE_GEN = 5, // added in GFX9 314 ID_HALT_WAVES = 6, // added in GFX9 315 ID_ORDERED_PS_DONE = 7, // added in GFX9 316 ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10 317 ID_GS_ALLOC_REQ = 9, // added in GFX9 318 ID_GET_DOORBELL = 10, // added in GFX9 319 ID_GET_DDID = 11, // added in GFX10 320 ID_SYSMSG = 15, 321 ID_GAPS_LAST_, // Indicate that sequence has gaps. 322 ID_GAPS_FIRST_ = ID_INTERRUPT, 323 ID_SHIFT_ = 0, 324 ID_WIDTH_ = 4, 325 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 326 }; 327 328 enum Op { // Both GS and SYS operation IDs. 329 OP_UNKNOWN_ = -1, 330 OP_SHIFT_ = 4, 331 OP_NONE_ = 0, 332 // Bits used for operation encoding 333 OP_WIDTH_ = 3, 334 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_), 335 // GS operations are encoded in bits 5:4 336 OP_GS_NOP = 0, 337 OP_GS_CUT = 1, 338 OP_GS_EMIT = 2, 339 OP_GS_EMIT_CUT = 3, 340 OP_GS_LAST_, 341 OP_GS_FIRST_ = OP_GS_NOP, 342 // SYS operations are encoded in bits 6:4 343 OP_SYS_ECC_ERR_INTERRUPT = 1, 344 OP_SYS_REG_RD = 2, 345 OP_SYS_HOST_TRAP_ACK = 3, 346 OP_SYS_TTRACE_PC = 4, 347 OP_SYS_LAST_, 348 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT, 349 }; 350 351 enum StreamId : unsigned { // Stream ID, (2) [9:8]. 352 STREAM_ID_NONE_ = 0, 353 STREAM_ID_DEFAULT_ = 0, 354 STREAM_ID_LAST_ = 4, 355 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_, 356 STREAM_ID_SHIFT_ = 8, 357 STREAM_ID_WIDTH_= 2, 358 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_) 359 }; 360 361 } // namespace SendMsg 362 363 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns. 364 365 enum Id { // HwRegCode, (6) [5:0] 366 ID_MODE = 1, 367 ID_STATUS = 2, 368 ID_TRAPSTS = 3, 369 ID_HW_ID = 4, 370 ID_GPR_ALLOC = 5, 371 ID_LDS_ALLOC = 6, 372 ID_IB_STS = 7, 373 ID_MEM_BASES = 15, 374 ID_TBA_LO = 16, 375 ID_TBA_HI = 17, 376 ID_TMA_LO = 18, 377 ID_TMA_HI = 19, 378 ID_XCC_ID = 20, 379 ID_SQ_PERF_SNAPSHOT_DATA = 21, 380 ID_SQ_PERF_SNAPSHOT_DATA1 = 22, 381 ID_SQ_PERF_SNAPSHOT_PC_LO = 23, 382 ID_SQ_PERF_SNAPSHOT_PC_HI = 24, 383 ID_FLAT_SCR_LO = 20, 384 ID_FLAT_SCR_HI = 21, 385 ID_XNACK_MASK = 22, 386 ID_HW_ID1 = 23, 387 ID_HW_ID2 = 24, 388 ID_POPS_PACKER = 25, 389 ID_SHADER_CYCLES = 29, 390 391 ID_SHIFT_ = 0, 392 ID_WIDTH_ = 6, 393 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 394 }; 395 396 enum Offset : unsigned { // Offset, (5) [10:6] 397 OFFSET_DEFAULT_ = 0, 398 OFFSET_SHIFT_ = 6, 399 OFFSET_WIDTH_ = 5, 400 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_), 401 402 OFFSET_MEM_VIOL = 8, 403 404 OFFSET_SRC_SHARED_BASE = 16, 405 OFFSET_SRC_PRIVATE_BASE = 0 406 }; 407 408 enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11] 409 WIDTH_M1_DEFAULT_ = 31, 410 WIDTH_M1_SHIFT_ = 11, 411 WIDTH_M1_WIDTH_ = 5, 412 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_), 413 414 WIDTH_M1_SRC_SHARED_BASE = 15, 415 WIDTH_M1_SRC_PRIVATE_BASE = 15 416 }; 417 418 // Some values from WidthMinusOne mapped into Width domain. 419 enum Width : unsigned { 420 WIDTH_DEFAULT_ = WIDTH_M1_DEFAULT_ + 1, 421 }; 422 423 enum ModeRegisterMasks : uint32_t { 424 FP_ROUND_MASK = 0xf << 0, // Bits 0..3 425 FP_DENORM_MASK = 0xf << 4, // Bits 4..7 426 DX10_CLAMP_MASK = 1 << 8, 427 IEEE_MODE_MASK = 1 << 9, 428 LOD_CLAMP_MASK = 1 << 10, 429 DEBUG_MASK = 1 << 11, 430 431 // EXCP_EN fields. 432 EXCP_EN_INVALID_MASK = 1 << 12, 433 EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13, 434 EXCP_EN_FLOAT_DIV0_MASK = 1 << 14, 435 EXCP_EN_OVERFLOW_MASK = 1 << 15, 436 EXCP_EN_UNDERFLOW_MASK = 1 << 16, 437 EXCP_EN_INEXACT_MASK = 1 << 17, 438 EXCP_EN_INT_DIV0_MASK = 1 << 18, 439 440 GPR_IDX_EN_MASK = 1 << 27, 441 VSKIP_MASK = 1 << 28, 442 CSP_MASK = 0x7u << 29 // Bits 29..31 443 }; 444 445 } // namespace Hwreg 446 447 namespace MTBUFFormat { 448 449 enum DataFormat : int64_t { 450 DFMT_INVALID = 0, 451 DFMT_8, 452 DFMT_16, 453 DFMT_8_8, 454 DFMT_32, 455 DFMT_16_16, 456 DFMT_10_11_11, 457 DFMT_11_11_10, 458 DFMT_10_10_10_2, 459 DFMT_2_10_10_10, 460 DFMT_8_8_8_8, 461 DFMT_32_32, 462 DFMT_16_16_16_16, 463 DFMT_32_32_32, 464 DFMT_32_32_32_32, 465 DFMT_RESERVED_15, 466 467 DFMT_MIN = DFMT_INVALID, 468 DFMT_MAX = DFMT_RESERVED_15, 469 470 DFMT_UNDEF = -1, 471 DFMT_DEFAULT = DFMT_8, 472 473 DFMT_SHIFT = 0, 474 DFMT_MASK = 0xF 475 }; 476 477 enum NumFormat : int64_t { 478 NFMT_UNORM = 0, 479 NFMT_SNORM, 480 NFMT_USCALED, 481 NFMT_SSCALED, 482 NFMT_UINT, 483 NFMT_SINT, 484 NFMT_RESERVED_6, // VI and GFX9 485 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only 486 NFMT_FLOAT, 487 488 NFMT_MIN = NFMT_UNORM, 489 NFMT_MAX = NFMT_FLOAT, 490 491 NFMT_UNDEF = -1, 492 NFMT_DEFAULT = NFMT_UNORM, 493 494 NFMT_SHIFT = 4, 495 NFMT_MASK = 7 496 }; 497 498 enum MergedFormat : int64_t { 499 DFMT_NFMT_UNDEF = -1, 500 DFMT_NFMT_DEFAULT = ((DFMT_DEFAULT & DFMT_MASK) << DFMT_SHIFT) | 501 ((NFMT_DEFAULT & NFMT_MASK) << NFMT_SHIFT), 502 503 504 DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT), 505 506 DFMT_NFMT_MAX = DFMT_NFMT_MASK 507 }; 508 509 enum UnifiedFormat : int64_t { 510 UFMT_INVALID = 0, 511 512 UFMT_8_UNORM, 513 UFMT_8_SNORM, 514 UFMT_8_USCALED, 515 UFMT_8_SSCALED, 516 UFMT_8_UINT, 517 UFMT_8_SINT, 518 519 UFMT_16_UNORM, 520 UFMT_16_SNORM, 521 UFMT_16_USCALED, 522 UFMT_16_SSCALED, 523 UFMT_16_UINT, 524 UFMT_16_SINT, 525 UFMT_16_FLOAT, 526 527 UFMT_8_8_UNORM, 528 UFMT_8_8_SNORM, 529 UFMT_8_8_USCALED, 530 UFMT_8_8_SSCALED, 531 UFMT_8_8_UINT, 532 UFMT_8_8_SINT, 533 534 UFMT_32_UINT, 535 UFMT_32_SINT, 536 UFMT_32_FLOAT, 537 538 UFMT_16_16_UNORM, 539 UFMT_16_16_SNORM, 540 UFMT_16_16_USCALED, 541 UFMT_16_16_SSCALED, 542 UFMT_16_16_UINT, 543 UFMT_16_16_SINT, 544 UFMT_16_16_FLOAT, 545 546 UFMT_10_11_11_UNORM, 547 UFMT_10_11_11_SNORM, 548 UFMT_10_11_11_USCALED, 549 UFMT_10_11_11_SSCALED, 550 UFMT_10_11_11_UINT, 551 UFMT_10_11_11_SINT, 552 UFMT_10_11_11_FLOAT, 553 554 UFMT_11_11_10_UNORM, 555 UFMT_11_11_10_SNORM, 556 UFMT_11_11_10_USCALED, 557 UFMT_11_11_10_SSCALED, 558 UFMT_11_11_10_UINT, 559 UFMT_11_11_10_SINT, 560 UFMT_11_11_10_FLOAT, 561 562 UFMT_10_10_10_2_UNORM, 563 UFMT_10_10_10_2_SNORM, 564 UFMT_10_10_10_2_USCALED, 565 UFMT_10_10_10_2_SSCALED, 566 UFMT_10_10_10_2_UINT, 567 UFMT_10_10_10_2_SINT, 568 569 UFMT_2_10_10_10_UNORM, 570 UFMT_2_10_10_10_SNORM, 571 UFMT_2_10_10_10_USCALED, 572 UFMT_2_10_10_10_SSCALED, 573 UFMT_2_10_10_10_UINT, 574 UFMT_2_10_10_10_SINT, 575 576 UFMT_8_8_8_8_UNORM, 577 UFMT_8_8_8_8_SNORM, 578 UFMT_8_8_8_8_USCALED, 579 UFMT_8_8_8_8_SSCALED, 580 UFMT_8_8_8_8_UINT, 581 UFMT_8_8_8_8_SINT, 582 583 UFMT_32_32_UINT, 584 UFMT_32_32_SINT, 585 UFMT_32_32_FLOAT, 586 587 UFMT_16_16_16_16_UNORM, 588 UFMT_16_16_16_16_SNORM, 589 UFMT_16_16_16_16_USCALED, 590 UFMT_16_16_16_16_SSCALED, 591 UFMT_16_16_16_16_UINT, 592 UFMT_16_16_16_16_SINT, 593 UFMT_16_16_16_16_FLOAT, 594 595 UFMT_32_32_32_UINT, 596 UFMT_32_32_32_SINT, 597 UFMT_32_32_32_FLOAT, 598 UFMT_32_32_32_32_UINT, 599 UFMT_32_32_32_32_SINT, 600 UFMT_32_32_32_32_FLOAT, 601 602 UFMT_FIRST = UFMT_INVALID, 603 UFMT_LAST = UFMT_32_32_32_32_FLOAT, 604 605 UFMT_MAX = 127, 606 607 UFMT_UNDEF = -1, 608 UFMT_DEFAULT = UFMT_8_UNORM 609 }; 610 611 } // namespace MTBUFFormat 612 613 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32. 614 615 enum Id : unsigned { // id of symbolic names 616 ID_QUAD_PERM = 0, 617 ID_BITMASK_PERM, 618 ID_SWAP, 619 ID_REVERSE, 620 ID_BROADCAST 621 }; 622 623 enum EncBits : unsigned { 624 625 // swizzle mode encodings 626 627 QUAD_PERM_ENC = 0x8000, 628 QUAD_PERM_ENC_MASK = 0xFF00, 629 630 BITMASK_PERM_ENC = 0x0000, 631 BITMASK_PERM_ENC_MASK = 0x8000, 632 633 // QUAD_PERM encodings 634 635 LANE_MASK = 0x3, 636 LANE_MAX = LANE_MASK, 637 LANE_SHIFT = 2, 638 LANE_NUM = 4, 639 640 // BITMASK_PERM encodings 641 642 BITMASK_MASK = 0x1F, 643 BITMASK_MAX = BITMASK_MASK, 644 BITMASK_WIDTH = 5, 645 646 BITMASK_AND_SHIFT = 0, 647 BITMASK_OR_SHIFT = 5, 648 BITMASK_XOR_SHIFT = 10 649 }; 650 651 } // namespace Swizzle 652 653 namespace SDWA { 654 655 enum SdwaSel : unsigned { 656 BYTE_0 = 0, 657 BYTE_1 = 1, 658 BYTE_2 = 2, 659 BYTE_3 = 3, 660 WORD_0 = 4, 661 WORD_1 = 5, 662 DWORD = 6, 663 }; 664 665 enum DstUnused : unsigned { 666 UNUSED_PAD = 0, 667 UNUSED_SEXT = 1, 668 UNUSED_PRESERVE = 2, 669 }; 670 671 enum SDWA9EncValues : unsigned { 672 SRC_SGPR_MASK = 0x100, 673 SRC_VGPR_MASK = 0xFF, 674 VOPC_DST_VCC_MASK = 0x80, 675 VOPC_DST_SGPR_MASK = 0x7F, 676 677 SRC_VGPR_MIN = 0, 678 SRC_VGPR_MAX = 255, 679 SRC_SGPR_MIN = 256, 680 SRC_SGPR_MAX_SI = 357, 681 SRC_SGPR_MAX_GFX10 = 361, 682 SRC_TTMP_MIN = 364, 683 SRC_TTMP_MAX = 379, 684 }; 685 686 } // namespace SDWA 687 688 namespace DPP { 689 690 // clang-format off 691 enum DppCtrl : unsigned { 692 QUAD_PERM_FIRST = 0, 693 QUAD_PERM_ID = 0xE4, // identity permutation 694 QUAD_PERM_LAST = 0xFF, 695 DPP_UNUSED1 = 0x100, 696 ROW_SHL0 = 0x100, 697 ROW_SHL_FIRST = 0x101, 698 ROW_SHL_LAST = 0x10F, 699 DPP_UNUSED2 = 0x110, 700 ROW_SHR0 = 0x110, 701 ROW_SHR_FIRST = 0x111, 702 ROW_SHR_LAST = 0x11F, 703 DPP_UNUSED3 = 0x120, 704 ROW_ROR0 = 0x120, 705 ROW_ROR_FIRST = 0x121, 706 ROW_ROR_LAST = 0x12F, 707 WAVE_SHL1 = 0x130, 708 DPP_UNUSED4_FIRST = 0x131, 709 DPP_UNUSED4_LAST = 0x133, 710 WAVE_ROL1 = 0x134, 711 DPP_UNUSED5_FIRST = 0x135, 712 DPP_UNUSED5_LAST = 0x137, 713 WAVE_SHR1 = 0x138, 714 DPP_UNUSED6_FIRST = 0x139, 715 DPP_UNUSED6_LAST = 0x13B, 716 WAVE_ROR1 = 0x13C, 717 DPP_UNUSED7_FIRST = 0x13D, 718 DPP_UNUSED7_LAST = 0x13F, 719 ROW_MIRROR = 0x140, 720 ROW_HALF_MIRROR = 0x141, 721 BCAST15 = 0x142, 722 BCAST31 = 0x143, 723 DPP_UNUSED8_FIRST = 0x144, 724 DPP_UNUSED8_LAST = 0x14F, 725 ROW_NEWBCAST_FIRST= 0x150, 726 ROW_NEWBCAST_LAST = 0x15F, 727 ROW_SHARE0 = 0x150, 728 ROW_SHARE_FIRST = 0x150, 729 ROW_SHARE_LAST = 0x15F, 730 ROW_XMASK0 = 0x160, 731 ROW_XMASK_FIRST = 0x160, 732 ROW_XMASK_LAST = 0x16F, 733 DPP_LAST = ROW_XMASK_LAST 734 }; 735 // clang-format on 736 737 enum DppFiMode { 738 DPP_FI_0 = 0, 739 DPP_FI_1 = 1, 740 DPP8_FI_0 = 0xE9, 741 DPP8_FI_1 = 0xEA, 742 }; 743 744 } // namespace DPP 745 746 namespace Exp { 747 748 enum Target : unsigned { 749 ET_MRT0 = 0, 750 ET_MRT7 = 7, 751 ET_MRTZ = 8, 752 ET_NULL = 9, 753 ET_POS0 = 12, 754 ET_POS3 = 15, 755 ET_POS4 = 16, // GFX10+ 756 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget 757 ET_PRIM = 20, // GFX10+ 758 ET_PARAM0 = 32, 759 ET_PARAM31 = 63, 760 761 ET_NULL_MAX_IDX = 0, 762 ET_MRTZ_MAX_IDX = 0, 763 ET_PRIM_MAX_IDX = 0, 764 ET_MRT_MAX_IDX = 7, 765 ET_POS_MAX_IDX = 4, 766 ET_PARAM_MAX_IDX = 31, 767 768 ET_INVALID = 255, 769 }; 770 771 } // namespace Exp 772 773 namespace VOP3PEncoding { 774 775 enum OpSel : uint64_t { 776 OP_SEL_HI_0 = UINT64_C(1) << 59, 777 OP_SEL_HI_1 = UINT64_C(1) << 60, 778 OP_SEL_HI_2 = UINT64_C(1) << 14, 779 }; 780 781 } // namespace VOP3PEncoding 782 783 namespace ImplicitArg { 784 // Implicit kernel argument offset for code object version 5. 785 enum Offset_COV5 : unsigned { 786 HOSTCALL_PTR_OFFSET = 80, 787 HEAP_PTR_OFFSET = 96, 788 PRIVATE_BASE_OFFSET = 192, 789 SHARED_BASE_OFFSET = 196, 790 QUEUE_PTR_OFFSET = 200, 791 }; 792 793 } // namespace ImplicitArg 794 } // namespace AMDGPU 795 796 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 797 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) 798 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) 799 #define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25) 800 #define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1) 801 #define C_00B028_MEM_ORDERED 0xFDFFFFFF 802 803 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C 804 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) 805 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 806 #define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27) 807 #define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1) 808 #define C_00B128_MEM_ORDERED 0xF7FFFFFF 809 810 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 811 #define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27) 812 #define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1) 813 #define C_00B228_WGP_MODE 0xF7FFFFFF 814 #define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25) 815 #define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1) 816 #define C_00B228_MEM_ORDERED 0xFDFFFFFF 817 818 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328 819 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428 820 #define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26) 821 #define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1) 822 #define C_00B428_WGP_MODE 0xFBFFFFFF 823 #define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24) 824 #define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1) 825 #define C_00B428_MEM_ORDERED 0xFEFFFFFF 826 827 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528 828 829 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C 830 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) 831 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 832 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE 833 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) 834 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) 835 #define C_00B84C_USER_SGPR 0xFFFFFFC1 836 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6) 837 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1) 838 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF 839 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) 840 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) 841 #define C_00B84C_TGID_X_EN 0xFFFFFF7F 842 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) 843 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) 844 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF 845 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) 846 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) 847 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF 848 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) 849 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) 850 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF 851 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) 852 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) 853 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF 854 /* CIK */ 855 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) 856 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) 857 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF 858 /* */ 859 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) 860 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) 861 #define C_00B84C_LDS_SIZE 0xFF007FFF 862 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) 863 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) 864 #define C_00B84C_EXCP_EN 865 866 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC 867 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 868 869 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 870 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) 871 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) 872 #define C_00B848_VGPRS 0xFFFFFFC0 873 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) 874 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) 875 #define C_00B848_SGPRS 0xFFFFFC3F 876 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) 877 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) 878 #define C_00B848_PRIORITY 0xFFFFF3FF 879 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) 880 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 881 #define C_00B848_FLOAT_MODE 0xFFF00FFF 882 #define S_00B848_PRIV(x) (((x) & 0x1) << 20) 883 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1) 884 #define C_00B848_PRIV 0xFFEFFFFF 885 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) 886 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) 887 #define C_00B848_DX10_CLAMP 0xFFDFFFFF 888 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) 889 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) 890 #define C_00B848_DEBUG_MODE 0xFFBFFFFF 891 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) 892 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) 893 #define C_00B848_IEEE_MODE 0xFF7FFFFF 894 #define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29) 895 #define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1) 896 #define C_00B848_WGP_MODE 0xDFFFFFFF 897 #define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30) 898 #define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1) 899 #define C_00B848_MEM_ORDERED 0xBFFFFFFF 900 #define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31) 901 #define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1) 902 #define C_00B848_FWD_PROGRESS 0x7FFFFFFF 903 904 905 // Helpers for setting FLOAT_MODE 906 #define FP_ROUND_ROUND_TO_NEAREST 0 907 #define FP_ROUND_ROUND_TO_INF 1 908 #define FP_ROUND_ROUND_TO_NEGINF 2 909 #define FP_ROUND_ROUND_TO_ZERO 3 910 911 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double 912 // precision. 913 #define FP_ROUND_MODE_SP(x) ((x) & 0x3) 914 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2) 915 916 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0 917 #define FP_DENORM_FLUSH_OUT 1 918 #define FP_DENORM_FLUSH_IN 2 919 #define FP_DENORM_FLUSH_NONE 3 920 921 922 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double 923 // precision. 924 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4) 925 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6) 926 927 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 928 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12) 929 930 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 931 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) 932 933 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54 934 #define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21) 935 #define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22) 936 #define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23) 937 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8 938 #define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15) 939 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800 940 #define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15) 941 942 #define R_SPILLED_SGPRS 0x4 943 #define R_SPILLED_VGPRS 0x8 944 } // End namespace llvm 945 946 #endif 947