1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // The file contains the R600 implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "R600RegisterInfo.h"
15 #include "AMDGPUTargetMachine.h"
16 #include "R600MachineFunctionInfo.h"
17 
18 using namespace llvm;
19 
20 R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm,
21     const TargetInstrInfo &tii)
22 : AMDGPURegisterInfo(tm, tii),
23   TM(tm),
24   TII(tii)
25   { }
26 
27 BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const
28 {
29   BitVector Reserved(getNumRegs());
30   const R600MachineFunctionInfo * MFI = MF.getInfo<R600MachineFunctionInfo>();
31 
32   Reserved.set(AMDGPU::ZERO);
33   Reserved.set(AMDGPU::HALF);
34   Reserved.set(AMDGPU::ONE);
35   Reserved.set(AMDGPU::ONE_INT);
36   Reserved.set(AMDGPU::NEG_HALF);
37   Reserved.set(AMDGPU::NEG_ONE);
38   Reserved.set(AMDGPU::PV_X);
39   Reserved.set(AMDGPU::ALU_LITERAL_X);
40 
41   for (TargetRegisterClass::iterator I = AMDGPU::R600_CReg32RegClass.begin(),
42                         E = AMDGPU::R600_CReg32RegClass.end(); I != E; ++I) {
43     Reserved.set(*I);
44   }
45 
46   for (std::vector<unsigned>::const_iterator I = MFI->ReservedRegs.begin(),
47                                     E = MFI->ReservedRegs.end(); I != E; ++I) {
48     Reserved.set(*I);
49   }
50 
51   return Reserved;
52 }
53 
54 const TargetRegisterClass *
55 R600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const
56 {
57   switch (rc->getID()) {
58   case AMDGPU::GPRF32RegClassID:
59   case AMDGPU::GPRI32RegClassID:
60     return &AMDGPU::R600_Reg32RegClass;
61   default: return rc;
62   }
63 }
64 
65 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const
66 {
67   switch(reg) {
68   case AMDGPU::ZERO:
69   case AMDGPU::ONE:
70   case AMDGPU::ONE_INT:
71   case AMDGPU::NEG_ONE:
72   case AMDGPU::HALF:
73   case AMDGPU::NEG_HALF:
74   case AMDGPU::ALU_LITERAL_X:
75     return 0;
76   default: return getHWRegChanGen(reg);
77   }
78 }
79 
80 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
81                                                                    MVT VT) const
82 {
83   switch(VT.SimpleTy) {
84   default:
85   case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
86   }
87 }
88 #include "R600HwRegInfo.include"
89