1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// R600 implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "R600RegisterInfo.h"
15 #include "AMDGPUTargetMachine.h"
16 #include "R600Defines.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineFunctionInfo.h"
19 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
20 
21 using namespace llvm;
22 
23 R600RegisterInfo::R600RegisterInfo() : R600GenRegisterInfo(0) {
24   RCW.RegWeight = 0;
25   RCW.WeightLimit = 0;
26 }
27 
28 #define GET_REGINFO_TARGET_DESC
29 #include "R600GenRegisterInfo.inc"
30 
31 unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) {
32   static const uint16_t SubRegFromChannelTable[] = {
33     R600::sub0, R600::sub1, R600::sub2, R600::sub3,
34     R600::sub4, R600::sub5, R600::sub6, R600::sub7,
35     R600::sub8, R600::sub9, R600::sub10, R600::sub11,
36     R600::sub12, R600::sub13, R600::sub14, R600::sub15
37   };
38 
39   assert(Channel < array_lengthof(SubRegFromChannelTable));
40   return SubRegFromChannelTable[Channel];
41 }
42 
43 BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
44   BitVector Reserved(getNumRegs());
45 
46   const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
47   const R600InstrInfo *TII = ST.getInstrInfo();
48 
49   reserveRegisterTuples(Reserved, R600::ZERO);
50   reserveRegisterTuples(Reserved, R600::HALF);
51   reserveRegisterTuples(Reserved, R600::ONE);
52   reserveRegisterTuples(Reserved, R600::ONE_INT);
53   reserveRegisterTuples(Reserved, R600::NEG_HALF);
54   reserveRegisterTuples(Reserved, R600::NEG_ONE);
55   reserveRegisterTuples(Reserved, R600::PV_X);
56   reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X);
57   reserveRegisterTuples(Reserved, R600::ALU_CONST);
58   reserveRegisterTuples(Reserved, R600::PREDICATE_BIT);
59   reserveRegisterTuples(Reserved, R600::PRED_SEL_OFF);
60   reserveRegisterTuples(Reserved, R600::PRED_SEL_ZERO);
61   reserveRegisterTuples(Reserved, R600::PRED_SEL_ONE);
62   reserveRegisterTuples(Reserved, R600::INDIRECT_BASE_ADDR);
63 
64   for (TargetRegisterClass::iterator I = R600::R600_AddrRegClass.begin(),
65                         E = R600::R600_AddrRegClass.end(); I != E; ++I) {
66     reserveRegisterTuples(Reserved, *I);
67   }
68 
69   TII->reserveIndirectRegisters(Reserved, MF, *this);
70 
71   return Reserved;
72 }
73 
74 // Dummy to not crash RegisterClassInfo.
75 static const MCPhysReg CalleeSavedReg = R600::NoRegister;
76 
77 const MCPhysReg *R600RegisterInfo::getCalleeSavedRegs(
78   const MachineFunction *) const {
79   return &CalleeSavedReg;
80 }
81 
82 Register R600RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
83   return R600::NoRegister;
84 }
85 
86 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
87   return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
88 }
89 
90 unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const {
91   return GET_REG_INDEX(getEncodingValue(Reg));
92 }
93 
94 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
95                                                                    MVT VT) const {
96   switch(VT.SimpleTy) {
97   default:
98   case MVT::i32: return &R600::R600_TReg32RegClass;
99   }
100 }
101 
102 const RegClassWeight &R600RegisterInfo::getRegClassWeight(
103   const TargetRegisterClass *RC) const {
104   return RCW;
105 }
106 
107 bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const {
108   assert(!Register::isVirtualRegister(Reg));
109 
110   switch (Reg) {
111   case R600::OQAP:
112   case R600::OQBP:
113   case R600::AR_X:
114     return false;
115   default:
116     return true;
117   }
118 }
119 
120 void R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
121                                            int SPAdj,
122                                            unsigned FIOperandNum,
123                                            RegScavenger *RS) const {
124   llvm_unreachable("Subroutines not supported yet");
125 }
126 
127 void R600RegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
128   MCRegAliasIterator R(Reg, this, true);
129 
130   for (; R.isValid(); ++R)
131     Reserved.set(*R);
132 }
133