1 //===----- R600Packetizer.cpp - VLIW packetizer ---------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// This pass implements instructions packetization for R600. It unsets isLast
12 /// bit of instructions inside a bundle and substitutes src register with
13 /// PreviousVector when applicable.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "llvm/Support/Debug.h"
18 #include "AMDGPU.h"
19 #include "AMDGPUSubtarget.h"
20 #include "R600InstrInfo.h"
21 #include "llvm/CodeGen/DFAPacketizer.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/ScheduleDAG.h"
27 #include "llvm/Support/raw_ostream.h"
28 
29 using namespace llvm;
30 
31 #define DEBUG_TYPE "packets"
32 
33 namespace {
34 
35 class R600Packetizer : public MachineFunctionPass {
36 
37 public:
38   static char ID;
39   R600Packetizer(const TargetMachine &TM) : MachineFunctionPass(ID) {}
40 
41   void getAnalysisUsage(AnalysisUsage &AU) const override {
42     AU.setPreservesCFG();
43     AU.addRequired<MachineDominatorTree>();
44     AU.addPreserved<MachineDominatorTree>();
45     AU.addRequired<MachineLoopInfo>();
46     AU.addPreserved<MachineLoopInfo>();
47     MachineFunctionPass::getAnalysisUsage(AU);
48   }
49 
50   const char *getPassName() const override {
51     return "R600 Packetizer";
52   }
53 
54   bool runOnMachineFunction(MachineFunction &Fn) override;
55 };
56 char R600Packetizer::ID = 0;
57 
58 class R600PacketizerList : public VLIWPacketizerList {
59 
60 private:
61   const R600InstrInfo *TII;
62   const R600RegisterInfo &TRI;
63   bool VLIW5;
64   bool ConsideredInstUsesAlreadyWrittenVectorElement;
65 
66   unsigned getSlot(const MachineInstr *MI) const {
67     return TRI.getHWRegChan(MI->getOperand(0).getReg());
68   }
69 
70   /// \returns register to PV chan mapping for bundle/single instructions that
71   /// immediately precedes I.
72   DenseMap<unsigned, unsigned> getPreviousVector(MachineBasicBlock::iterator I)
73       const {
74     DenseMap<unsigned, unsigned> Result;
75     I--;
76     if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle())
77       return Result;
78     MachineBasicBlock::instr_iterator BI = I.getInstrIterator();
79     if (I->isBundle())
80       BI++;
81     int LastDstChan = -1;
82     do {
83       bool isTrans = false;
84       int BISlot = getSlot(&*BI);
85       if (LastDstChan >= BISlot)
86         isTrans = true;
87       LastDstChan = BISlot;
88       if (TII->isPredicated(&*BI))
89         continue;
90       int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write);
91       if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm() == 0)
92         continue;
93       int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst);
94       if (DstIdx == -1) {
95         continue;
96       }
97       unsigned Dst = BI->getOperand(DstIdx).getReg();
98       if (isTrans || TII->isTransOnly(&*BI)) {
99         Result[Dst] = AMDGPU::PS;
100         continue;
101       }
102       if (BI->getOpcode() == AMDGPU::DOT4_r600 ||
103           BI->getOpcode() == AMDGPU::DOT4_eg) {
104         Result[Dst] = AMDGPU::PV_X;
105         continue;
106       }
107       if (Dst == AMDGPU::OQAP) {
108         continue;
109       }
110       unsigned PVReg = 0;
111       switch (TRI.getHWRegChan(Dst)) {
112       case 0:
113         PVReg = AMDGPU::PV_X;
114         break;
115       case 1:
116         PVReg = AMDGPU::PV_Y;
117         break;
118       case 2:
119         PVReg = AMDGPU::PV_Z;
120         break;
121       case 3:
122         PVReg = AMDGPU::PV_W;
123         break;
124       default:
125         llvm_unreachable("Invalid Chan");
126       }
127       Result[Dst] = PVReg;
128     } while ((++BI)->isBundledWithPred());
129     return Result;
130   }
131 
132   void substitutePV(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PVs)
133       const {
134     unsigned Ops[] = {
135       AMDGPU::OpName::src0,
136       AMDGPU::OpName::src1,
137       AMDGPU::OpName::src2
138     };
139     for (unsigned i = 0; i < 3; i++) {
140       int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]);
141       if (OperandIdx < 0)
142         continue;
143       unsigned Src = MI->getOperand(OperandIdx).getReg();
144       const DenseMap<unsigned, unsigned>::const_iterator It = PVs.find(Src);
145       if (It != PVs.end())
146         MI->getOperand(OperandIdx).setReg(It->second);
147     }
148   }
149 public:
150   // Ctor.
151   R600PacketizerList(MachineFunction &MF, MachineLoopInfo &MLI)
152       : VLIWPacketizerList(MF, MLI), TII(static_cast<const R600InstrInfo *>(
153             MF.getSubtarget().getInstrInfo())),
154         TRI(TII->getRegisterInfo()) {
155     VLIW5 = !MF.getSubtarget<AMDGPUSubtarget>().hasCaymanISA();
156   }
157 
158   // initPacketizerState - initialize some internal flags.
159   void initPacketizerState() override {
160     ConsideredInstUsesAlreadyWrittenVectorElement = false;
161   }
162 
163   // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
164   bool ignorePseudoInstruction(MachineInstr *MI,
165                                MachineBasicBlock *MBB) override {
166     return false;
167   }
168 
169   // isSoloInstruction - return true if instruction MI can not be packetized
170   // with any other instruction, which means that MI itself is a packet.
171   bool isSoloInstruction(MachineInstr *MI) override {
172     if (TII->isVector(*MI))
173       return true;
174     if (!TII->isALUInstr(MI->getOpcode()))
175       return true;
176     if (MI->getOpcode() == AMDGPU::GROUP_BARRIER)
177       return true;
178     // XXX: This can be removed once the packetizer properly handles all the
179     // LDS instruction group restrictions.
180     if (TII->isLDSInstr(MI->getOpcode()))
181       return true;
182     return false;
183   }
184 
185   // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
186   // together.
187   bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override {
188     MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr();
189     if (getSlot(MII) == getSlot(MIJ))
190       ConsideredInstUsesAlreadyWrittenVectorElement = true;
191     // Does MII and MIJ share the same pred_sel ?
192     int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGPU::OpName::pred_sel),
193         OpJ = TII->getOperandIdx(MIJ->getOpcode(), AMDGPU::OpName::pred_sel);
194     unsigned PredI = (OpI > -1)?MII->getOperand(OpI).getReg():0,
195         PredJ = (OpJ > -1)?MIJ->getOperand(OpJ).getReg():0;
196     if (PredI != PredJ)
197       return false;
198     if (SUJ->isSucc(SUI)) {
199       for (unsigned i = 0, e = SUJ->Succs.size(); i < e; ++i) {
200         const SDep &Dep = SUJ->Succs[i];
201         if (Dep.getSUnit() != SUI)
202           continue;
203         if (Dep.getKind() == SDep::Anti)
204           continue;
205         if (Dep.getKind() == SDep::Output)
206           if (MII->getOperand(0).getReg() != MIJ->getOperand(0).getReg())
207             continue;
208         return false;
209       }
210     }
211 
212     bool ARDef = TII->definesAddressRegister(MII) ||
213                  TII->definesAddressRegister(MIJ);
214     bool ARUse = TII->usesAddressRegister(MII) ||
215                  TII->usesAddressRegister(MIJ);
216     if (ARDef && ARUse)
217       return false;
218 
219     return true;
220   }
221 
222   // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
223   // and SUJ.
224   bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override {
225     return false;
226   }
227 
228   void setIsLastBit(MachineInstr *MI, unsigned Bit) const {
229     unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::last);
230     MI->getOperand(LastOp).setImm(Bit);
231   }
232 
233   bool isBundlableWithCurrentPMI(MachineInstr *MI,
234                                  const DenseMap<unsigned, unsigned> &PV,
235                                  std::vector<R600InstrInfo::BankSwizzle> &BS,
236                                  bool &isTransSlot) {
237     isTransSlot = TII->isTransOnly(MI);
238     assert (!isTransSlot || VLIW5);
239 
240     // Is the dst reg sequence legal ?
241     if (!isTransSlot && !CurrentPacketMIs.empty()) {
242       if (getSlot(MI) <= getSlot(CurrentPacketMIs.back())) {
243         if (ConsideredInstUsesAlreadyWrittenVectorElement  &&
244             !TII->isVectorOnly(MI) && VLIW5) {
245           isTransSlot = true;
246           DEBUG(dbgs() << "Considering as Trans Inst :"; MI->dump(););
247         }
248         else
249           return false;
250       }
251     }
252 
253     // Are the Constants limitations met ?
254     CurrentPacketMIs.push_back(MI);
255     if (!TII->fitsConstReadLimitations(CurrentPacketMIs)) {
256       DEBUG(
257         dbgs() << "Couldn't pack :\n";
258         MI->dump();
259         dbgs() << "with the following packets :\n";
260         for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) {
261           CurrentPacketMIs[i]->dump();
262           dbgs() << "\n";
263         }
264         dbgs() << "because of Consts read limitations\n";
265       );
266       CurrentPacketMIs.pop_back();
267       return false;
268     }
269 
270     // Is there a BankSwizzle set that meet Read Port limitations ?
271     if (!TII->fitsReadPortLimitations(CurrentPacketMIs,
272             PV, BS, isTransSlot)) {
273       DEBUG(
274         dbgs() << "Couldn't pack :\n";
275         MI->dump();
276         dbgs() << "with the following packets :\n";
277         for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) {
278           CurrentPacketMIs[i]->dump();
279           dbgs() << "\n";
280         }
281         dbgs() << "because of Read port limitations\n";
282       );
283       CurrentPacketMIs.pop_back();
284       return false;
285     }
286 
287     // We cannot read LDS source registrs from the Trans slot.
288     if (isTransSlot && TII->readsLDSSrcReg(MI))
289       return false;
290 
291     CurrentPacketMIs.pop_back();
292     return true;
293   }
294 
295   MachineBasicBlock::iterator addToPacket(MachineInstr *MI) override {
296     MachineBasicBlock::iterator FirstInBundle =
297         CurrentPacketMIs.empty() ? MI : CurrentPacketMIs.front();
298     const DenseMap<unsigned, unsigned> &PV =
299         getPreviousVector(FirstInBundle);
300     std::vector<R600InstrInfo::BankSwizzle> BS;
301     bool isTransSlot;
302 
303     if (isBundlableWithCurrentPMI(MI, PV, BS, isTransSlot)) {
304       for (unsigned i = 0, e = CurrentPacketMIs.size(); i < e; i++) {
305         MachineInstr *MI = CurrentPacketMIs[i];
306         unsigned Op = TII->getOperandIdx(MI->getOpcode(),
307             AMDGPU::OpName::bank_swizzle);
308         MI->getOperand(Op).setImm(BS[i]);
309       }
310       unsigned Op = TII->getOperandIdx(MI->getOpcode(),
311           AMDGPU::OpName::bank_swizzle);
312       MI->getOperand(Op).setImm(BS.back());
313       if (!CurrentPacketMIs.empty())
314         setIsLastBit(CurrentPacketMIs.back(), 0);
315       substitutePV(MI, PV);
316       MachineBasicBlock::iterator It = VLIWPacketizerList::addToPacket(MI);
317       if (isTransSlot) {
318         endPacket(std::next(It)->getParent(), std::next(It));
319       }
320       return It;
321     }
322     endPacket(MI->getParent(), MI);
323     if (TII->isTransOnly(MI))
324       return MI;
325     return VLIWPacketizerList::addToPacket(MI);
326   }
327 };
328 
329 bool R600Packetizer::runOnMachineFunction(MachineFunction &Fn) {
330   const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
331   MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
332 
333   // Instantiate the packetizer.
334   R600PacketizerList Packetizer(Fn, MLI);
335 
336   // DFA state table should not be empty.
337   assert(Packetizer.getResourceTracker() && "Empty DFA table!");
338 
339   //
340   // Loop over all basic blocks and remove KILL pseudo-instructions
341   // These instructions confuse the dependence analysis. Consider:
342   // D0 = ...   (Insn 0)
343   // R0 = KILL R0, D0 (Insn 1)
344   // R0 = ... (Insn 2)
345   // Here, Insn 1 will result in the dependence graph not emitting an output
346   // dependence between Insn 0 and Insn 2. This can lead to incorrect
347   // packetization
348   //
349   for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
350        MBB != MBBe; ++MBB) {
351     MachineBasicBlock::iterator End = MBB->end();
352     MachineBasicBlock::iterator MI = MBB->begin();
353     while (MI != End) {
354       if (MI->isKill() || MI->getOpcode() == AMDGPU::IMPLICIT_DEF ||
355           (MI->getOpcode() == AMDGPU::CF_ALU && !MI->getOperand(8).getImm())) {
356         MachineBasicBlock::iterator DeleteMI = MI;
357         ++MI;
358         MBB->erase(DeleteMI);
359         End = MBB->end();
360         continue;
361       }
362       ++MI;
363     }
364   }
365 
366   // Loop over all of the basic blocks.
367   for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
368        MBB != MBBe; ++MBB) {
369     // Find scheduling regions and schedule / packetize each region.
370     unsigned RemainingCount = MBB->size();
371     for(MachineBasicBlock::iterator RegionEnd = MBB->end();
372         RegionEnd != MBB->begin();) {
373       // The next region starts above the previous region. Look backward in the
374       // instruction stream until we find the nearest boundary.
375       MachineBasicBlock::iterator I = RegionEnd;
376       for(;I != MBB->begin(); --I, --RemainingCount) {
377         if (TII->isSchedulingBoundary(&*std::prev(I), &*MBB, Fn))
378           break;
379       }
380       I = MBB->begin();
381 
382       // Skip empty scheduling regions.
383       if (I == RegionEnd) {
384         RegionEnd = std::prev(RegionEnd);
385         --RemainingCount;
386         continue;
387       }
388       // Skip regions with one instruction.
389       if (I == std::prev(RegionEnd)) {
390         RegionEnd = std::prev(RegionEnd);
391         continue;
392       }
393 
394       Packetizer.PacketizeMIs(&*MBB, &*I, RegionEnd);
395       RegionEnd = I;
396     }
397   }
398 
399   return true;
400 
401 }
402 
403 } // end anonymous namespace
404 
405 llvm::FunctionPass *llvm::createR600Packetizer(TargetMachine &tm) {
406   return new R600Packetizer(tm);
407 }
408