1 //===-- R600MachineScheduler.h - R600 Scheduler Interface -*- C++ -*-------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief R600 Machine Scheduler interface
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H
16 #define LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H
17 
18 #include "R600InstrInfo.h"
19 #include "llvm/CodeGen/MachineScheduler.h"
20 
21 using namespace llvm;
22 
23 namespace llvm {
24 
25 class R600SchedStrategy final : public MachineSchedStrategy {
26 
27   const ScheduleDAGMILive *DAG;
28   const R600InstrInfo *TII;
29   const R600RegisterInfo *TRI;
30   MachineRegisterInfo *MRI;
31 
32   enum InstKind {
33     IDAlu,
34     IDFetch,
35     IDOther,
36     IDLast
37   };
38 
39   enum AluKind {
40     AluAny,
41     AluT_X,
42     AluT_Y,
43     AluT_Z,
44     AluT_W,
45     AluT_XYZW,
46     AluPredX,
47     AluTrans,
48     AluDiscarded, // LLVM Instructions that are going to be eliminated
49     AluLast
50   };
51 
52   std::vector<SUnit *> Available[IDLast], Pending[IDLast];
53   std::vector<SUnit *> AvailableAlus[AluLast];
54   std::vector<SUnit *> PhysicalRegCopy;
55 
56   InstKind CurInstKind;
57   int CurEmitted;
58   InstKind NextInstKind;
59 
60   unsigned AluInstCount;
61   unsigned FetchInstCount;
62 
63   int InstKindLimit[IDLast];
64 
65   int OccupedSlotsMask;
66 
67 public:
68   R600SchedStrategy() :
69     DAG(nullptr), TII(nullptr), TRI(nullptr), MRI(nullptr) {
70   }
71 
72   virtual ~R600SchedStrategy() {}
73 
74   void initialize(ScheduleDAGMI *dag) override;
75   SUnit *pickNode(bool &IsTopNode) override;
76   void schedNode(SUnit *SU, bool IsTopNode) override;
77   void releaseTopNode(SUnit *SU) override;
78   void releaseBottomNode(SUnit *SU) override;
79 
80 private:
81   std::vector<MachineInstr *> InstructionsGroupCandidate;
82   bool VLIW5;
83 
84   int getInstKind(SUnit *SU);
85   bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const;
86   AluKind getAluKind(SUnit *SU) const;
87   void LoadAlu();
88   unsigned AvailablesAluCount() const;
89   SUnit *AttemptFillSlot (unsigned Slot, bool AnyAlu);
90   void PrepareNextSlot();
91   SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);
92 
93   void AssignSlot(MachineInstr *MI, unsigned Slot);
94   SUnit* pickAlu();
95   SUnit* pickOther(int QID);
96   void MoveUnits(std::vector<SUnit *> &QSrc, std::vector<SUnit *> &QDst);
97 };
98 
99 } // namespace llvm
100 
101 #endif /* R600MACHINESCHEDULER_H_ */
102