1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition for R600InstrInfo
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
17 
18 #include "AMDGPUInstrInfo.h"
19 #include "R600RegisterInfo.h"
20 
21 namespace llvm {
22 class AMDGPUTargetMachine;
23 class DFAPacketizer;
24 class MachineFunction;
25 class MachineInstr;
26 class MachineInstrBuilder;
27 class R600Subtarget;
28 
29 class R600InstrInfo final : public AMDGPUInstrInfo {
30 private:
31   const R600RegisterInfo RI;
32   const R600Subtarget &ST;
33 
34   std::vector<std::pair<int, unsigned>>
35   ExtractSrcs(MachineInstr *MI,
36               const DenseMap<unsigned, unsigned> &PV,
37               unsigned &ConstCount) const;
38 
39   MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
40                                         MachineBasicBlock::iterator I,
41                                         unsigned ValueReg, unsigned Address,
42                                         unsigned OffsetReg,
43                                         unsigned AddrChan) const;
44 
45   MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
46                                          MachineBasicBlock::iterator I,
47                                          unsigned ValueReg, unsigned Address,
48                                          unsigned OffsetReg,
49                                          unsigned AddrChan) const;
50 public:
51   enum BankSwizzle {
52     ALU_VEC_012_SCL_210 = 0,
53     ALU_VEC_021_SCL_122,
54     ALU_VEC_120_SCL_212,
55     ALU_VEC_102_SCL_221,
56     ALU_VEC_201,
57     ALU_VEC_210
58   };
59 
60   explicit R600InstrInfo(const R600Subtarget &);
61 
62   const R600RegisterInfo &getRegisterInfo() const {
63     return RI;
64   }
65 
66   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
67                    const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
68                    bool KillSrc) const override;
69   bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
70                            MachineBasicBlock::iterator MBBI) const override;
71 
72   bool isTrig(const MachineInstr &MI) const;
73   bool isPlaceHolderOpcode(unsigned opcode) const;
74   bool isReductionOp(unsigned opcode) const;
75   bool isCubeOp(unsigned opcode) const;
76 
77   /// \returns true if this \p Opcode represents an ALU instruction.
78   bool isALUInstr(unsigned Opcode) const;
79   bool hasInstrModifiers(unsigned Opcode) const;
80   bool isLDSInstr(unsigned Opcode) const;
81   bool isLDSNoRetInstr(unsigned Opcode) const;
82   bool isLDSRetInstr(unsigned Opcode) const;
83 
84   /// \returns true if this \p Opcode represents an ALU instruction or an
85   /// instruction that will be lowered in ExpandSpecialInstrs Pass.
86   bool canBeConsideredALU(const MachineInstr *MI) const;
87 
88   bool isTransOnly(unsigned Opcode) const;
89   bool isTransOnly(const MachineInstr *MI) const;
90   bool isVectorOnly(unsigned Opcode) const;
91   bool isVectorOnly(const MachineInstr *MI) const;
92   bool isExport(unsigned Opcode) const;
93 
94   bool usesVertexCache(unsigned Opcode) const;
95   bool usesVertexCache(const MachineInstr *MI) const;
96   bool usesTextureCache(unsigned Opcode) const;
97   bool usesTextureCache(const MachineInstr *MI) const;
98 
99   bool mustBeLastInClause(unsigned Opcode) const;
100   bool usesAddressRegister(MachineInstr *MI) const;
101   bool definesAddressRegister(MachineInstr *MI) const;
102   bool readsLDSSrcReg(const MachineInstr *MI) const;
103 
104   /// \returns The operand index for the given source number.  Legal values
105   /// for SrcNum are 0, 1, and 2.
106   int getSrcIdx(unsigned Opcode, unsigned SrcNum) const;
107   /// \returns The operand Index for the Sel operand given an index to one
108   /// of the instruction's src operands.
109   int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
110 
111   /// \returns a pair for each src of an ALU instructions.
112   /// The first member of a pair is the register id.
113   /// If register is ALU_CONST, second member is SEL.
114   /// If register is ALU_LITERAL, second member is IMM.
115   /// Otherwise, second member value is undefined.
116   SmallVector<std::pair<MachineOperand *, int64_t>, 3>
117   getSrcs(MachineInstr *MI) const;
118 
119   unsigned  isLegalUpTo(
120     const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
121     const std::vector<R600InstrInfo::BankSwizzle> &Swz,
122     const std::vector<std::pair<int, unsigned> > &TransSrcs,
123     R600InstrInfo::BankSwizzle TransSwz) const;
124 
125   bool FindSwizzleForVectorSlot(
126     const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
127     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
128     const std::vector<std::pair<int, unsigned> > &TransSrcs,
129     R600InstrInfo::BankSwizzle TransSwz) const;
130 
131   /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
132   /// returns true and the first (in lexical order) BankSwizzle affectation
133   /// starting from the one already provided in the Instruction Group MIs that
134   /// fits Read Port limitations in BS if available. Otherwise returns false
135   /// and undefined content in BS.
136   /// isLastAluTrans should be set if the last Alu of MIs will be executed on
137   /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
138   /// apply to the last instruction.
139   /// PV holds GPR to PV registers in the Instruction Group MIs.
140   bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
141                                const DenseMap<unsigned, unsigned> &PV,
142                                std::vector<BankSwizzle> &BS,
143                                bool isLastAluTrans) const;
144 
145   /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
146   /// from KCache bank on R700+. This function check if MI set in input meet
147   /// this limitations
148   bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
149   /// Same but using const index set instead of MI set.
150   bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
151 
152   /// \brief Vector instructions are instructions that must fill all
153   /// instruction slots within an instruction group.
154   bool isVector(const MachineInstr &MI) const;
155 
156   bool isMov(unsigned Opcode) const;
157 
158   DFAPacketizer *
159   CreateTargetScheduleState(const TargetSubtargetInfo &) const override;
160 
161   bool ReverseBranchCondition(
162     SmallVectorImpl<MachineOperand> &Cond) const override;
163 
164   bool AnalyzeBranch(MachineBasicBlock &MBB,
165                      MachineBasicBlock *&TBB,
166                      MachineBasicBlock *&FBB,
167                      SmallVectorImpl<MachineOperand> &Cond,
168                      bool AllowModify) const override;
169 
170   unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
171                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
172                         const DebugLoc &DL) const override;
173 
174   unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
175 
176   bool isPredicated(const MachineInstr &MI) const override;
177 
178   bool isPredicable(MachineInstr &MI) const override;
179 
180   bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
181                                  BranchProbability Probability) const override;
182 
183   bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
184                            unsigned ExtraPredCycles,
185                            BranchProbability Probability) const override ;
186 
187   bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
188                            unsigned NumTCycles, unsigned ExtraTCycles,
189                            MachineBasicBlock &FMBB,
190                            unsigned NumFCycles, unsigned ExtraFCycles,
191                            BranchProbability Probability) const override;
192 
193   bool DefinesPredicate(MachineInstr &MI,
194                         std::vector<MachineOperand> &Pred) const override;
195 
196   bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
197                          ArrayRef<MachineOperand> Pred2) const override;
198 
199   bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
200                                  MachineBasicBlock &FMBB) const override;
201 
202   bool PredicateInstruction(MachineInstr &MI,
203                             ArrayRef<MachineOperand> Pred) const override;
204 
205   unsigned int getPredicationCost(const MachineInstr &) const override;
206 
207   unsigned int getInstrLatency(const InstrItineraryData *ItinData,
208                                const MachineInstr *MI,
209                                unsigned *PredCost = nullptr) const override;
210 
211   int getInstrLatency(const InstrItineraryData *ItinData,
212                       SDNode *Node) const override { return 1;}
213 
214   bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
215 
216   /// \brief Reserve the registers that may be accesed using indirect addressing.
217   void reserveIndirectRegisters(BitVector &Reserved,
218                                 const MachineFunction &MF) const;
219 
220   /// Calculate the "Indirect Address" for the given \p RegIndex and
221   /// \p Channel
222   ///
223   /// We model indirect addressing using a virtual address space that can be
224   /// accesed with loads and stores.  The "Indirect Address" is the memory
225   /// address in this virtual address space that maps to the given \p RegIndex
226   /// and \p Channel.
227   unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const;
228 
229 
230   const TargetRegisterClass *getIndirectAddrRegClass() const override;
231 
232   /// \brief Build instruction(s) for an indirect register write.
233   ///
234   /// \returns The instruction that performs the indirect register write
235   MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
236                                          MachineBasicBlock::iterator I,
237                                          unsigned ValueReg, unsigned Address,
238                                          unsigned OffsetReg) const;
239 
240   /// \brief Build instruction(s) for an indirect register read.
241   ///
242   /// \returns The instruction that performs the indirect register read
243   MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
244                                         MachineBasicBlock::iterator I,
245                                         unsigned ValueReg, unsigned Address,
246                                         unsigned OffsetReg) const;
247 
248   unsigned getMaxAlusPerClause() const;
249 
250   /// buildDefaultInstruction - This function returns a MachineInstr with all
251   /// the instruction modifiers initialized to their default values.  You can
252   /// use this function to avoid manually specifying each instruction modifier
253   /// operand when building a new instruction.
254   ///
255   /// \returns a MachineInstr with all the instruction modifiers initialized
256   /// to their default values.
257   MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
258                                               MachineBasicBlock::iterator I,
259                                               unsigned Opcode,
260                                               unsigned DstReg,
261                                               unsigned Src0Reg,
262                                               unsigned Src1Reg = 0) const;
263 
264   MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
265                                              MachineInstr *MI,
266                                              unsigned Slot,
267                                              unsigned DstReg) const;
268 
269   MachineInstr *buildMovImm(MachineBasicBlock &BB,
270                             MachineBasicBlock::iterator I,
271                             unsigned DstReg,
272                             uint64_t Imm) const;
273 
274   MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
275                               MachineBasicBlock::iterator I,
276                               unsigned DstReg, unsigned SrcReg) const;
277 
278   /// \brief Get the index of Op in the MachineInstr.
279   ///
280   /// \returns -1 if the Instruction does not contain the specified \p Op.
281   int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
282 
283   /// \brief Get the index of \p Op for the given Opcode.
284   ///
285   /// \returns -1 if the Instruction does not contain the specified \p Op.
286   int getOperandIdx(unsigned Opcode, unsigned Op) const;
287 
288   /// \brief Helper function for setting instruction flag values.
289   void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const;
290 
291   /// \returns true if this instruction has an operand for storing target flags.
292   bool hasFlagOperand(const MachineInstr &MI) const;
293 
294   ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
295   void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
296 
297   ///\brief Determine if the specified \p Flag is set on this \p Operand.
298   bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
299 
300   /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
301   /// \param Flag The flag being set.
302   ///
303   /// \returns the operand containing the flags for this instruction.
304   MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
305                             unsigned Flag = 0) const;
306 
307   /// \brief Clear the specified flag on the instruction.
308   void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
309 
310   // Helper functions that check the opcode for status information
311   bool isRegisterStore(const MachineInstr &MI) const;
312   bool isRegisterLoad(const MachineInstr &MI) const;
313 };
314 
315 namespace AMDGPU {
316 
317 int getLDSNoRetOp(uint16_t Opcode);
318 
319 } //End namespace AMDGPU
320 
321 } // End llvm namespace
322 
323 #endif
324