1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition for R600InstrInfo
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
17 
18 #include "AMDGPUInstrInfo.h"
19 #include "R600Defines.h"
20 #include "R600RegisterInfo.h"
21 #include <map>
22 
23 namespace llvm {
24   class AMDGPUTargetMachine;
25   class DFAPacketizer;
26   class MachineFunction;
27   class MachineInstr;
28   class MachineInstrBuilder;
29 
30   class R600InstrInfo final : public AMDGPUInstrInfo {
31   private:
32   const R600RegisterInfo RI;
33 
34   std::vector<std::pair<int, unsigned> >
35   ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
36 
37 
38   MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
39                                         MachineBasicBlock::iterator I,
40                                         unsigned ValueReg, unsigned Address,
41                                         unsigned OffsetReg,
42                                         unsigned AddrChan) const;
43 
44   MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
45                                         MachineBasicBlock::iterator I,
46                                         unsigned ValueReg, unsigned Address,
47                                         unsigned OffsetReg,
48                                         unsigned AddrChan) const;
49   public:
50   enum BankSwizzle {
51     ALU_VEC_012_SCL_210 = 0,
52     ALU_VEC_021_SCL_122,
53     ALU_VEC_120_SCL_212,
54     ALU_VEC_102_SCL_221,
55     ALU_VEC_201,
56     ALU_VEC_210
57   };
58 
59   explicit R600InstrInfo(const AMDGPUSubtarget &st);
60 
61   const R600RegisterInfo &getRegisterInfo() const override;
62   void copyPhysReg(MachineBasicBlock &MBB,
63                    MachineBasicBlock::iterator MI, DebugLoc DL,
64                    unsigned DestReg, unsigned SrcReg,
65                    bool KillSrc) const override;
66   bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
67                            MachineBasicBlock::iterator MBBI) const override;
68 
69   bool isTrig(const MachineInstr &MI) const;
70   bool isPlaceHolderOpcode(unsigned opcode) const;
71   bool isReductionOp(unsigned opcode) const;
72   bool isCubeOp(unsigned opcode) const;
73 
74   /// \returns true if this \p Opcode represents an ALU instruction.
75   bool isALUInstr(unsigned Opcode) const;
76   bool hasInstrModifiers(unsigned Opcode) const;
77   bool isLDSInstr(unsigned Opcode) const;
78   bool isLDSNoRetInstr(unsigned Opcode) const;
79   bool isLDSRetInstr(unsigned Opcode) const;
80 
81   /// \returns true if this \p Opcode represents an ALU instruction or an
82   /// instruction that will be lowered in ExpandSpecialInstrs Pass.
83   bool canBeConsideredALU(const MachineInstr *MI) const;
84 
85   bool isTransOnly(unsigned Opcode) const;
86   bool isTransOnly(const MachineInstr *MI) const;
87   bool isVectorOnly(unsigned Opcode) const;
88   bool isVectorOnly(const MachineInstr *MI) const;
89   bool isExport(unsigned Opcode) const;
90 
91   bool usesVertexCache(unsigned Opcode) const;
92   bool usesVertexCache(const MachineInstr *MI) const;
93   bool usesTextureCache(unsigned Opcode) const;
94   bool usesTextureCache(const MachineInstr *MI) const;
95 
96   bool mustBeLastInClause(unsigned Opcode) const;
97   bool usesAddressRegister(MachineInstr *MI) const;
98   bool definesAddressRegister(MachineInstr *MI) const;
99   bool readsLDSSrcReg(const MachineInstr *MI) const;
100 
101   /// \returns The operand index for the given source number.  Legal values
102   /// for SrcNum are 0, 1, and 2.
103   int getSrcIdx(unsigned Opcode, unsigned SrcNum) const;
104   /// \returns The operand Index for the Sel operand given an index to one
105   /// of the instruction's src operands.
106   int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
107 
108   /// \returns a pair for each src of an ALU instructions.
109   /// The first member of a pair is the register id.
110   /// If register is ALU_CONST, second member is SEL.
111   /// If register is ALU_LITERAL, second member is IMM.
112   /// Otherwise, second member value is undefined.
113   SmallVector<std::pair<MachineOperand *, int64_t>, 3>
114       getSrcs(MachineInstr *MI) const;
115 
116   unsigned  isLegalUpTo(
117     const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
118     const std::vector<R600InstrInfo::BankSwizzle> &Swz,
119     const std::vector<std::pair<int, unsigned> > &TransSrcs,
120     R600InstrInfo::BankSwizzle TransSwz) const;
121 
122   bool FindSwizzleForVectorSlot(
123     const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
124     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
125     const std::vector<std::pair<int, unsigned> > &TransSrcs,
126     R600InstrInfo::BankSwizzle TransSwz) const;
127 
128   /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
129   /// returns true and the first (in lexical order) BankSwizzle affectation
130   /// starting from the one already provided in the Instruction Group MIs that
131   /// fits Read Port limitations in BS if available. Otherwise returns false
132   /// and undefined content in BS.
133   /// isLastAluTrans should be set if the last Alu of MIs will be executed on
134   /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
135   /// apply to the last instruction.
136   /// PV holds GPR to PV registers in the Instruction Group MIs.
137   bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
138                                const DenseMap<unsigned, unsigned> &PV,
139                                std::vector<BankSwizzle> &BS,
140                                bool isLastAluTrans) const;
141 
142   /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
143   /// from KCache bank on R700+. This function check if MI set in input meet
144   /// this limitations
145   bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
146   /// Same but using const index set instead of MI set.
147   bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
148 
149   /// \brief Vector instructions are instructions that must fill all
150   /// instruction slots within an instruction group.
151   bool isVector(const MachineInstr &MI) const;
152 
153   bool isMov(unsigned Opcode) const;
154 
155   DFAPacketizer *
156   CreateTargetScheduleState(const TargetSubtargetInfo &) const override;
157 
158   bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
159 
160   bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
161                      SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override;
162 
163   unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
164                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
165                         DebugLoc DL) const override;
166 
167   unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
168 
169   bool isPredicated(const MachineInstr &MI) const override;
170 
171   bool isPredicable(MachineInstr &MI) const override;
172 
173   bool
174    isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
175                              BranchProbability Probability) const override;
176 
177   bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
178                            unsigned ExtraPredCycles,
179                            BranchProbability Probability) const override ;
180 
181   bool
182    isProfitableToIfCvt(MachineBasicBlock &TMBB,
183                        unsigned NumTCycles, unsigned ExtraTCycles,
184                        MachineBasicBlock &FMBB,
185                        unsigned NumFCycles, unsigned ExtraFCycles,
186                        BranchProbability Probability) const override;
187 
188   bool DefinesPredicate(MachineInstr &MI,
189                         std::vector<MachineOperand> &Pred) const override;
190 
191   bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
192                          ArrayRef<MachineOperand> Pred2) const override;
193 
194   bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
195                                           MachineBasicBlock &FMBB) const override;
196 
197   bool PredicateInstruction(MachineInstr &MI,
198                             ArrayRef<MachineOperand> Pred) const override;
199 
200   unsigned int getPredicationCost(const MachineInstr &) const override;
201 
202   unsigned int getInstrLatency(const InstrItineraryData *ItinData,
203                                const MachineInstr *MI,
204                                unsigned *PredCost = nullptr) const override;
205 
206   int getInstrLatency(const InstrItineraryData *ItinData,
207                       SDNode *Node) const override { return 1;}
208 
209   bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
210 
211   /// \brief Reserve the registers that may be accesed using indirect addressing.
212   void reserveIndirectRegisters(BitVector &Reserved,
213                                 const MachineFunction &MF) const;
214 
215   /// Calculate the "Indirect Address" for the given \p RegIndex and
216   /// \p Channel
217   ///
218   /// We model indirect addressing using a virtual address space that can be
219   /// accesed with loads and stores.  The "Indirect Address" is the memory
220   /// address in this virtual address space that maps to the given \p RegIndex
221   /// and \p Channel.
222   unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const;
223 
224 
225   const TargetRegisterClass *getIndirectAddrRegClass() const override;
226 
227   /// \brief Build instruction(s) for an indirect register write.
228   ///
229   /// \returns The instruction that performs the indirect register write
230   MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
231                                          MachineBasicBlock::iterator I,
232                                          unsigned ValueReg, unsigned Address,
233                                          unsigned OffsetReg) const;
234 
235   /// \brief Build instruction(s) for an indirect register read.
236   ///
237   /// \returns The instruction that performs the indirect register read
238   MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
239                                         MachineBasicBlock::iterator I,
240                                         unsigned ValueReg, unsigned Address,
241                                         unsigned OffsetReg) const;
242 
243   unsigned getMaxAlusPerClause() const;
244 
245   ///buildDefaultInstruction - This function returns a MachineInstr with
246   /// all the instruction modifiers initialized to their default values.
247   /// You can use this function to avoid manually specifying each instruction
248   /// modifier operand when building a new instruction.
249   ///
250   /// \returns a MachineInstr with all the instruction modifiers initialized
251   /// to their default values.
252   MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
253                                               MachineBasicBlock::iterator I,
254                                               unsigned Opcode,
255                                               unsigned DstReg,
256                                               unsigned Src0Reg,
257                                               unsigned Src1Reg = 0) const;
258 
259   MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
260                                              MachineInstr *MI,
261                                              unsigned Slot,
262                                              unsigned DstReg) const;
263 
264   MachineInstr *buildMovImm(MachineBasicBlock &BB,
265                                   MachineBasicBlock::iterator I,
266                                   unsigned DstReg,
267                                   uint64_t Imm) const;
268 
269   MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
270                               MachineBasicBlock::iterator I,
271                               unsigned DstReg, unsigned SrcReg) const;
272 
273   /// \brief Get the index of Op in the MachineInstr.
274   ///
275   /// \returns -1 if the Instruction does not contain the specified \p Op.
276   int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
277 
278   /// \brief Get the index of \p Op for the given Opcode.
279   ///
280   /// \returns -1 if the Instruction does not contain the specified \p Op.
281   int getOperandIdx(unsigned Opcode, unsigned Op) const;
282 
283   /// \brief Helper function for setting instruction flag values.
284   void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const;
285 
286   /// \returns true if this instruction has an operand for storing target flags.
287   bool hasFlagOperand(const MachineInstr &MI) const;
288 
289   ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
290   void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
291 
292   ///\brief Determine if the specified \p Flag is set on this \p Operand.
293   bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
294 
295   /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
296   /// \param Flag The flag being set.
297   ///
298   /// \returns the operand containing the flags for this instruction.
299   MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
300                             unsigned Flag = 0) const;
301 
302   /// \brief Clear the specified flag on the instruction.
303   void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
304 
305   // Helper functions that check the opcode for status information
306   bool isRegisterStore(const MachineInstr &MI) const;
307   bool isRegisterLoad(const MachineInstr &MI) const;
308 
309 };
310 
311 namespace AMDGPU {
312 
313 int getLDSNoRetOp(uint16_t Opcode);
314 
315 } //End namespace AMDGPU
316 
317 } // End llvm namespace
318 
319 #endif
320