1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief R600 Implementation of TargetInstrInfo.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "R600InstrInfo.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUSubtarget.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "R600Defines.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 
26 using namespace llvm;
27 
28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "AMDGPUGenDFAPacketizer.inc"
30 
31 R600InstrInfo::R600InstrInfo(const R600Subtarget &ST)
32   : AMDGPUInstrInfo(ST), RI(), ST(ST) {}
33 
34 bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
35   return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
36 }
37 
38 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
39   return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
40 }
41 
42 void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
43                                 MachineBasicBlock::iterator MI,
44                                 const DebugLoc &DL, unsigned DestReg,
45                                 unsigned SrcReg, bool KillSrc) const {
46   unsigned VectorComponents = 0;
47   if ((AMDGPU::R600_Reg128RegClass.contains(DestReg) ||
48       AMDGPU::R600_Reg128VerticalRegClass.contains(DestReg)) &&
49       (AMDGPU::R600_Reg128RegClass.contains(SrcReg) ||
50        AMDGPU::R600_Reg128VerticalRegClass.contains(SrcReg))) {
51     VectorComponents = 4;
52   } else if((AMDGPU::R600_Reg64RegClass.contains(DestReg) ||
53             AMDGPU::R600_Reg64VerticalRegClass.contains(DestReg)) &&
54             (AMDGPU::R600_Reg64RegClass.contains(SrcReg) ||
55              AMDGPU::R600_Reg64VerticalRegClass.contains(SrcReg))) {
56     VectorComponents = 2;
57   }
58 
59   if (VectorComponents > 0) {
60     for (unsigned I = 0; I < VectorComponents; I++) {
61       unsigned SubRegIndex = RI.getSubRegFromChannel(I);
62       buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
63                               RI.getSubReg(DestReg, SubRegIndex),
64                               RI.getSubReg(SrcReg, SubRegIndex))
65                               .addReg(DestReg,
66                                       RegState::Define | RegState::Implicit);
67     }
68   } else {
69     MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
70                                                   DestReg, SrcReg);
71     NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0))
72                                     .setIsKill(KillSrc);
73   }
74 }
75 
76 /// \returns true if \p MBBI can be moved into a new basic.
77 bool R600InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
78                                        MachineBasicBlock::iterator MBBI) const {
79   for (MachineInstr::const_mop_iterator I = MBBI->operands_begin(),
80                                         E = MBBI->operands_end(); I != E; ++I) {
81     if (I->isReg() && !TargetRegisterInfo::isVirtualRegister(I->getReg()) &&
82         I->isUse() && RI.isPhysRegLiveAcrossClauses(I->getReg()))
83       return false;
84   }
85   return true;
86 }
87 
88 bool R600InstrInfo::isMov(unsigned Opcode) const {
89   switch(Opcode) {
90   default:
91     return false;
92   case AMDGPU::MOV:
93   case AMDGPU::MOV_IMM_F32:
94   case AMDGPU::MOV_IMM_I32:
95     return true;
96   }
97 }
98 
99 // Some instructions act as place holders to emulate operations that the GPU
100 // hardware does automatically. This function can be used to check if
101 // an opcode falls into this category.
102 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {
103   switch (Opcode) {
104   default: return false;
105   case AMDGPU::RETURN:
106     return true;
107   }
108 }
109 
110 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
111   return false;
112 }
113 
114 bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
115   switch(Opcode) {
116     default: return false;
117     case AMDGPU::CUBE_r600_pseudo:
118     case AMDGPU::CUBE_r600_real:
119     case AMDGPU::CUBE_eg_pseudo:
120     case AMDGPU::CUBE_eg_real:
121       return true;
122   }
123 }
124 
125 bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
126   unsigned TargetFlags = get(Opcode).TSFlags;
127 
128   return (TargetFlags & R600_InstFlag::ALU_INST);
129 }
130 
131 bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const {
132   unsigned TargetFlags = get(Opcode).TSFlags;
133 
134   return ((TargetFlags & R600_InstFlag::OP1) |
135           (TargetFlags & R600_InstFlag::OP2) |
136           (TargetFlags & R600_InstFlag::OP3));
137 }
138 
139 bool R600InstrInfo::isLDSInstr(unsigned Opcode) const {
140   unsigned TargetFlags = get(Opcode).TSFlags;
141 
142   return ((TargetFlags & R600_InstFlag::LDS_1A) |
143           (TargetFlags & R600_InstFlag::LDS_1A1D) |
144           (TargetFlags & R600_InstFlag::LDS_1A2D));
145 }
146 
147 bool R600InstrInfo::isLDSNoRetInstr(unsigned Opcode) const {
148   return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) == -1;
149 }
150 
151 bool R600InstrInfo::isLDSRetInstr(unsigned Opcode) const {
152   return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) != -1;
153 }
154 
155 bool R600InstrInfo::canBeConsideredALU(const MachineInstr *MI) const {
156   if (isALUInstr(MI->getOpcode()))
157     return true;
158   if (isVector(*MI) || isCubeOp(MI->getOpcode()))
159     return true;
160   switch (MI->getOpcode()) {
161   case AMDGPU::PRED_X:
162   case AMDGPU::INTERP_PAIR_XY:
163   case AMDGPU::INTERP_PAIR_ZW:
164   case AMDGPU::INTERP_VEC_LOAD:
165   case AMDGPU::COPY:
166   case AMDGPU::DOT_4:
167     return true;
168   default:
169     return false;
170   }
171 }
172 
173 bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
174   if (ST.hasCaymanISA())
175     return false;
176   return (get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU);
177 }
178 
179 bool R600InstrInfo::isTransOnly(const MachineInstr *MI) const {
180   return isTransOnly(MI->getOpcode());
181 }
182 
183 bool R600InstrInfo::isVectorOnly(unsigned Opcode) const {
184   return (get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU);
185 }
186 
187 bool R600InstrInfo::isVectorOnly(const MachineInstr *MI) const {
188   return isVectorOnly(MI->getOpcode());
189 }
190 
191 bool R600InstrInfo::isExport(unsigned Opcode) const {
192   return (get(Opcode).TSFlags & R600_InstFlag::IS_EXPORT);
193 }
194 
195 bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
196   return ST.hasVertexCache() && IS_VTX(get(Opcode));
197 }
198 
199 bool R600InstrInfo::usesVertexCache(const MachineInstr *MI) const {
200   const MachineFunction *MF = MI->getParent()->getParent();
201   return !AMDGPU::isCompute(MF->getFunction()->getCallingConv()) &&
202     usesVertexCache(MI->getOpcode());
203 }
204 
205 bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {
206   return (!ST.hasVertexCache() && IS_VTX(get(Opcode))) || IS_TEX(get(Opcode));
207 }
208 
209 bool R600InstrInfo::usesTextureCache(const MachineInstr *MI) const {
210   const MachineFunction *MF = MI->getParent()->getParent();
211   return (AMDGPU::isCompute(MF->getFunction()->getCallingConv()) &&
212           usesVertexCache(MI->getOpcode())) ||
213     usesTextureCache(MI->getOpcode());
214 }
215 
216 bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const {
217   switch (Opcode) {
218   case AMDGPU::KILLGT:
219   case AMDGPU::GROUP_BARRIER:
220     return true;
221   default:
222     return false;
223   }
224 }
225 
226 bool R600InstrInfo::usesAddressRegister(MachineInstr *MI) const {
227   return  MI->findRegisterUseOperandIdx(AMDGPU::AR_X) != -1;
228 }
229 
230 bool R600InstrInfo::definesAddressRegister(MachineInstr *MI) const {
231   return MI->findRegisterDefOperandIdx(AMDGPU::AR_X) != -1;
232 }
233 
234 bool R600InstrInfo::readsLDSSrcReg(const MachineInstr *MI) const {
235   if (!isALUInstr(MI->getOpcode())) {
236     return false;
237   }
238   for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
239                                         E = MI->operands_end(); I != E; ++I) {
240     if (!I->isReg() || !I->isUse() ||
241         TargetRegisterInfo::isVirtualRegister(I->getReg()))
242       continue;
243 
244     if (AMDGPU::R600_LDS_SRC_REGRegClass.contains(I->getReg()))
245       return true;
246   }
247   return false;
248 }
249 
250 int R600InstrInfo::getSrcIdx(unsigned Opcode, unsigned SrcNum) const {
251   static const unsigned OpTable[] = {
252     AMDGPU::OpName::src0,
253     AMDGPU::OpName::src1,
254     AMDGPU::OpName::src2
255   };
256 
257   assert (SrcNum < 3);
258   return getOperandIdx(Opcode, OpTable[SrcNum]);
259 }
260 
261 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const {
262   static const unsigned SrcSelTable[][2] = {
263     {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
264     {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
265     {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
266     {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
267     {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
268     {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
269     {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
270     {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
271     {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
272     {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
273     {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W}
274   };
275 
276   for (const auto &Row : SrcSelTable) {
277     if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) {
278       return getOperandIdx(Opcode, Row[1]);
279     }
280   }
281   return -1;
282 }
283 
284 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
285 R600InstrInfo::getSrcs(MachineInstr *MI) const {
286   SmallVector<std::pair<MachineOperand *, int64_t>, 3> Result;
287 
288   if (MI->getOpcode() == AMDGPU::DOT_4) {
289     static const unsigned OpTable[8][2] = {
290       {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
291       {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
292       {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
293       {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
294       {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
295       {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
296       {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
297       {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W},
298     };
299 
300     for (unsigned j = 0; j < 8; j++) {
301       MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
302                                                         OpTable[j][0]));
303       unsigned Reg = MO.getReg();
304       if (Reg == AMDGPU::ALU_CONST) {
305         MachineOperand &Sel = MI->getOperand(getOperandIdx(MI->getOpcode(),
306                                                     OpTable[j][1]));
307         Result.push_back(std::make_pair(&MO, Sel.getImm()));
308         continue;
309       }
310 
311     }
312     return Result;
313   }
314 
315   static const unsigned OpTable[3][2] = {
316     {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
317     {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
318     {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
319   };
320 
321   for (unsigned j = 0; j < 3; j++) {
322     int SrcIdx = getOperandIdx(MI->getOpcode(), OpTable[j][0]);
323     if (SrcIdx < 0)
324       break;
325     MachineOperand &MO = MI->getOperand(SrcIdx);
326     unsigned Reg = MO.getReg();
327     if (Reg == AMDGPU::ALU_CONST) {
328       MachineOperand &Sel = MI->getOperand(
329           getOperandIdx(MI->getOpcode(), OpTable[j][1]));
330       Result.push_back(std::make_pair(&MO, Sel.getImm()));
331       continue;
332     }
333     if (Reg == AMDGPU::ALU_LITERAL_X) {
334       MachineOperand &Operand = MI->getOperand(
335           getOperandIdx(MI->getOpcode(), AMDGPU::OpName::literal));
336       if (Operand.isImm()) {
337         Result.push_back(std::make_pair(&MO, Operand.getImm()));
338         continue;
339       }
340       assert(Operand.isGlobal());
341     }
342     Result.push_back(std::make_pair(&MO, 0));
343   }
344   return Result;
345 }
346 
347 std::vector<std::pair<int, unsigned> >
348 R600InstrInfo::ExtractSrcs(MachineInstr *MI,
349                            const DenseMap<unsigned, unsigned> &PV,
350                            unsigned &ConstCount) const {
351   ConstCount = 0;
352   ArrayRef<std::pair<MachineOperand *, int64_t>> Srcs = getSrcs(MI);
353   const std::pair<int, unsigned> DummyPair(-1, 0);
354   std::vector<std::pair<int, unsigned> > Result;
355   unsigned i = 0;
356   for (unsigned n = Srcs.size(); i < n; ++i) {
357     unsigned Reg = Srcs[i].first->getReg();
358     int Index = RI.getEncodingValue(Reg) & 0xff;
359     if (Reg == AMDGPU::OQAP) {
360       Result.push_back(std::make_pair(Index, 0U));
361     }
362     if (PV.find(Reg) != PV.end()) {
363       // 255 is used to tells its a PS/PV reg
364       Result.push_back(std::make_pair(255, 0U));
365       continue;
366     }
367     if (Index > 127) {
368       ConstCount++;
369       Result.push_back(DummyPair);
370       continue;
371     }
372     unsigned Chan = RI.getHWRegChan(Reg);
373     Result.push_back(std::make_pair(Index, Chan));
374   }
375   for (; i < 3; ++i)
376     Result.push_back(DummyPair);
377   return Result;
378 }
379 
380 static std::vector<std::pair<int, unsigned> >
381 Swizzle(std::vector<std::pair<int, unsigned> > Src,
382         R600InstrInfo::BankSwizzle Swz) {
383   if (Src[0] == Src[1])
384     Src[1].first = -1;
385   switch (Swz) {
386   case R600InstrInfo::ALU_VEC_012_SCL_210:
387     break;
388   case R600InstrInfo::ALU_VEC_021_SCL_122:
389     std::swap(Src[1], Src[2]);
390     break;
391   case R600InstrInfo::ALU_VEC_102_SCL_221:
392     std::swap(Src[0], Src[1]);
393     break;
394   case R600InstrInfo::ALU_VEC_120_SCL_212:
395     std::swap(Src[0], Src[1]);
396     std::swap(Src[0], Src[2]);
397     break;
398   case R600InstrInfo::ALU_VEC_201:
399     std::swap(Src[0], Src[2]);
400     std::swap(Src[0], Src[1]);
401     break;
402   case R600InstrInfo::ALU_VEC_210:
403     std::swap(Src[0], Src[2]);
404     break;
405   }
406   return Src;
407 }
408 
409 static unsigned
410 getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) {
411   switch (Swz) {
412   case R600InstrInfo::ALU_VEC_012_SCL_210: {
413     unsigned Cycles[3] = { 2, 1, 0};
414     return Cycles[Op];
415   }
416   case R600InstrInfo::ALU_VEC_021_SCL_122: {
417     unsigned Cycles[3] = { 1, 2, 2};
418     return Cycles[Op];
419   }
420   case R600InstrInfo::ALU_VEC_120_SCL_212: {
421     unsigned Cycles[3] = { 2, 1, 2};
422     return Cycles[Op];
423   }
424   case R600InstrInfo::ALU_VEC_102_SCL_221: {
425     unsigned Cycles[3] = { 2, 2, 1};
426     return Cycles[Op];
427   }
428   default:
429     llvm_unreachable("Wrong Swizzle for Trans Slot");
430     return 0;
431   }
432 }
433 
434 /// returns how many MIs (whose inputs are represented by IGSrcs) can be packed
435 /// in the same Instruction Group while meeting read port limitations given a
436 /// Swz swizzle sequence.
437 unsigned  R600InstrInfo::isLegalUpTo(
438     const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
439     const std::vector<R600InstrInfo::BankSwizzle> &Swz,
440     const std::vector<std::pair<int, unsigned> > &TransSrcs,
441     R600InstrInfo::BankSwizzle TransSwz) const {
442   int Vector[4][3];
443   memset(Vector, -1, sizeof(Vector));
444   for (unsigned i = 0, e = IGSrcs.size(); i < e; i++) {
445     const std::vector<std::pair<int, unsigned> > &Srcs =
446         Swizzle(IGSrcs[i], Swz[i]);
447     for (unsigned j = 0; j < 3; j++) {
448       const std::pair<int, unsigned> &Src = Srcs[j];
449       if (Src.first < 0 || Src.first == 255)
450         continue;
451       if (Src.first == GET_REG_INDEX(RI.getEncodingValue(AMDGPU::OQAP))) {
452         if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 &&
453             Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) {
454             // The value from output queue A (denoted by register OQAP) can
455             // only be fetched during the first cycle.
456             return false;
457         }
458         // OQAP does not count towards the normal read port restrictions
459         continue;
460       }
461       if (Vector[Src.second][j] < 0)
462         Vector[Src.second][j] = Src.first;
463       if (Vector[Src.second][j] != Src.first)
464         return i;
465     }
466   }
467   // Now check Trans Alu
468   for (unsigned i = 0, e = TransSrcs.size(); i < e; ++i) {
469     const std::pair<int, unsigned> &Src = TransSrcs[i];
470     unsigned Cycle = getTransSwizzle(TransSwz, i);
471     if (Src.first < 0)
472       continue;
473     if (Src.first == 255)
474       continue;
475     if (Vector[Src.second][Cycle] < 0)
476       Vector[Src.second][Cycle] = Src.first;
477     if (Vector[Src.second][Cycle] != Src.first)
478       return IGSrcs.size() - 1;
479   }
480   return IGSrcs.size();
481 }
482 
483 /// Given a swizzle sequence SwzCandidate and an index Idx, returns the next
484 /// (in lexicographic term) swizzle sequence assuming that all swizzles after
485 /// Idx can be skipped
486 static bool
487 NextPossibleSolution(
488     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
489     unsigned Idx) {
490   assert(Idx < SwzCandidate.size());
491   int ResetIdx = Idx;
492   while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210)
493     ResetIdx --;
494   for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) {
495     SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210;
496   }
497   if (ResetIdx == -1)
498     return false;
499   int NextSwizzle = SwzCandidate[ResetIdx] + 1;
500   SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle;
501   return true;
502 }
503 
504 /// Enumerate all possible Swizzle sequence to find one that can meet all
505 /// read port requirements.
506 bool R600InstrInfo::FindSwizzleForVectorSlot(
507     const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
508     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
509     const std::vector<std::pair<int, unsigned> > &TransSrcs,
510     R600InstrInfo::BankSwizzle TransSwz) const {
511   unsigned ValidUpTo = 0;
512   do {
513     ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz);
514     if (ValidUpTo == IGSrcs.size())
515       return true;
516   } while (NextPossibleSolution(SwzCandidate, ValidUpTo));
517   return false;
518 }
519 
520 /// Instructions in Trans slot can't read gpr at cycle 0 if they also read
521 /// a const, and can't read a gpr at cycle 1 if they read 2 const.
522 static bool
523 isConstCompatible(R600InstrInfo::BankSwizzle TransSwz,
524                   const std::vector<std::pair<int, unsigned> > &TransOps,
525                   unsigned ConstCount) {
526   // TransALU can't read 3 constants
527   if (ConstCount > 2)
528     return false;
529   for (unsigned i = 0, e = TransOps.size(); i < e; ++i) {
530     const std::pair<int, unsigned> &Src = TransOps[i];
531     unsigned Cycle = getTransSwizzle(TransSwz, i);
532     if (Src.first < 0)
533       continue;
534     if (ConstCount > 0 && Cycle == 0)
535       return false;
536     if (ConstCount > 1 && Cycle == 1)
537       return false;
538   }
539   return true;
540 }
541 
542 bool
543 R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
544                                        const DenseMap<unsigned, unsigned> &PV,
545                                        std::vector<BankSwizzle> &ValidSwizzle,
546                                        bool isLastAluTrans)
547     const {
548   //Todo : support shared src0 - src1 operand
549 
550   std::vector<std::vector<std::pair<int, unsigned> > > IGSrcs;
551   ValidSwizzle.clear();
552   unsigned ConstCount;
553   BankSwizzle TransBS = ALU_VEC_012_SCL_210;
554   for (unsigned i = 0, e = IG.size(); i < e; ++i) {
555     IGSrcs.push_back(ExtractSrcs(IG[i], PV, ConstCount));
556     unsigned Op = getOperandIdx(IG[i]->getOpcode(),
557         AMDGPU::OpName::bank_swizzle);
558     ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle)
559         IG[i]->getOperand(Op).getImm());
560   }
561   std::vector<std::pair<int, unsigned> > TransOps;
562   if (!isLastAluTrans)
563     return FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps, TransBS);
564 
565   TransOps = std::move(IGSrcs.back());
566   IGSrcs.pop_back();
567   ValidSwizzle.pop_back();
568 
569   static const R600InstrInfo::BankSwizzle TransSwz[] = {
570     ALU_VEC_012_SCL_210,
571     ALU_VEC_021_SCL_122,
572     ALU_VEC_120_SCL_212,
573     ALU_VEC_102_SCL_221
574   };
575   for (unsigned i = 0; i < 4; i++) {
576     TransBS = TransSwz[i];
577     if (!isConstCompatible(TransBS, TransOps, ConstCount))
578       continue;
579     bool Result = FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps,
580         TransBS);
581     if (Result) {
582       ValidSwizzle.push_back(TransBS);
583       return true;
584     }
585   }
586 
587   return false;
588 }
589 
590 
591 bool
592 R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)
593     const {
594   assert (Consts.size() <= 12 && "Too many operands in instructions group");
595   unsigned Pair1 = 0, Pair2 = 0;
596   for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
597     unsigned ReadConstHalf = Consts[i] & 2;
598     unsigned ReadConstIndex = Consts[i] & (~3);
599     unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
600     if (!Pair1) {
601       Pair1 = ReadHalfConst;
602       continue;
603     }
604     if (Pair1 == ReadHalfConst)
605       continue;
606     if (!Pair2) {
607       Pair2 = ReadHalfConst;
608       continue;
609     }
610     if (Pair2 != ReadHalfConst)
611       return false;
612   }
613   return true;
614 }
615 
616 bool
617 R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs)
618     const {
619   std::vector<unsigned> Consts;
620   SmallSet<int64_t, 4> Literals;
621   for (unsigned i = 0, n = MIs.size(); i < n; i++) {
622     MachineInstr *MI = MIs[i];
623     if (!isALUInstr(MI->getOpcode()))
624       continue;
625 
626     ArrayRef<std::pair<MachineOperand *, int64_t>> Srcs = getSrcs(MI);
627 
628     for (const auto &Src:Srcs) {
629       if (Src.first->getReg() == AMDGPU::ALU_LITERAL_X)
630         Literals.insert(Src.second);
631       if (Literals.size() > 4)
632         return false;
633       if (Src.first->getReg() == AMDGPU::ALU_CONST)
634         Consts.push_back(Src.second);
635       if (AMDGPU::R600_KC0RegClass.contains(Src.first->getReg()) ||
636           AMDGPU::R600_KC1RegClass.contains(Src.first->getReg())) {
637         unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
638         unsigned Chan = RI.getHWRegChan(Src.first->getReg());
639         Consts.push_back((Index << 2) | Chan);
640       }
641     }
642   }
643   return fitsConstReadLimitations(Consts);
644 }
645 
646 DFAPacketizer *
647 R600InstrInfo::CreateTargetScheduleState(const TargetSubtargetInfo &STI) const {
648   const InstrItineraryData *II = STI.getInstrItineraryData();
649   return static_cast<const R600Subtarget &>(STI).createDFAPacketizer(II);
650 }
651 
652 static bool
653 isPredicateSetter(unsigned Opcode) {
654   switch (Opcode) {
655   case AMDGPU::PRED_X:
656     return true;
657   default:
658     return false;
659   }
660 }
661 
662 static MachineInstr *
663 findFirstPredicateSetterFrom(MachineBasicBlock &MBB,
664                              MachineBasicBlock::iterator I) {
665   while (I != MBB.begin()) {
666     --I;
667     MachineInstr *MI = I;
668     if (isPredicateSetter(MI->getOpcode()))
669       return MI;
670   }
671 
672   return nullptr;
673 }
674 
675 static
676 bool isJump(unsigned Opcode) {
677   return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND;
678 }
679 
680 static bool isBranch(unsigned Opcode) {
681   return Opcode == AMDGPU::BRANCH || Opcode == AMDGPU::BRANCH_COND_i32 ||
682       Opcode == AMDGPU::BRANCH_COND_f32;
683 }
684 
685 bool
686 R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
687                              MachineBasicBlock *&TBB,
688                              MachineBasicBlock *&FBB,
689                              SmallVectorImpl<MachineOperand> &Cond,
690                              bool AllowModify) const {
691   // Most of the following comes from the ARM implementation of AnalyzeBranch
692 
693   // If the block has no terminators, it just falls into the block after it.
694   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
695   if (I == MBB.end())
696     return false;
697 
698   // AMDGPU::BRANCH* instructions are only available after isel and are not
699   // handled
700   if (isBranch(I->getOpcode()))
701     return true;
702   if (!isJump(static_cast<MachineInstr *>(I)->getOpcode())) {
703     return false;
704   }
705 
706   // Remove successive JUMP
707   while (I != MBB.begin() && std::prev(I)->getOpcode() == AMDGPU::JUMP) {
708       MachineBasicBlock::iterator PriorI = std::prev(I);
709       if (AllowModify)
710         I->removeFromParent();
711       I = PriorI;
712   }
713   MachineInstr *LastInst = I;
714 
715   // If there is only one terminator instruction, process it.
716   unsigned LastOpc = LastInst->getOpcode();
717   if (I == MBB.begin() ||
718           !isJump(static_cast<MachineInstr *>(--I)->getOpcode())) {
719     if (LastOpc == AMDGPU::JUMP) {
720       TBB = LastInst->getOperand(0).getMBB();
721       return false;
722     } else if (LastOpc == AMDGPU::JUMP_COND) {
723       MachineInstr *predSet = I;
724       while (!isPredicateSetter(predSet->getOpcode())) {
725         predSet = --I;
726       }
727       TBB = LastInst->getOperand(0).getMBB();
728       Cond.push_back(predSet->getOperand(1));
729       Cond.push_back(predSet->getOperand(2));
730       Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
731       return false;
732     }
733     return true;  // Can't handle indirect branch.
734   }
735 
736   // Get the instruction before it if it is a terminator.
737   MachineInstr *SecondLastInst = I;
738   unsigned SecondLastOpc = SecondLastInst->getOpcode();
739 
740   // If the block ends with a B and a Bcc, handle it.
741   if (SecondLastOpc == AMDGPU::JUMP_COND && LastOpc == AMDGPU::JUMP) {
742     MachineInstr *predSet = --I;
743     while (!isPredicateSetter(predSet->getOpcode())) {
744       predSet = --I;
745     }
746     TBB = SecondLastInst->getOperand(0).getMBB();
747     FBB = LastInst->getOperand(0).getMBB();
748     Cond.push_back(predSet->getOperand(1));
749     Cond.push_back(predSet->getOperand(2));
750     Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
751     return false;
752   }
753 
754   // Otherwise, can't handle this.
755   return true;
756 }
757 
758 static
759 MachineBasicBlock::iterator FindLastAluClause(MachineBasicBlock &MBB) {
760   for (MachineBasicBlock::reverse_iterator It = MBB.rbegin(), E = MBB.rend();
761       It != E; ++It) {
762     if (It->getOpcode() == AMDGPU::CF_ALU ||
763         It->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
764       return std::prev(It.base());
765   }
766   return MBB.end();
767 }
768 
769 unsigned R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
770                                      MachineBasicBlock *TBB,
771                                      MachineBasicBlock *FBB,
772                                      ArrayRef<MachineOperand> Cond,
773                                      const DebugLoc &DL) const {
774   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
775 
776   if (!FBB) {
777     if (Cond.empty()) {
778       BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB);
779       return 1;
780     } else {
781       MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
782       assert(PredSet && "No previous predicate !");
783       addFlag(PredSet, 0, MO_FLAG_PUSH);
784       PredSet->getOperand(2).setImm(Cond[1].getImm());
785 
786       BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
787              .addMBB(TBB)
788              .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
789       MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
790       if (CfAlu == MBB.end())
791         return 1;
792       assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
793       CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
794       return 1;
795     }
796   } else {
797     MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
798     assert(PredSet && "No previous predicate !");
799     addFlag(PredSet, 0, MO_FLAG_PUSH);
800     PredSet->getOperand(2).setImm(Cond[1].getImm());
801     BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
802             .addMBB(TBB)
803             .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
804     BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB);
805     MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
806     if (CfAlu == MBB.end())
807       return 2;
808     assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
809     CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
810     return 2;
811   }
812 }
813 
814 unsigned
815 R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
816 
817   // Note : we leave PRED* instructions there.
818   // They may be needed when predicating instructions.
819 
820   MachineBasicBlock::iterator I = MBB.end();
821 
822   if (I == MBB.begin()) {
823     return 0;
824   }
825   --I;
826   switch (I->getOpcode()) {
827   default:
828     return 0;
829   case AMDGPU::JUMP_COND: {
830     MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
831     clearFlag(predSet, 0, MO_FLAG_PUSH);
832     I->eraseFromParent();
833     MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
834     if (CfAlu == MBB.end())
835       break;
836     assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
837     CfAlu->setDesc(get(AMDGPU::CF_ALU));
838     break;
839   }
840   case AMDGPU::JUMP:
841     I->eraseFromParent();
842     break;
843   }
844   I = MBB.end();
845 
846   if (I == MBB.begin()) {
847     return 1;
848   }
849   --I;
850   switch (I->getOpcode()) {
851     // FIXME: only one case??
852   default:
853     return 1;
854   case AMDGPU::JUMP_COND: {
855     MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
856     clearFlag(predSet, 0, MO_FLAG_PUSH);
857     I->eraseFromParent();
858     MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
859     if (CfAlu == MBB.end())
860       break;
861     assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
862     CfAlu->setDesc(get(AMDGPU::CF_ALU));
863     break;
864   }
865   case AMDGPU::JUMP:
866     I->eraseFromParent();
867     break;
868   }
869   return 2;
870 }
871 
872 bool R600InstrInfo::isPredicated(const MachineInstr &MI) const {
873   int idx = MI.findFirstPredOperandIdx();
874   if (idx < 0)
875     return false;
876 
877   unsigned Reg = MI.getOperand(idx).getReg();
878   switch (Reg) {
879   default: return false;
880   case AMDGPU::PRED_SEL_ONE:
881   case AMDGPU::PRED_SEL_ZERO:
882   case AMDGPU::PREDICATE_BIT:
883     return true;
884   }
885 }
886 
887 bool R600InstrInfo::isPredicable(MachineInstr &MI) const {
888   // XXX: KILL* instructions can be predicated, but they must be the last
889   // instruction in a clause, so this means any instructions after them cannot
890   // be predicated.  Until we have proper support for instruction clauses in the
891   // backend, we will mark KILL* instructions as unpredicable.
892 
893   if (MI.getOpcode() == AMDGPU::KILLGT) {
894     return false;
895   } else if (MI.getOpcode() == AMDGPU::CF_ALU) {
896     // If the clause start in the middle of MBB then the MBB has more
897     // than a single clause, unable to predicate several clauses.
898     if (MI.getParent()->begin() != MachineBasicBlock::iterator(MI))
899       return false;
900     // TODO: We don't support KC merging atm
901     return MI.getOperand(3).getImm() == 0 && MI.getOperand(4).getImm() == 0;
902   } else if (isVector(MI)) {
903     return false;
904   } else {
905     return AMDGPUInstrInfo::isPredicable(MI);
906   }
907 }
908 
909 
910 bool
911 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
912                                    unsigned NumCyles,
913                                    unsigned ExtraPredCycles,
914                                    BranchProbability Probability) const{
915   return true;
916 }
917 
918 bool
919 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
920                                    unsigned NumTCycles,
921                                    unsigned ExtraTCycles,
922                                    MachineBasicBlock &FMBB,
923                                    unsigned NumFCycles,
924                                    unsigned ExtraFCycles,
925                                    BranchProbability Probability) const {
926   return true;
927 }
928 
929 bool
930 R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
931                                          unsigned NumCyles,
932                                          BranchProbability Probability)
933                                          const {
934   return true;
935 }
936 
937 bool
938 R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
939                                          MachineBasicBlock &FMBB) const {
940   return false;
941 }
942 
943 
944 bool
945 R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
946   MachineOperand &MO = Cond[1];
947   switch (MO.getImm()) {
948   case OPCODE_IS_ZERO_INT:
949     MO.setImm(OPCODE_IS_NOT_ZERO_INT);
950     break;
951   case OPCODE_IS_NOT_ZERO_INT:
952     MO.setImm(OPCODE_IS_ZERO_INT);
953     break;
954   case OPCODE_IS_ZERO:
955     MO.setImm(OPCODE_IS_NOT_ZERO);
956     break;
957   case OPCODE_IS_NOT_ZERO:
958     MO.setImm(OPCODE_IS_ZERO);
959     break;
960   default:
961     return true;
962   }
963 
964   MachineOperand &MO2 = Cond[2];
965   switch (MO2.getReg()) {
966   case AMDGPU::PRED_SEL_ZERO:
967     MO2.setReg(AMDGPU::PRED_SEL_ONE);
968     break;
969   case AMDGPU::PRED_SEL_ONE:
970     MO2.setReg(AMDGPU::PRED_SEL_ZERO);
971     break;
972   default:
973     return true;
974   }
975   return false;
976 }
977 
978 bool R600InstrInfo::DefinesPredicate(MachineInstr &MI,
979                                      std::vector<MachineOperand> &Pred) const {
980   return isPredicateSetter(MI.getOpcode());
981 }
982 
983 
984 bool
985 R600InstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
986                                  ArrayRef<MachineOperand> Pred2) const {
987   return false;
988 }
989 
990 bool R600InstrInfo::PredicateInstruction(MachineInstr &MI,
991                                          ArrayRef<MachineOperand> Pred) const {
992   int PIdx = MI.findFirstPredOperandIdx();
993 
994   if (MI.getOpcode() == AMDGPU::CF_ALU) {
995     MI.getOperand(8).setImm(0);
996     return true;
997   }
998 
999   if (MI.getOpcode() == AMDGPU::DOT_4) {
1000     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_X))
1001         .setReg(Pred[2].getReg());
1002     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_Y))
1003         .setReg(Pred[2].getReg());
1004     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_Z))
1005         .setReg(Pred[2].getReg());
1006     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_W))
1007         .setReg(Pred[2].getReg());
1008     MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
1009     MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
1010     return true;
1011   }
1012 
1013   if (PIdx != -1) {
1014     MachineOperand &PMO = MI.getOperand(PIdx);
1015     PMO.setReg(Pred[2].getReg());
1016     MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
1017     MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
1018     return true;
1019   }
1020 
1021   return false;
1022 }
1023 
1024 unsigned int R600InstrInfo::getPredicationCost(const MachineInstr &) const {
1025   return 2;
1026 }
1027 
1028 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1029                                             const MachineInstr *MI,
1030                                             unsigned *PredCost) const {
1031   if (PredCost)
1032     *PredCost = 2;
1033   return 2;
1034 }
1035 
1036 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex,
1037                                                    unsigned Channel) const {
1038   assert(Channel == 0);
1039   return RegIndex;
1040 }
1041 
1042 bool R600InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
1043 
1044   switch(MI->getOpcode()) {
1045   default: {
1046     MachineBasicBlock *MBB = MI->getParent();
1047     int OffsetOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1048                                                  AMDGPU::OpName::addr);
1049      // addr is a custom operand with multiple MI operands, and only the
1050      // first MI operand is given a name.
1051     int RegOpIdx = OffsetOpIdx + 1;
1052     int ChanOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1053                                                AMDGPU::OpName::chan);
1054     if (isRegisterLoad(*MI)) {
1055       int DstOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1056                                                 AMDGPU::OpName::dst);
1057       unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
1058       unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
1059       unsigned Address = calculateIndirectAddress(RegIndex, Channel);
1060       unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
1061       if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
1062         buildMovInstr(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
1063                       getIndirectAddrRegClass()->getRegister(Address));
1064       } else {
1065         buildIndirectRead(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
1066                           Address, OffsetReg);
1067       }
1068     } else if (isRegisterStore(*MI)) {
1069       int ValOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1070                                                 AMDGPU::OpName::val);
1071       unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
1072       unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
1073       unsigned Address = calculateIndirectAddress(RegIndex, Channel);
1074       unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
1075       if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
1076         buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address),
1077                       MI->getOperand(ValOpIdx).getReg());
1078       } else {
1079         buildIndirectWrite(MBB, MI, MI->getOperand(ValOpIdx).getReg(),
1080                            calculateIndirectAddress(RegIndex, Channel),
1081                            OffsetReg);
1082       }
1083     } else {
1084       return false;
1085     }
1086 
1087     MBB->erase(MI);
1088     return true;
1089   }
1090   case AMDGPU::R600_EXTRACT_ELT_V2:
1091   case AMDGPU::R600_EXTRACT_ELT_V4:
1092     buildIndirectRead(MI->getParent(), MI, MI->getOperand(0).getReg(),
1093                       RI.getHWRegIndex(MI->getOperand(1).getReg()), //  Address
1094                       MI->getOperand(2).getReg(),
1095                       RI.getHWRegChan(MI->getOperand(1).getReg()));
1096     break;
1097   case AMDGPU::R600_INSERT_ELT_V2:
1098   case AMDGPU::R600_INSERT_ELT_V4:
1099     buildIndirectWrite(MI->getParent(), MI, MI->getOperand(2).getReg(), // Value
1100                        RI.getHWRegIndex(MI->getOperand(1).getReg()),  // Address
1101                        MI->getOperand(3).getReg(),                    // Offset
1102                        RI.getHWRegChan(MI->getOperand(1).getReg()));  // Channel
1103     break;
1104   }
1105   MI->eraseFromParent();
1106   return true;
1107 }
1108 
1109 void  R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,
1110                                              const MachineFunction &MF) const {
1111   const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
1112   const R600FrameLowering *TFL = ST.getFrameLowering();
1113 
1114   unsigned StackWidth = TFL->getStackWidth(MF);
1115   int End = getIndirectIndexEnd(MF);
1116 
1117   if (End == -1)
1118     return;
1119 
1120   for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
1121     unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
1122     Reserved.set(SuperReg);
1123     for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
1124       unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
1125       Reserved.set(Reg);
1126     }
1127   }
1128 }
1129 
1130 const TargetRegisterClass *R600InstrInfo::getIndirectAddrRegClass() const {
1131   return &AMDGPU::R600_TReg32_XRegClass;
1132 }
1133 
1134 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1135                                        MachineBasicBlock::iterator I,
1136                                        unsigned ValueReg, unsigned Address,
1137                                        unsigned OffsetReg) const {
1138   return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0);
1139 }
1140 
1141 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1142                                        MachineBasicBlock::iterator I,
1143                                        unsigned ValueReg, unsigned Address,
1144                                        unsigned OffsetReg,
1145                                        unsigned AddrChan) const {
1146   unsigned AddrReg;
1147   switch (AddrChan) {
1148     default: llvm_unreachable("Invalid Channel");
1149     case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break;
1150     case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break;
1151     case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break;
1152     case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address); break;
1153   }
1154   MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1155                                                AMDGPU::AR_X, OffsetReg);
1156   setImmOperand(MOVA, AMDGPU::OpName::write, 0);
1157 
1158   MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1159                                       AddrReg, ValueReg)
1160                                       .addReg(AMDGPU::AR_X,
1161                                            RegState::Implicit | RegState::Kill);
1162   setImmOperand(Mov, AMDGPU::OpName::dst_rel, 1);
1163   return Mov;
1164 }
1165 
1166 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1167                                        MachineBasicBlock::iterator I,
1168                                        unsigned ValueReg, unsigned Address,
1169                                        unsigned OffsetReg) const {
1170   return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0);
1171 }
1172 
1173 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1174                                        MachineBasicBlock::iterator I,
1175                                        unsigned ValueReg, unsigned Address,
1176                                        unsigned OffsetReg,
1177                                        unsigned AddrChan) const {
1178   unsigned AddrReg;
1179   switch (AddrChan) {
1180     default: llvm_unreachable("Invalid Channel");
1181     case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break;
1182     case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break;
1183     case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break;
1184     case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address); break;
1185   }
1186   MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1187                                                        AMDGPU::AR_X,
1188                                                        OffsetReg);
1189   setImmOperand(MOVA, AMDGPU::OpName::write, 0);
1190   MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1191                                       ValueReg,
1192                                       AddrReg)
1193                                       .addReg(AMDGPU::AR_X,
1194                                            RegState::Implicit | RegState::Kill);
1195   setImmOperand(Mov, AMDGPU::OpName::src0_rel, 1);
1196 
1197   return Mov;
1198 }
1199 
1200 unsigned R600InstrInfo::getMaxAlusPerClause() const {
1201   return 115;
1202 }
1203 
1204 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
1205                                                   MachineBasicBlock::iterator I,
1206                                                   unsigned Opcode,
1207                                                   unsigned DstReg,
1208                                                   unsigned Src0Reg,
1209                                                   unsigned Src1Reg) const {
1210   MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
1211     DstReg);           // $dst
1212 
1213   if (Src1Reg) {
1214     MIB.addImm(0)     // $update_exec_mask
1215        .addImm(0);    // $update_predicate
1216   }
1217   MIB.addImm(1)        // $write
1218      .addImm(0)        // $omod
1219      .addImm(0)        // $dst_rel
1220      .addImm(0)        // $dst_clamp
1221      .addReg(Src0Reg)  // $src0
1222      .addImm(0)        // $src0_neg
1223      .addImm(0)        // $src0_rel
1224      .addImm(0)        // $src0_abs
1225      .addImm(-1);       // $src0_sel
1226 
1227   if (Src1Reg) {
1228     MIB.addReg(Src1Reg) // $src1
1229        .addImm(0)       // $src1_neg
1230        .addImm(0)       // $src1_rel
1231        .addImm(0)       // $src1_abs
1232        .addImm(-1);      // $src1_sel
1233   }
1234 
1235   //XXX: The r600g finalizer expects this to be 1, once we've moved the
1236   //scheduling to the backend, we can change the default to 0.
1237   MIB.addImm(1)        // $last
1238       .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
1239       .addImm(0)         // $literal
1240       .addImm(0);        // $bank_swizzle
1241 
1242   return MIB;
1243 }
1244 
1245 #define OPERAND_CASE(Label) \
1246   case Label: { \
1247     static const unsigned Ops[] = \
1248     { \
1249       Label##_X, \
1250       Label##_Y, \
1251       Label##_Z, \
1252       Label##_W \
1253     }; \
1254     return Ops[Slot]; \
1255   }
1256 
1257 static unsigned getSlotedOps(unsigned  Op, unsigned Slot) {
1258   switch (Op) {
1259   OPERAND_CASE(AMDGPU::OpName::update_exec_mask)
1260   OPERAND_CASE(AMDGPU::OpName::update_pred)
1261   OPERAND_CASE(AMDGPU::OpName::write)
1262   OPERAND_CASE(AMDGPU::OpName::omod)
1263   OPERAND_CASE(AMDGPU::OpName::dst_rel)
1264   OPERAND_CASE(AMDGPU::OpName::clamp)
1265   OPERAND_CASE(AMDGPU::OpName::src0)
1266   OPERAND_CASE(AMDGPU::OpName::src0_neg)
1267   OPERAND_CASE(AMDGPU::OpName::src0_rel)
1268   OPERAND_CASE(AMDGPU::OpName::src0_abs)
1269   OPERAND_CASE(AMDGPU::OpName::src0_sel)
1270   OPERAND_CASE(AMDGPU::OpName::src1)
1271   OPERAND_CASE(AMDGPU::OpName::src1_neg)
1272   OPERAND_CASE(AMDGPU::OpName::src1_rel)
1273   OPERAND_CASE(AMDGPU::OpName::src1_abs)
1274   OPERAND_CASE(AMDGPU::OpName::src1_sel)
1275   OPERAND_CASE(AMDGPU::OpName::pred_sel)
1276   default:
1277     llvm_unreachable("Wrong Operand");
1278   }
1279 }
1280 
1281 #undef OPERAND_CASE
1282 
1283 MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction(
1284     MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg)
1285     const {
1286   assert (MI->getOpcode() == AMDGPU::DOT_4 && "Not Implemented");
1287   unsigned Opcode;
1288   if (ST.getGeneration() <= R600Subtarget::R700)
1289     Opcode = AMDGPU::DOT4_r600;
1290   else
1291     Opcode = AMDGPU::DOT4_eg;
1292   MachineBasicBlock::iterator I = MI;
1293   MachineOperand &Src0 = MI->getOperand(
1294       getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot)));
1295   MachineOperand &Src1 = MI->getOperand(
1296       getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot)));
1297   MachineInstr *MIB = buildDefaultInstruction(
1298       MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
1299   static const unsigned  Operands[14] = {
1300     AMDGPU::OpName::update_exec_mask,
1301     AMDGPU::OpName::update_pred,
1302     AMDGPU::OpName::write,
1303     AMDGPU::OpName::omod,
1304     AMDGPU::OpName::dst_rel,
1305     AMDGPU::OpName::clamp,
1306     AMDGPU::OpName::src0_neg,
1307     AMDGPU::OpName::src0_rel,
1308     AMDGPU::OpName::src0_abs,
1309     AMDGPU::OpName::src0_sel,
1310     AMDGPU::OpName::src1_neg,
1311     AMDGPU::OpName::src1_rel,
1312     AMDGPU::OpName::src1_abs,
1313     AMDGPU::OpName::src1_sel,
1314   };
1315 
1316   MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
1317       getSlotedOps(AMDGPU::OpName::pred_sel, Slot)));
1318   MIB->getOperand(getOperandIdx(Opcode, AMDGPU::OpName::pred_sel))
1319       .setReg(MO.getReg());
1320 
1321   for (unsigned i = 0; i < 14; i++) {
1322     MachineOperand &MO = MI->getOperand(
1323         getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
1324     assert (MO.isImm());
1325     setImmOperand(MIB, Operands[i], MO.getImm());
1326   }
1327   MIB->getOperand(20).setImm(0);
1328   return MIB;
1329 }
1330 
1331 MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
1332                                          MachineBasicBlock::iterator I,
1333                                          unsigned DstReg,
1334                                          uint64_t Imm) const {
1335   MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
1336                                                   AMDGPU::ALU_LITERAL_X);
1337   setImmOperand(MovImm, AMDGPU::OpName::literal, Imm);
1338   return MovImm;
1339 }
1340 
1341 MachineInstr *R600InstrInfo::buildMovInstr(MachineBasicBlock *MBB,
1342                                        MachineBasicBlock::iterator I,
1343                                        unsigned DstReg, unsigned SrcReg) const {
1344   return buildDefaultInstruction(*MBB, I, AMDGPU::MOV, DstReg, SrcReg);
1345 }
1346 
1347 int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const {
1348   return getOperandIdx(MI.getOpcode(), Op);
1349 }
1350 
1351 int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const {
1352   return AMDGPU::getNamedOperandIdx(Opcode, Op);
1353 }
1354 
1355 void R600InstrInfo::setImmOperand(MachineInstr *MI, unsigned Op,
1356                                   int64_t Imm) const {
1357   int Idx = getOperandIdx(*MI, Op);
1358   assert(Idx != -1 && "Operand not supported for this instruction.");
1359   assert(MI->getOperand(Idx).isImm());
1360   MI->getOperand(Idx).setImm(Imm);
1361 }
1362 
1363 //===----------------------------------------------------------------------===//
1364 // Instruction flag getters/setters
1365 //===----------------------------------------------------------------------===//
1366 
1367 bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const {
1368   return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
1369 }
1370 
1371 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr *MI, unsigned SrcIdx,
1372                                          unsigned Flag) const {
1373   unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1374   int FlagIndex = 0;
1375   if (Flag != 0) {
1376     // If we pass something other than the default value of Flag to this
1377     // function, it means we are want to set a flag on an instruction
1378     // that uses native encoding.
1379     assert(HAS_NATIVE_OPERANDS(TargetFlags));
1380     bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3;
1381     switch (Flag) {
1382     case MO_FLAG_CLAMP:
1383       FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::clamp);
1384       break;
1385     case MO_FLAG_MASK:
1386       FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::write);
1387       break;
1388     case MO_FLAG_NOT_LAST:
1389     case MO_FLAG_LAST:
1390       FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::last);
1391       break;
1392     case MO_FLAG_NEG:
1393       switch (SrcIdx) {
1394       case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_neg); break;
1395       case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_neg); break;
1396       case 2: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src2_neg); break;
1397       }
1398       break;
1399 
1400     case MO_FLAG_ABS:
1401       assert(!IsOP3 && "Cannot set absolute value modifier for OP3 "
1402                        "instructions.");
1403       (void)IsOP3;
1404       switch (SrcIdx) {
1405       case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_abs); break;
1406       case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_abs); break;
1407       }
1408       break;
1409 
1410     default:
1411       FlagIndex = -1;
1412       break;
1413     }
1414     assert(FlagIndex != -1 && "Flag not supported for this instruction");
1415   } else {
1416       FlagIndex = GET_FLAG_OPERAND_IDX(TargetFlags);
1417       assert(FlagIndex != 0 &&
1418          "Instruction flags not supported for this instruction");
1419   }
1420 
1421   MachineOperand &FlagOp = MI->getOperand(FlagIndex);
1422   assert(FlagOp.isImm());
1423   return FlagOp;
1424 }
1425 
1426 void R600InstrInfo::addFlag(MachineInstr *MI, unsigned Operand,
1427                             unsigned Flag) const {
1428   unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1429   if (Flag == 0) {
1430     return;
1431   }
1432   if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1433     MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1434     if (Flag == MO_FLAG_NOT_LAST) {
1435       clearFlag(MI, Operand, MO_FLAG_LAST);
1436     } else if (Flag == MO_FLAG_MASK) {
1437       clearFlag(MI, Operand, Flag);
1438     } else {
1439       FlagOp.setImm(1);
1440     }
1441   } else {
1442       MachineOperand &FlagOp = getFlagOp(MI, Operand);
1443       FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
1444   }
1445 }
1446 
1447 void R600InstrInfo::clearFlag(MachineInstr *MI, unsigned Operand,
1448                               unsigned Flag) const {
1449   unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1450   if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1451     MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1452     FlagOp.setImm(0);
1453   } else {
1454     MachineOperand &FlagOp = getFlagOp(MI);
1455     unsigned InstFlags = FlagOp.getImm();
1456     InstFlags &= ~(Flag << (NUM_MO_FLAGS * Operand));
1457     FlagOp.setImm(InstFlags);
1458   }
1459 }
1460 
1461 bool R600InstrInfo::isRegisterStore(const MachineInstr &MI) const {
1462   return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE;
1463 }
1464 
1465 bool R600InstrInfo::isRegisterLoad(const MachineInstr &MI) const {
1466   return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;
1467 }
1468