1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief R600 Implementation of TargetInstrInfo.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "R600InstrInfo.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUSubtarget.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "R600Defines.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 
26 using namespace llvm;
27 
28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "AMDGPUGenDFAPacketizer.inc"
30 
31 R600InstrInfo::R600InstrInfo(const R600Subtarget &ST)
32   : AMDGPUInstrInfo(ST), RI(), ST(ST) {}
33 
34 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
35   return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
36 }
37 
38 void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
39                                 MachineBasicBlock::iterator MI,
40                                 const DebugLoc &DL, unsigned DestReg,
41                                 unsigned SrcReg, bool KillSrc) const {
42   unsigned VectorComponents = 0;
43   if ((AMDGPU::R600_Reg128RegClass.contains(DestReg) ||
44       AMDGPU::R600_Reg128VerticalRegClass.contains(DestReg)) &&
45       (AMDGPU::R600_Reg128RegClass.contains(SrcReg) ||
46        AMDGPU::R600_Reg128VerticalRegClass.contains(SrcReg))) {
47     VectorComponents = 4;
48   } else if((AMDGPU::R600_Reg64RegClass.contains(DestReg) ||
49             AMDGPU::R600_Reg64VerticalRegClass.contains(DestReg)) &&
50             (AMDGPU::R600_Reg64RegClass.contains(SrcReg) ||
51              AMDGPU::R600_Reg64VerticalRegClass.contains(SrcReg))) {
52     VectorComponents = 2;
53   }
54 
55   if (VectorComponents > 0) {
56     for (unsigned I = 0; I < VectorComponents; I++) {
57       unsigned SubRegIndex = RI.getSubRegFromChannel(I);
58       buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
59                               RI.getSubReg(DestReg, SubRegIndex),
60                               RI.getSubReg(SrcReg, SubRegIndex))
61                               .addReg(DestReg,
62                                       RegState::Define | RegState::Implicit);
63     }
64   } else {
65     MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
66                                                   DestReg, SrcReg);
67     NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0))
68                                     .setIsKill(KillSrc);
69   }
70 }
71 
72 /// \returns true if \p MBBI can be moved into a new basic.
73 bool R600InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
74                                        MachineBasicBlock::iterator MBBI) const {
75   for (MachineInstr::const_mop_iterator I = MBBI->operands_begin(),
76                                         E = MBBI->operands_end(); I != E; ++I) {
77     if (I->isReg() && !TargetRegisterInfo::isVirtualRegister(I->getReg()) &&
78         I->isUse() && RI.isPhysRegLiveAcrossClauses(I->getReg()))
79       return false;
80   }
81   return true;
82 }
83 
84 bool R600InstrInfo::isMov(unsigned Opcode) const {
85   switch(Opcode) {
86   default:
87     return false;
88   case AMDGPU::MOV:
89   case AMDGPU::MOV_IMM_F32:
90   case AMDGPU::MOV_IMM_I32:
91     return true;
92   }
93 }
94 
95 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
96   return false;
97 }
98 
99 bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
100   switch(Opcode) {
101     default: return false;
102     case AMDGPU::CUBE_r600_pseudo:
103     case AMDGPU::CUBE_r600_real:
104     case AMDGPU::CUBE_eg_pseudo:
105     case AMDGPU::CUBE_eg_real:
106       return true;
107   }
108 }
109 
110 bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
111   unsigned TargetFlags = get(Opcode).TSFlags;
112 
113   return (TargetFlags & R600_InstFlag::ALU_INST);
114 }
115 
116 bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const {
117   unsigned TargetFlags = get(Opcode).TSFlags;
118 
119   return ((TargetFlags & R600_InstFlag::OP1) |
120           (TargetFlags & R600_InstFlag::OP2) |
121           (TargetFlags & R600_InstFlag::OP3));
122 }
123 
124 bool R600InstrInfo::isLDSInstr(unsigned Opcode) const {
125   unsigned TargetFlags = get(Opcode).TSFlags;
126 
127   return ((TargetFlags & R600_InstFlag::LDS_1A) |
128           (TargetFlags & R600_InstFlag::LDS_1A1D) |
129           (TargetFlags & R600_InstFlag::LDS_1A2D));
130 }
131 
132 bool R600InstrInfo::isLDSRetInstr(unsigned Opcode) const {
133   return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) != -1;
134 }
135 
136 bool R600InstrInfo::canBeConsideredALU(const MachineInstr &MI) const {
137   if (isALUInstr(MI.getOpcode()))
138     return true;
139   if (isVector(MI) || isCubeOp(MI.getOpcode()))
140     return true;
141   switch (MI.getOpcode()) {
142   case AMDGPU::PRED_X:
143   case AMDGPU::INTERP_PAIR_XY:
144   case AMDGPU::INTERP_PAIR_ZW:
145   case AMDGPU::INTERP_VEC_LOAD:
146   case AMDGPU::COPY:
147   case AMDGPU::DOT_4:
148     return true;
149   default:
150     return false;
151   }
152 }
153 
154 bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
155   if (ST.hasCaymanISA())
156     return false;
157   return (get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU);
158 }
159 
160 bool R600InstrInfo::isTransOnly(const MachineInstr &MI) const {
161   return isTransOnly(MI.getOpcode());
162 }
163 
164 bool R600InstrInfo::isVectorOnly(unsigned Opcode) const {
165   return (get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU);
166 }
167 
168 bool R600InstrInfo::isVectorOnly(const MachineInstr &MI) const {
169   return isVectorOnly(MI.getOpcode());
170 }
171 
172 bool R600InstrInfo::isExport(unsigned Opcode) const {
173   return (get(Opcode).TSFlags & R600_InstFlag::IS_EXPORT);
174 }
175 
176 bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
177   return ST.hasVertexCache() && IS_VTX(get(Opcode));
178 }
179 
180 bool R600InstrInfo::usesVertexCache(const MachineInstr &MI) const {
181   const MachineFunction *MF = MI.getParent()->getParent();
182   return !AMDGPU::isCompute(MF->getFunction()->getCallingConv()) &&
183          usesVertexCache(MI.getOpcode());
184 }
185 
186 bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {
187   return (!ST.hasVertexCache() && IS_VTX(get(Opcode))) || IS_TEX(get(Opcode));
188 }
189 
190 bool R600InstrInfo::usesTextureCache(const MachineInstr &MI) const {
191   const MachineFunction *MF = MI.getParent()->getParent();
192   return (AMDGPU::isCompute(MF->getFunction()->getCallingConv()) &&
193           usesVertexCache(MI.getOpcode())) ||
194          usesTextureCache(MI.getOpcode());
195 }
196 
197 bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const {
198   switch (Opcode) {
199   case AMDGPU::KILLGT:
200   case AMDGPU::GROUP_BARRIER:
201     return true;
202   default:
203     return false;
204   }
205 }
206 
207 bool R600InstrInfo::usesAddressRegister(MachineInstr &MI) const {
208   return MI.findRegisterUseOperandIdx(AMDGPU::AR_X) != -1;
209 }
210 
211 bool R600InstrInfo::definesAddressRegister(MachineInstr &MI) const {
212   return MI.findRegisterDefOperandIdx(AMDGPU::AR_X) != -1;
213 }
214 
215 bool R600InstrInfo::readsLDSSrcReg(const MachineInstr &MI) const {
216   if (!isALUInstr(MI.getOpcode())) {
217     return false;
218   }
219   for (MachineInstr::const_mop_iterator I = MI.operands_begin(),
220                                         E = MI.operands_end();
221        I != E; ++I) {
222     if (!I->isReg() || !I->isUse() ||
223         TargetRegisterInfo::isVirtualRegister(I->getReg()))
224       continue;
225 
226     if (AMDGPU::R600_LDS_SRC_REGRegClass.contains(I->getReg()))
227       return true;
228   }
229   return false;
230 }
231 
232 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const {
233   static const unsigned SrcSelTable[][2] = {
234     {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
235     {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
236     {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
237     {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
238     {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
239     {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
240     {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
241     {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
242     {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
243     {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
244     {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W}
245   };
246 
247   for (const auto &Row : SrcSelTable) {
248     if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) {
249       return getOperandIdx(Opcode, Row[1]);
250     }
251   }
252   return -1;
253 }
254 
255 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
256 R600InstrInfo::getSrcs(MachineInstr &MI) const {
257   SmallVector<std::pair<MachineOperand *, int64_t>, 3> Result;
258 
259   if (MI.getOpcode() == AMDGPU::DOT_4) {
260     static const unsigned OpTable[8][2] = {
261       {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
262       {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
263       {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
264       {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
265       {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
266       {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
267       {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
268       {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W},
269     };
270 
271     for (unsigned j = 0; j < 8; j++) {
272       MachineOperand &MO =
273           MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][0]));
274       unsigned Reg = MO.getReg();
275       if (Reg == AMDGPU::ALU_CONST) {
276         MachineOperand &Sel =
277             MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1]));
278         Result.push_back(std::make_pair(&MO, Sel.getImm()));
279         continue;
280       }
281 
282     }
283     return Result;
284   }
285 
286   static const unsigned OpTable[3][2] = {
287     {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
288     {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
289     {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
290   };
291 
292   for (unsigned j = 0; j < 3; j++) {
293     int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]);
294     if (SrcIdx < 0)
295       break;
296     MachineOperand &MO = MI.getOperand(SrcIdx);
297     unsigned Reg = MO.getReg();
298     if (Reg == AMDGPU::ALU_CONST) {
299       MachineOperand &Sel =
300           MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1]));
301       Result.push_back(std::make_pair(&MO, Sel.getImm()));
302       continue;
303     }
304     if (Reg == AMDGPU::ALU_LITERAL_X) {
305       MachineOperand &Operand =
306           MI.getOperand(getOperandIdx(MI.getOpcode(), AMDGPU::OpName::literal));
307       if (Operand.isImm()) {
308         Result.push_back(std::make_pair(&MO, Operand.getImm()));
309         continue;
310       }
311       assert(Operand.isGlobal());
312     }
313     Result.push_back(std::make_pair(&MO, 0));
314   }
315   return Result;
316 }
317 
318 std::vector<std::pair<int, unsigned>>
319 R600InstrInfo::ExtractSrcs(MachineInstr &MI,
320                            const DenseMap<unsigned, unsigned> &PV,
321                            unsigned &ConstCount) const {
322   ConstCount = 0;
323   const std::pair<int, unsigned> DummyPair(-1, 0);
324   std::vector<std::pair<int, unsigned> > Result;
325   unsigned i = 0;
326   for (const auto &Src : getSrcs(MI)) {
327     ++i;
328     unsigned Reg = Src.first->getReg();
329     int Index = RI.getEncodingValue(Reg) & 0xff;
330     if (Reg == AMDGPU::OQAP) {
331       Result.push_back(std::make_pair(Index, 0U));
332     }
333     if (PV.find(Reg) != PV.end()) {
334       // 255 is used to tells its a PS/PV reg
335       Result.push_back(std::make_pair(255, 0U));
336       continue;
337     }
338     if (Index > 127) {
339       ConstCount++;
340       Result.push_back(DummyPair);
341       continue;
342     }
343     unsigned Chan = RI.getHWRegChan(Reg);
344     Result.push_back(std::make_pair(Index, Chan));
345   }
346   for (; i < 3; ++i)
347     Result.push_back(DummyPair);
348   return Result;
349 }
350 
351 static std::vector<std::pair<int, unsigned> >
352 Swizzle(std::vector<std::pair<int, unsigned> > Src,
353         R600InstrInfo::BankSwizzle Swz) {
354   if (Src[0] == Src[1])
355     Src[1].first = -1;
356   switch (Swz) {
357   case R600InstrInfo::ALU_VEC_012_SCL_210:
358     break;
359   case R600InstrInfo::ALU_VEC_021_SCL_122:
360     std::swap(Src[1], Src[2]);
361     break;
362   case R600InstrInfo::ALU_VEC_102_SCL_221:
363     std::swap(Src[0], Src[1]);
364     break;
365   case R600InstrInfo::ALU_VEC_120_SCL_212:
366     std::swap(Src[0], Src[1]);
367     std::swap(Src[0], Src[2]);
368     break;
369   case R600InstrInfo::ALU_VEC_201:
370     std::swap(Src[0], Src[2]);
371     std::swap(Src[0], Src[1]);
372     break;
373   case R600InstrInfo::ALU_VEC_210:
374     std::swap(Src[0], Src[2]);
375     break;
376   }
377   return Src;
378 }
379 
380 static unsigned getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) {
381   switch (Swz) {
382   case R600InstrInfo::ALU_VEC_012_SCL_210: {
383     unsigned Cycles[3] = { 2, 1, 0};
384     return Cycles[Op];
385   }
386   case R600InstrInfo::ALU_VEC_021_SCL_122: {
387     unsigned Cycles[3] = { 1, 2, 2};
388     return Cycles[Op];
389   }
390   case R600InstrInfo::ALU_VEC_120_SCL_212: {
391     unsigned Cycles[3] = { 2, 1, 2};
392     return Cycles[Op];
393   }
394   case R600InstrInfo::ALU_VEC_102_SCL_221: {
395     unsigned Cycles[3] = { 2, 2, 1};
396     return Cycles[Op];
397   }
398   default:
399     llvm_unreachable("Wrong Swizzle for Trans Slot");
400   }
401 }
402 
403 /// returns how many MIs (whose inputs are represented by IGSrcs) can be packed
404 /// in the same Instruction Group while meeting read port limitations given a
405 /// Swz swizzle sequence.
406 unsigned  R600InstrInfo::isLegalUpTo(
407     const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
408     const std::vector<R600InstrInfo::BankSwizzle> &Swz,
409     const std::vector<std::pair<int, unsigned> > &TransSrcs,
410     R600InstrInfo::BankSwizzle TransSwz) const {
411   int Vector[4][3];
412   memset(Vector, -1, sizeof(Vector));
413   for (unsigned i = 0, e = IGSrcs.size(); i < e; i++) {
414     const std::vector<std::pair<int, unsigned> > &Srcs =
415         Swizzle(IGSrcs[i], Swz[i]);
416     for (unsigned j = 0; j < 3; j++) {
417       const std::pair<int, unsigned> &Src = Srcs[j];
418       if (Src.first < 0 || Src.first == 255)
419         continue;
420       if (Src.first == GET_REG_INDEX(RI.getEncodingValue(AMDGPU::OQAP))) {
421         if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 &&
422             Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) {
423             // The value from output queue A (denoted by register OQAP) can
424             // only be fetched during the first cycle.
425             return false;
426         }
427         // OQAP does not count towards the normal read port restrictions
428         continue;
429       }
430       if (Vector[Src.second][j] < 0)
431         Vector[Src.second][j] = Src.first;
432       if (Vector[Src.second][j] != Src.first)
433         return i;
434     }
435   }
436   // Now check Trans Alu
437   for (unsigned i = 0, e = TransSrcs.size(); i < e; ++i) {
438     const std::pair<int, unsigned> &Src = TransSrcs[i];
439     unsigned Cycle = getTransSwizzle(TransSwz, i);
440     if (Src.first < 0)
441       continue;
442     if (Src.first == 255)
443       continue;
444     if (Vector[Src.second][Cycle] < 0)
445       Vector[Src.second][Cycle] = Src.first;
446     if (Vector[Src.second][Cycle] != Src.first)
447       return IGSrcs.size() - 1;
448   }
449   return IGSrcs.size();
450 }
451 
452 /// Given a swizzle sequence SwzCandidate and an index Idx, returns the next
453 /// (in lexicographic term) swizzle sequence assuming that all swizzles after
454 /// Idx can be skipped
455 static bool
456 NextPossibleSolution(
457     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
458     unsigned Idx) {
459   assert(Idx < SwzCandidate.size());
460   int ResetIdx = Idx;
461   while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210)
462     ResetIdx --;
463   for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) {
464     SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210;
465   }
466   if (ResetIdx == -1)
467     return false;
468   int NextSwizzle = SwzCandidate[ResetIdx] + 1;
469   SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle;
470   return true;
471 }
472 
473 /// Enumerate all possible Swizzle sequence to find one that can meet all
474 /// read port requirements.
475 bool R600InstrInfo::FindSwizzleForVectorSlot(
476     const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
477     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
478     const std::vector<std::pair<int, unsigned> > &TransSrcs,
479     R600InstrInfo::BankSwizzle TransSwz) const {
480   unsigned ValidUpTo = 0;
481   do {
482     ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz);
483     if (ValidUpTo == IGSrcs.size())
484       return true;
485   } while (NextPossibleSolution(SwzCandidate, ValidUpTo));
486   return false;
487 }
488 
489 /// Instructions in Trans slot can't read gpr at cycle 0 if they also read
490 /// a const, and can't read a gpr at cycle 1 if they read 2 const.
491 static bool
492 isConstCompatible(R600InstrInfo::BankSwizzle TransSwz,
493                   const std::vector<std::pair<int, unsigned> > &TransOps,
494                   unsigned ConstCount) {
495   // TransALU can't read 3 constants
496   if (ConstCount > 2)
497     return false;
498   for (unsigned i = 0, e = TransOps.size(); i < e; ++i) {
499     const std::pair<int, unsigned> &Src = TransOps[i];
500     unsigned Cycle = getTransSwizzle(TransSwz, i);
501     if (Src.first < 0)
502       continue;
503     if (ConstCount > 0 && Cycle == 0)
504       return false;
505     if (ConstCount > 1 && Cycle == 1)
506       return false;
507   }
508   return true;
509 }
510 
511 bool
512 R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
513                                        const DenseMap<unsigned, unsigned> &PV,
514                                        std::vector<BankSwizzle> &ValidSwizzle,
515                                        bool isLastAluTrans)
516     const {
517   //Todo : support shared src0 - src1 operand
518 
519   std::vector<std::vector<std::pair<int, unsigned> > > IGSrcs;
520   ValidSwizzle.clear();
521   unsigned ConstCount;
522   BankSwizzle TransBS = ALU_VEC_012_SCL_210;
523   for (unsigned i = 0, e = IG.size(); i < e; ++i) {
524     IGSrcs.push_back(ExtractSrcs(*IG[i], PV, ConstCount));
525     unsigned Op = getOperandIdx(IG[i]->getOpcode(),
526         AMDGPU::OpName::bank_swizzle);
527     ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle)
528         IG[i]->getOperand(Op).getImm());
529   }
530   std::vector<std::pair<int, unsigned> > TransOps;
531   if (!isLastAluTrans)
532     return FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps, TransBS);
533 
534   TransOps = std::move(IGSrcs.back());
535   IGSrcs.pop_back();
536   ValidSwizzle.pop_back();
537 
538   static const R600InstrInfo::BankSwizzle TransSwz[] = {
539     ALU_VEC_012_SCL_210,
540     ALU_VEC_021_SCL_122,
541     ALU_VEC_120_SCL_212,
542     ALU_VEC_102_SCL_221
543   };
544   for (unsigned i = 0; i < 4; i++) {
545     TransBS = TransSwz[i];
546     if (!isConstCompatible(TransBS, TransOps, ConstCount))
547       continue;
548     bool Result = FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps,
549         TransBS);
550     if (Result) {
551       ValidSwizzle.push_back(TransBS);
552       return true;
553     }
554   }
555 
556   return false;
557 }
558 
559 
560 bool
561 R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)
562     const {
563   assert (Consts.size() <= 12 && "Too many operands in instructions group");
564   unsigned Pair1 = 0, Pair2 = 0;
565   for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
566     unsigned ReadConstHalf = Consts[i] & 2;
567     unsigned ReadConstIndex = Consts[i] & (~3);
568     unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
569     if (!Pair1) {
570       Pair1 = ReadHalfConst;
571       continue;
572     }
573     if (Pair1 == ReadHalfConst)
574       continue;
575     if (!Pair2) {
576       Pair2 = ReadHalfConst;
577       continue;
578     }
579     if (Pair2 != ReadHalfConst)
580       return false;
581   }
582   return true;
583 }
584 
585 bool
586 R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs)
587     const {
588   std::vector<unsigned> Consts;
589   SmallSet<int64_t, 4> Literals;
590   for (unsigned i = 0, n = MIs.size(); i < n; i++) {
591     MachineInstr &MI = *MIs[i];
592     if (!isALUInstr(MI.getOpcode()))
593       continue;
594 
595     for (const auto &Src : getSrcs(MI)) {
596       if (Src.first->getReg() == AMDGPU::ALU_LITERAL_X)
597         Literals.insert(Src.second);
598       if (Literals.size() > 4)
599         return false;
600       if (Src.first->getReg() == AMDGPU::ALU_CONST)
601         Consts.push_back(Src.second);
602       if (AMDGPU::R600_KC0RegClass.contains(Src.first->getReg()) ||
603           AMDGPU::R600_KC1RegClass.contains(Src.first->getReg())) {
604         unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
605         unsigned Chan = RI.getHWRegChan(Src.first->getReg());
606         Consts.push_back((Index << 2) | Chan);
607       }
608     }
609   }
610   return fitsConstReadLimitations(Consts);
611 }
612 
613 DFAPacketizer *
614 R600InstrInfo::CreateTargetScheduleState(const TargetSubtargetInfo &STI) const {
615   const InstrItineraryData *II = STI.getInstrItineraryData();
616   return static_cast<const R600Subtarget &>(STI).createDFAPacketizer(II);
617 }
618 
619 static bool
620 isPredicateSetter(unsigned Opcode) {
621   switch (Opcode) {
622   case AMDGPU::PRED_X:
623     return true;
624   default:
625     return false;
626   }
627 }
628 
629 static MachineInstr *
630 findFirstPredicateSetterFrom(MachineBasicBlock &MBB,
631                              MachineBasicBlock::iterator I) {
632   while (I != MBB.begin()) {
633     --I;
634     MachineInstr &MI = *I;
635     if (isPredicateSetter(MI.getOpcode()))
636       return &MI;
637   }
638 
639   return nullptr;
640 }
641 
642 static
643 bool isJump(unsigned Opcode) {
644   return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND;
645 }
646 
647 static bool isBranch(unsigned Opcode) {
648   return Opcode == AMDGPU::BRANCH || Opcode == AMDGPU::BRANCH_COND_i32 ||
649       Opcode == AMDGPU::BRANCH_COND_f32;
650 }
651 
652 bool R600InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
653                                   MachineBasicBlock *&TBB,
654                                   MachineBasicBlock *&FBB,
655                                   SmallVectorImpl<MachineOperand> &Cond,
656                                   bool AllowModify) const {
657   // Most of the following comes from the ARM implementation of AnalyzeBranch
658 
659   // If the block has no terminators, it just falls into the block after it.
660   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
661   if (I == MBB.end())
662     return false;
663 
664   // AMDGPU::BRANCH* instructions are only available after isel and are not
665   // handled
666   if (isBranch(I->getOpcode()))
667     return true;
668   if (!isJump(I->getOpcode())) {
669     return false;
670   }
671 
672   // Remove successive JUMP
673   while (I != MBB.begin() && std::prev(I)->getOpcode() == AMDGPU::JUMP) {
674       MachineBasicBlock::iterator PriorI = std::prev(I);
675       if (AllowModify)
676         I->removeFromParent();
677       I = PriorI;
678   }
679   MachineInstr &LastInst = *I;
680 
681   // If there is only one terminator instruction, process it.
682   unsigned LastOpc = LastInst.getOpcode();
683   if (I == MBB.begin() || !isJump((--I)->getOpcode())) {
684     if (LastOpc == AMDGPU::JUMP) {
685       TBB = LastInst.getOperand(0).getMBB();
686       return false;
687     } else if (LastOpc == AMDGPU::JUMP_COND) {
688       auto predSet = I;
689       while (!isPredicateSetter(predSet->getOpcode())) {
690         predSet = --I;
691       }
692       TBB = LastInst.getOperand(0).getMBB();
693       Cond.push_back(predSet->getOperand(1));
694       Cond.push_back(predSet->getOperand(2));
695       Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
696       return false;
697     }
698     return true;  // Can't handle indirect branch.
699   }
700 
701   // Get the instruction before it if it is a terminator.
702   MachineInstr &SecondLastInst = *I;
703   unsigned SecondLastOpc = SecondLastInst.getOpcode();
704 
705   // If the block ends with a B and a Bcc, handle it.
706   if (SecondLastOpc == AMDGPU::JUMP_COND && LastOpc == AMDGPU::JUMP) {
707     auto predSet = --I;
708     while (!isPredicateSetter(predSet->getOpcode())) {
709       predSet = --I;
710     }
711     TBB = SecondLastInst.getOperand(0).getMBB();
712     FBB = LastInst.getOperand(0).getMBB();
713     Cond.push_back(predSet->getOperand(1));
714     Cond.push_back(predSet->getOperand(2));
715     Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
716     return false;
717   }
718 
719   // Otherwise, can't handle this.
720   return true;
721 }
722 
723 static
724 MachineBasicBlock::iterator FindLastAluClause(MachineBasicBlock &MBB) {
725   for (MachineBasicBlock::reverse_iterator It = MBB.rbegin(), E = MBB.rend();
726       It != E; ++It) {
727     if (It->getOpcode() == AMDGPU::CF_ALU ||
728         It->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
729       return std::prev(It.base());
730   }
731   return MBB.end();
732 }
733 
734 unsigned R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
735                                      MachineBasicBlock *TBB,
736                                      MachineBasicBlock *FBB,
737                                      ArrayRef<MachineOperand> Cond,
738                                      const DebugLoc &DL) const {
739   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
740 
741   if (!FBB) {
742     if (Cond.empty()) {
743       BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB);
744       return 1;
745     } else {
746       MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
747       assert(PredSet && "No previous predicate !");
748       addFlag(*PredSet, 0, MO_FLAG_PUSH);
749       PredSet->getOperand(2).setImm(Cond[1].getImm());
750 
751       BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
752              .addMBB(TBB)
753              .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
754       MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
755       if (CfAlu == MBB.end())
756         return 1;
757       assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
758       CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
759       return 1;
760     }
761   } else {
762     MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
763     assert(PredSet && "No previous predicate !");
764     addFlag(*PredSet, 0, MO_FLAG_PUSH);
765     PredSet->getOperand(2).setImm(Cond[1].getImm());
766     BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
767             .addMBB(TBB)
768             .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
769     BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB);
770     MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
771     if (CfAlu == MBB.end())
772       return 2;
773     assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
774     CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
775     return 2;
776   }
777 }
778 
779 unsigned
780 R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
781 
782   // Note : we leave PRED* instructions there.
783   // They may be needed when predicating instructions.
784 
785   MachineBasicBlock::iterator I = MBB.end();
786 
787   if (I == MBB.begin()) {
788     return 0;
789   }
790   --I;
791   switch (I->getOpcode()) {
792   default:
793     return 0;
794   case AMDGPU::JUMP_COND: {
795     MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
796     clearFlag(*predSet, 0, MO_FLAG_PUSH);
797     I->eraseFromParent();
798     MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
799     if (CfAlu == MBB.end())
800       break;
801     assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
802     CfAlu->setDesc(get(AMDGPU::CF_ALU));
803     break;
804   }
805   case AMDGPU::JUMP:
806     I->eraseFromParent();
807     break;
808   }
809   I = MBB.end();
810 
811   if (I == MBB.begin()) {
812     return 1;
813   }
814   --I;
815   switch (I->getOpcode()) {
816     // FIXME: only one case??
817   default:
818     return 1;
819   case AMDGPU::JUMP_COND: {
820     MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
821     clearFlag(*predSet, 0, MO_FLAG_PUSH);
822     I->eraseFromParent();
823     MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
824     if (CfAlu == MBB.end())
825       break;
826     assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
827     CfAlu->setDesc(get(AMDGPU::CF_ALU));
828     break;
829   }
830   case AMDGPU::JUMP:
831     I->eraseFromParent();
832     break;
833   }
834   return 2;
835 }
836 
837 bool R600InstrInfo::isPredicated(const MachineInstr &MI) const {
838   int idx = MI.findFirstPredOperandIdx();
839   if (idx < 0)
840     return false;
841 
842   unsigned Reg = MI.getOperand(idx).getReg();
843   switch (Reg) {
844   default: return false;
845   case AMDGPU::PRED_SEL_ONE:
846   case AMDGPU::PRED_SEL_ZERO:
847   case AMDGPU::PREDICATE_BIT:
848     return true;
849   }
850 }
851 
852 bool R600InstrInfo::isPredicable(MachineInstr &MI) const {
853   // XXX: KILL* instructions can be predicated, but they must be the last
854   // instruction in a clause, so this means any instructions after them cannot
855   // be predicated.  Until we have proper support for instruction clauses in the
856   // backend, we will mark KILL* instructions as unpredicable.
857 
858   if (MI.getOpcode() == AMDGPU::KILLGT) {
859     return false;
860   } else if (MI.getOpcode() == AMDGPU::CF_ALU) {
861     // If the clause start in the middle of MBB then the MBB has more
862     // than a single clause, unable to predicate several clauses.
863     if (MI.getParent()->begin() != MachineBasicBlock::iterator(MI))
864       return false;
865     // TODO: We don't support KC merging atm
866     return MI.getOperand(3).getImm() == 0 && MI.getOperand(4).getImm() == 0;
867   } else if (isVector(MI)) {
868     return false;
869   } else {
870     return AMDGPUInstrInfo::isPredicable(MI);
871   }
872 }
873 
874 
875 bool
876 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
877                                    unsigned NumCyles,
878                                    unsigned ExtraPredCycles,
879                                    BranchProbability Probability) const{
880   return true;
881 }
882 
883 bool
884 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
885                                    unsigned NumTCycles,
886                                    unsigned ExtraTCycles,
887                                    MachineBasicBlock &FMBB,
888                                    unsigned NumFCycles,
889                                    unsigned ExtraFCycles,
890                                    BranchProbability Probability) const {
891   return true;
892 }
893 
894 bool
895 R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
896                                          unsigned NumCyles,
897                                          BranchProbability Probability)
898                                          const {
899   return true;
900 }
901 
902 bool
903 R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
904                                          MachineBasicBlock &FMBB) const {
905   return false;
906 }
907 
908 
909 bool
910 R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
911   MachineOperand &MO = Cond[1];
912   switch (MO.getImm()) {
913   case OPCODE_IS_ZERO_INT:
914     MO.setImm(OPCODE_IS_NOT_ZERO_INT);
915     break;
916   case OPCODE_IS_NOT_ZERO_INT:
917     MO.setImm(OPCODE_IS_ZERO_INT);
918     break;
919   case OPCODE_IS_ZERO:
920     MO.setImm(OPCODE_IS_NOT_ZERO);
921     break;
922   case OPCODE_IS_NOT_ZERO:
923     MO.setImm(OPCODE_IS_ZERO);
924     break;
925   default:
926     return true;
927   }
928 
929   MachineOperand &MO2 = Cond[2];
930   switch (MO2.getReg()) {
931   case AMDGPU::PRED_SEL_ZERO:
932     MO2.setReg(AMDGPU::PRED_SEL_ONE);
933     break;
934   case AMDGPU::PRED_SEL_ONE:
935     MO2.setReg(AMDGPU::PRED_SEL_ZERO);
936     break;
937   default:
938     return true;
939   }
940   return false;
941 }
942 
943 bool R600InstrInfo::DefinesPredicate(MachineInstr &MI,
944                                      std::vector<MachineOperand> &Pred) const {
945   return isPredicateSetter(MI.getOpcode());
946 }
947 
948 
949 bool R600InstrInfo::PredicateInstruction(MachineInstr &MI,
950                                          ArrayRef<MachineOperand> Pred) const {
951   int PIdx = MI.findFirstPredOperandIdx();
952 
953   if (MI.getOpcode() == AMDGPU::CF_ALU) {
954     MI.getOperand(8).setImm(0);
955     return true;
956   }
957 
958   if (MI.getOpcode() == AMDGPU::DOT_4) {
959     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_X))
960         .setReg(Pred[2].getReg());
961     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_Y))
962         .setReg(Pred[2].getReg());
963     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_Z))
964         .setReg(Pred[2].getReg());
965     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_W))
966         .setReg(Pred[2].getReg());
967     MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
968     MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
969     return true;
970   }
971 
972   if (PIdx != -1) {
973     MachineOperand &PMO = MI.getOperand(PIdx);
974     PMO.setReg(Pred[2].getReg());
975     MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
976     MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
977     return true;
978   }
979 
980   return false;
981 }
982 
983 unsigned int R600InstrInfo::getPredicationCost(const MachineInstr &) const {
984   return 2;
985 }
986 
987 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
988                                             const MachineInstr &,
989                                             unsigned *PredCost) const {
990   if (PredCost)
991     *PredCost = 2;
992   return 2;
993 }
994 
995 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex,
996                                                    unsigned Channel) const {
997   assert(Channel == 0);
998   return RegIndex;
999 }
1000 
1001 bool R600InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1002   switch (MI.getOpcode()) {
1003   default: {
1004     MachineBasicBlock *MBB = MI.getParent();
1005     int OffsetOpIdx =
1006         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::addr);
1007     // addr is a custom operand with multiple MI operands, and only the
1008     // first MI operand is given a name.
1009     int RegOpIdx = OffsetOpIdx + 1;
1010     int ChanOpIdx =
1011         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::chan);
1012     if (isRegisterLoad(MI)) {
1013       int DstOpIdx =
1014           AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst);
1015       unsigned RegIndex = MI.getOperand(RegOpIdx).getImm();
1016       unsigned Channel = MI.getOperand(ChanOpIdx).getImm();
1017       unsigned Address = calculateIndirectAddress(RegIndex, Channel);
1018       unsigned OffsetReg = MI.getOperand(OffsetOpIdx).getReg();
1019       if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
1020         buildMovInstr(MBB, MI, MI.getOperand(DstOpIdx).getReg(),
1021                       getIndirectAddrRegClass()->getRegister(Address));
1022       } else {
1023         buildIndirectRead(MBB, MI, MI.getOperand(DstOpIdx).getReg(), Address,
1024                           OffsetReg);
1025       }
1026     } else if (isRegisterStore(MI)) {
1027       int ValOpIdx =
1028           AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::val);
1029       unsigned RegIndex = MI.getOperand(RegOpIdx).getImm();
1030       unsigned Channel = MI.getOperand(ChanOpIdx).getImm();
1031       unsigned Address = calculateIndirectAddress(RegIndex, Channel);
1032       unsigned OffsetReg = MI.getOperand(OffsetOpIdx).getReg();
1033       if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
1034         buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address),
1035                       MI.getOperand(ValOpIdx).getReg());
1036       } else {
1037         buildIndirectWrite(MBB, MI, MI.getOperand(ValOpIdx).getReg(),
1038                            calculateIndirectAddress(RegIndex, Channel),
1039                            OffsetReg);
1040       }
1041     } else {
1042       return false;
1043     }
1044 
1045     MBB->erase(MI);
1046     return true;
1047   }
1048   case AMDGPU::R600_EXTRACT_ELT_V2:
1049   case AMDGPU::R600_EXTRACT_ELT_V4:
1050     buildIndirectRead(MI.getParent(), MI, MI.getOperand(0).getReg(),
1051                       RI.getHWRegIndex(MI.getOperand(1).getReg()), //  Address
1052                       MI.getOperand(2).getReg(),
1053                       RI.getHWRegChan(MI.getOperand(1).getReg()));
1054     break;
1055   case AMDGPU::R600_INSERT_ELT_V2:
1056   case AMDGPU::R600_INSERT_ELT_V4:
1057     buildIndirectWrite(MI.getParent(), MI, MI.getOperand(2).getReg(), // Value
1058                        RI.getHWRegIndex(MI.getOperand(1).getReg()),   // Address
1059                        MI.getOperand(3).getReg(),                     // Offset
1060                        RI.getHWRegChan(MI.getOperand(1).getReg()));   // Channel
1061     break;
1062   }
1063   MI.eraseFromParent();
1064   return true;
1065 }
1066 
1067 void  R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,
1068                                              const MachineFunction &MF) const {
1069   const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
1070   const R600FrameLowering *TFL = ST.getFrameLowering();
1071 
1072   unsigned StackWidth = TFL->getStackWidth(MF);
1073   int End = getIndirectIndexEnd(MF);
1074 
1075   if (End == -1)
1076     return;
1077 
1078   for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
1079     unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
1080     Reserved.set(SuperReg);
1081     for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
1082       unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
1083       Reserved.set(Reg);
1084     }
1085   }
1086 }
1087 
1088 const TargetRegisterClass *R600InstrInfo::getIndirectAddrRegClass() const {
1089   return &AMDGPU::R600_TReg32_XRegClass;
1090 }
1091 
1092 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1093                                        MachineBasicBlock::iterator I,
1094                                        unsigned ValueReg, unsigned Address,
1095                                        unsigned OffsetReg) const {
1096   return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0);
1097 }
1098 
1099 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1100                                        MachineBasicBlock::iterator I,
1101                                        unsigned ValueReg, unsigned Address,
1102                                        unsigned OffsetReg,
1103                                        unsigned AddrChan) const {
1104   unsigned AddrReg;
1105   switch (AddrChan) {
1106     default: llvm_unreachable("Invalid Channel");
1107     case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break;
1108     case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break;
1109     case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break;
1110     case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address); break;
1111   }
1112   MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1113                                                AMDGPU::AR_X, OffsetReg);
1114   setImmOperand(*MOVA, AMDGPU::OpName::write, 0);
1115 
1116   MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1117                                       AddrReg, ValueReg)
1118                                       .addReg(AMDGPU::AR_X,
1119                                            RegState::Implicit | RegState::Kill);
1120   setImmOperand(*Mov, AMDGPU::OpName::dst_rel, 1);
1121   return Mov;
1122 }
1123 
1124 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1125                                        MachineBasicBlock::iterator I,
1126                                        unsigned ValueReg, unsigned Address,
1127                                        unsigned OffsetReg) const {
1128   return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0);
1129 }
1130 
1131 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1132                                        MachineBasicBlock::iterator I,
1133                                        unsigned ValueReg, unsigned Address,
1134                                        unsigned OffsetReg,
1135                                        unsigned AddrChan) const {
1136   unsigned AddrReg;
1137   switch (AddrChan) {
1138     default: llvm_unreachable("Invalid Channel");
1139     case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break;
1140     case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break;
1141     case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break;
1142     case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address); break;
1143   }
1144   MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1145                                                        AMDGPU::AR_X,
1146                                                        OffsetReg);
1147   setImmOperand(*MOVA, AMDGPU::OpName::write, 0);
1148   MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1149                                       ValueReg,
1150                                       AddrReg)
1151                                       .addReg(AMDGPU::AR_X,
1152                                            RegState::Implicit | RegState::Kill);
1153   setImmOperand(*Mov, AMDGPU::OpName::src0_rel, 1);
1154 
1155   return Mov;
1156 }
1157 
1158 int R600InstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
1159   const MachineRegisterInfo &MRI = MF.getRegInfo();
1160   const MachineFrameInfo &MFI = MF.getFrameInfo();
1161   int Offset = -1;
1162 
1163   if (MFI.getNumObjects() == 0) {
1164     return -1;
1165   }
1166 
1167   if (MRI.livein_empty()) {
1168     return 0;
1169   }
1170 
1171   const TargetRegisterClass *IndirectRC = getIndirectAddrRegClass();
1172   for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
1173                                             LE = MRI.livein_end();
1174                                             LI != LE; ++LI) {
1175     unsigned Reg = LI->first;
1176     if (TargetRegisterInfo::isVirtualRegister(Reg) ||
1177         !IndirectRC->contains(Reg))
1178       continue;
1179 
1180     unsigned RegIndex;
1181     unsigned RegEnd;
1182     for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd;
1183                                                           ++RegIndex) {
1184       if (IndirectRC->getRegister(RegIndex) == Reg)
1185         break;
1186     }
1187     Offset = std::max(Offset, (int)RegIndex);
1188   }
1189 
1190   return Offset + 1;
1191 }
1192 
1193 int R600InstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
1194   int Offset = 0;
1195   const MachineFrameInfo &MFI = MF.getFrameInfo();
1196 
1197   // Variable sized objects are not supported
1198   if (MFI.hasVarSizedObjects()) {
1199     return -1;
1200   }
1201 
1202   if (MFI.getNumObjects() == 0) {
1203     return -1;
1204   }
1205 
1206   const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
1207   const R600FrameLowering *TFL = ST.getFrameLowering();
1208 
1209   unsigned IgnoredFrameReg;
1210   Offset = TFL->getFrameIndexReference(MF, -1, IgnoredFrameReg);
1211 
1212   return getIndirectIndexBegin(MF) + Offset;
1213 }
1214 
1215 unsigned R600InstrInfo::getMaxAlusPerClause() const {
1216   return 115;
1217 }
1218 
1219 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
1220                                                   MachineBasicBlock::iterator I,
1221                                                   unsigned Opcode,
1222                                                   unsigned DstReg,
1223                                                   unsigned Src0Reg,
1224                                                   unsigned Src1Reg) const {
1225   MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
1226     DstReg);           // $dst
1227 
1228   if (Src1Reg) {
1229     MIB.addImm(0)     // $update_exec_mask
1230        .addImm(0);    // $update_predicate
1231   }
1232   MIB.addImm(1)        // $write
1233      .addImm(0)        // $omod
1234      .addImm(0)        // $dst_rel
1235      .addImm(0)        // $dst_clamp
1236      .addReg(Src0Reg)  // $src0
1237      .addImm(0)        // $src0_neg
1238      .addImm(0)        // $src0_rel
1239      .addImm(0)        // $src0_abs
1240      .addImm(-1);       // $src0_sel
1241 
1242   if (Src1Reg) {
1243     MIB.addReg(Src1Reg) // $src1
1244        .addImm(0)       // $src1_neg
1245        .addImm(0)       // $src1_rel
1246        .addImm(0)       // $src1_abs
1247        .addImm(-1);      // $src1_sel
1248   }
1249 
1250   //XXX: The r600g finalizer expects this to be 1, once we've moved the
1251   //scheduling to the backend, we can change the default to 0.
1252   MIB.addImm(1)        // $last
1253       .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
1254       .addImm(0)         // $literal
1255       .addImm(0);        // $bank_swizzle
1256 
1257   return MIB;
1258 }
1259 
1260 #define OPERAND_CASE(Label) \
1261   case Label: { \
1262     static const unsigned Ops[] = \
1263     { \
1264       Label##_X, \
1265       Label##_Y, \
1266       Label##_Z, \
1267       Label##_W \
1268     }; \
1269     return Ops[Slot]; \
1270   }
1271 
1272 static unsigned getSlotedOps(unsigned  Op, unsigned Slot) {
1273   switch (Op) {
1274   OPERAND_CASE(AMDGPU::OpName::update_exec_mask)
1275   OPERAND_CASE(AMDGPU::OpName::update_pred)
1276   OPERAND_CASE(AMDGPU::OpName::write)
1277   OPERAND_CASE(AMDGPU::OpName::omod)
1278   OPERAND_CASE(AMDGPU::OpName::dst_rel)
1279   OPERAND_CASE(AMDGPU::OpName::clamp)
1280   OPERAND_CASE(AMDGPU::OpName::src0)
1281   OPERAND_CASE(AMDGPU::OpName::src0_neg)
1282   OPERAND_CASE(AMDGPU::OpName::src0_rel)
1283   OPERAND_CASE(AMDGPU::OpName::src0_abs)
1284   OPERAND_CASE(AMDGPU::OpName::src0_sel)
1285   OPERAND_CASE(AMDGPU::OpName::src1)
1286   OPERAND_CASE(AMDGPU::OpName::src1_neg)
1287   OPERAND_CASE(AMDGPU::OpName::src1_rel)
1288   OPERAND_CASE(AMDGPU::OpName::src1_abs)
1289   OPERAND_CASE(AMDGPU::OpName::src1_sel)
1290   OPERAND_CASE(AMDGPU::OpName::pred_sel)
1291   default:
1292     llvm_unreachable("Wrong Operand");
1293   }
1294 }
1295 
1296 #undef OPERAND_CASE
1297 
1298 MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction(
1299     MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg)
1300     const {
1301   assert (MI->getOpcode() == AMDGPU::DOT_4 && "Not Implemented");
1302   unsigned Opcode;
1303   if (ST.getGeneration() <= R600Subtarget::R700)
1304     Opcode = AMDGPU::DOT4_r600;
1305   else
1306     Opcode = AMDGPU::DOT4_eg;
1307   MachineBasicBlock::iterator I = MI;
1308   MachineOperand &Src0 = MI->getOperand(
1309       getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot)));
1310   MachineOperand &Src1 = MI->getOperand(
1311       getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot)));
1312   MachineInstr *MIB = buildDefaultInstruction(
1313       MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
1314   static const unsigned  Operands[14] = {
1315     AMDGPU::OpName::update_exec_mask,
1316     AMDGPU::OpName::update_pred,
1317     AMDGPU::OpName::write,
1318     AMDGPU::OpName::omod,
1319     AMDGPU::OpName::dst_rel,
1320     AMDGPU::OpName::clamp,
1321     AMDGPU::OpName::src0_neg,
1322     AMDGPU::OpName::src0_rel,
1323     AMDGPU::OpName::src0_abs,
1324     AMDGPU::OpName::src0_sel,
1325     AMDGPU::OpName::src1_neg,
1326     AMDGPU::OpName::src1_rel,
1327     AMDGPU::OpName::src1_abs,
1328     AMDGPU::OpName::src1_sel,
1329   };
1330 
1331   MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
1332       getSlotedOps(AMDGPU::OpName::pred_sel, Slot)));
1333   MIB->getOperand(getOperandIdx(Opcode, AMDGPU::OpName::pred_sel))
1334       .setReg(MO.getReg());
1335 
1336   for (unsigned i = 0; i < 14; i++) {
1337     MachineOperand &MO = MI->getOperand(
1338         getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
1339     assert (MO.isImm());
1340     setImmOperand(*MIB, Operands[i], MO.getImm());
1341   }
1342   MIB->getOperand(20).setImm(0);
1343   return MIB;
1344 }
1345 
1346 MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
1347                                          MachineBasicBlock::iterator I,
1348                                          unsigned DstReg,
1349                                          uint64_t Imm) const {
1350   MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
1351                                                   AMDGPU::ALU_LITERAL_X);
1352   setImmOperand(*MovImm, AMDGPU::OpName::literal, Imm);
1353   return MovImm;
1354 }
1355 
1356 MachineInstr *R600InstrInfo::buildMovInstr(MachineBasicBlock *MBB,
1357                                        MachineBasicBlock::iterator I,
1358                                        unsigned DstReg, unsigned SrcReg) const {
1359   return buildDefaultInstruction(*MBB, I, AMDGPU::MOV, DstReg, SrcReg);
1360 }
1361 
1362 int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const {
1363   return getOperandIdx(MI.getOpcode(), Op);
1364 }
1365 
1366 int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const {
1367   return AMDGPU::getNamedOperandIdx(Opcode, Op);
1368 }
1369 
1370 void R600InstrInfo::setImmOperand(MachineInstr &MI, unsigned Op,
1371                                   int64_t Imm) const {
1372   int Idx = getOperandIdx(MI, Op);
1373   assert(Idx != -1 && "Operand not supported for this instruction.");
1374   assert(MI.getOperand(Idx).isImm());
1375   MI.getOperand(Idx).setImm(Imm);
1376 }
1377 
1378 //===----------------------------------------------------------------------===//
1379 // Instruction flag getters/setters
1380 //===----------------------------------------------------------------------===//
1381 
1382 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx,
1383                                          unsigned Flag) const {
1384   unsigned TargetFlags = get(MI.getOpcode()).TSFlags;
1385   int FlagIndex = 0;
1386   if (Flag != 0) {
1387     // If we pass something other than the default value of Flag to this
1388     // function, it means we are want to set a flag on an instruction
1389     // that uses native encoding.
1390     assert(HAS_NATIVE_OPERANDS(TargetFlags));
1391     bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3;
1392     switch (Flag) {
1393     case MO_FLAG_CLAMP:
1394       FlagIndex = getOperandIdx(MI, AMDGPU::OpName::clamp);
1395       break;
1396     case MO_FLAG_MASK:
1397       FlagIndex = getOperandIdx(MI, AMDGPU::OpName::write);
1398       break;
1399     case MO_FLAG_NOT_LAST:
1400     case MO_FLAG_LAST:
1401       FlagIndex = getOperandIdx(MI, AMDGPU::OpName::last);
1402       break;
1403     case MO_FLAG_NEG:
1404       switch (SrcIdx) {
1405       case 0:
1406         FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src0_neg);
1407         break;
1408       case 1:
1409         FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src1_neg);
1410         break;
1411       case 2:
1412         FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src2_neg);
1413         break;
1414       }
1415       break;
1416 
1417     case MO_FLAG_ABS:
1418       assert(!IsOP3 && "Cannot set absolute value modifier for OP3 "
1419                        "instructions.");
1420       (void)IsOP3;
1421       switch (SrcIdx) {
1422       case 0:
1423         FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src0_abs);
1424         break;
1425       case 1:
1426         FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src1_abs);
1427         break;
1428       }
1429       break;
1430 
1431     default:
1432       FlagIndex = -1;
1433       break;
1434     }
1435     assert(FlagIndex != -1 && "Flag not supported for this instruction");
1436   } else {
1437       FlagIndex = GET_FLAG_OPERAND_IDX(TargetFlags);
1438       assert(FlagIndex != 0 &&
1439          "Instruction flags not supported for this instruction");
1440   }
1441 
1442   MachineOperand &FlagOp = MI.getOperand(FlagIndex);
1443   assert(FlagOp.isImm());
1444   return FlagOp;
1445 }
1446 
1447 void R600InstrInfo::addFlag(MachineInstr &MI, unsigned Operand,
1448                             unsigned Flag) const {
1449   unsigned TargetFlags = get(MI.getOpcode()).TSFlags;
1450   if (Flag == 0) {
1451     return;
1452   }
1453   if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1454     MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1455     if (Flag == MO_FLAG_NOT_LAST) {
1456       clearFlag(MI, Operand, MO_FLAG_LAST);
1457     } else if (Flag == MO_FLAG_MASK) {
1458       clearFlag(MI, Operand, Flag);
1459     } else {
1460       FlagOp.setImm(1);
1461     }
1462   } else {
1463       MachineOperand &FlagOp = getFlagOp(MI, Operand);
1464       FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
1465   }
1466 }
1467 
1468 void R600InstrInfo::clearFlag(MachineInstr &MI, unsigned Operand,
1469                               unsigned Flag) const {
1470   unsigned TargetFlags = get(MI.getOpcode()).TSFlags;
1471   if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1472     MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1473     FlagOp.setImm(0);
1474   } else {
1475     MachineOperand &FlagOp = getFlagOp(MI);
1476     unsigned InstFlags = FlagOp.getImm();
1477     InstFlags &= ~(Flag << (NUM_MO_FLAGS * Operand));
1478     FlagOp.setImm(InstFlags);
1479   }
1480 }
1481 
1482 bool R600InstrInfo::isRegisterStore(const MachineInstr &MI) const {
1483   return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE;
1484 }
1485 
1486 bool R600InstrInfo::isRegisterLoad(const MachineInstr &MI) const {
1487   return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;
1488 }
1489