1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief R600 Implementation of TargetInstrInfo.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "R600InstrInfo.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUSubtarget.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "R600Defines.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 
26 using namespace llvm;
27 
28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "AMDGPUGenDFAPacketizer.inc"
30 
31 R600InstrInfo::R600InstrInfo(const R600Subtarget &ST)
32   : AMDGPUInstrInfo(ST), RI(), ST(ST) {}
33 
34 bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
35   return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
36 }
37 
38 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
39   return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
40 }
41 
42 void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
43                                 MachineBasicBlock::iterator MI,
44                                 const DebugLoc &DL, unsigned DestReg,
45                                 unsigned SrcReg, bool KillSrc) const {
46   unsigned VectorComponents = 0;
47   if ((AMDGPU::R600_Reg128RegClass.contains(DestReg) ||
48       AMDGPU::R600_Reg128VerticalRegClass.contains(DestReg)) &&
49       (AMDGPU::R600_Reg128RegClass.contains(SrcReg) ||
50        AMDGPU::R600_Reg128VerticalRegClass.contains(SrcReg))) {
51     VectorComponents = 4;
52   } else if((AMDGPU::R600_Reg64RegClass.contains(DestReg) ||
53             AMDGPU::R600_Reg64VerticalRegClass.contains(DestReg)) &&
54             (AMDGPU::R600_Reg64RegClass.contains(SrcReg) ||
55              AMDGPU::R600_Reg64VerticalRegClass.contains(SrcReg))) {
56     VectorComponents = 2;
57   }
58 
59   if (VectorComponents > 0) {
60     for (unsigned I = 0; I < VectorComponents; I++) {
61       unsigned SubRegIndex = RI.getSubRegFromChannel(I);
62       buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
63                               RI.getSubReg(DestReg, SubRegIndex),
64                               RI.getSubReg(SrcReg, SubRegIndex))
65                               .addReg(DestReg,
66                                       RegState::Define | RegState::Implicit);
67     }
68   } else {
69     MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
70                                                   DestReg, SrcReg);
71     NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0))
72                                     .setIsKill(KillSrc);
73   }
74 }
75 
76 /// \returns true if \p MBBI can be moved into a new basic.
77 bool R600InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
78                                        MachineBasicBlock::iterator MBBI) const {
79   for (MachineInstr::const_mop_iterator I = MBBI->operands_begin(),
80                                         E = MBBI->operands_end(); I != E; ++I) {
81     if (I->isReg() && !TargetRegisterInfo::isVirtualRegister(I->getReg()) &&
82         I->isUse() && RI.isPhysRegLiveAcrossClauses(I->getReg()))
83       return false;
84   }
85   return true;
86 }
87 
88 bool R600InstrInfo::isMov(unsigned Opcode) const {
89   switch(Opcode) {
90   default:
91     return false;
92   case AMDGPU::MOV:
93   case AMDGPU::MOV_IMM_F32:
94   case AMDGPU::MOV_IMM_I32:
95     return true;
96   }
97 }
98 
99 // Some instructions act as place holders to emulate operations that the GPU
100 // hardware does automatically. This function can be used to check if
101 // an opcode falls into this category.
102 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {
103   switch (Opcode) {
104   default: return false;
105   case AMDGPU::RETURN:
106     return true;
107   }
108 }
109 
110 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
111   return false;
112 }
113 
114 bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
115   switch(Opcode) {
116     default: return false;
117     case AMDGPU::CUBE_r600_pseudo:
118     case AMDGPU::CUBE_r600_real:
119     case AMDGPU::CUBE_eg_pseudo:
120     case AMDGPU::CUBE_eg_real:
121       return true;
122   }
123 }
124 
125 bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
126   unsigned TargetFlags = get(Opcode).TSFlags;
127 
128   return (TargetFlags & R600_InstFlag::ALU_INST);
129 }
130 
131 bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const {
132   unsigned TargetFlags = get(Opcode).TSFlags;
133 
134   return ((TargetFlags & R600_InstFlag::OP1) |
135           (TargetFlags & R600_InstFlag::OP2) |
136           (TargetFlags & R600_InstFlag::OP3));
137 }
138 
139 bool R600InstrInfo::isLDSInstr(unsigned Opcode) const {
140   unsigned TargetFlags = get(Opcode).TSFlags;
141 
142   return ((TargetFlags & R600_InstFlag::LDS_1A) |
143           (TargetFlags & R600_InstFlag::LDS_1A1D) |
144           (TargetFlags & R600_InstFlag::LDS_1A2D));
145 }
146 
147 bool R600InstrInfo::isLDSNoRetInstr(unsigned Opcode) const {
148   return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) == -1;
149 }
150 
151 bool R600InstrInfo::isLDSRetInstr(unsigned Opcode) const {
152   return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) != -1;
153 }
154 
155 bool R600InstrInfo::canBeConsideredALU(const MachineInstr &MI) const {
156   if (isALUInstr(MI.getOpcode()))
157     return true;
158   if (isVector(MI) || isCubeOp(MI.getOpcode()))
159     return true;
160   switch (MI.getOpcode()) {
161   case AMDGPU::PRED_X:
162   case AMDGPU::INTERP_PAIR_XY:
163   case AMDGPU::INTERP_PAIR_ZW:
164   case AMDGPU::INTERP_VEC_LOAD:
165   case AMDGPU::COPY:
166   case AMDGPU::DOT_4:
167     return true;
168   default:
169     return false;
170   }
171 }
172 
173 bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
174   if (ST.hasCaymanISA())
175     return false;
176   return (get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU);
177 }
178 
179 bool R600InstrInfo::isTransOnly(const MachineInstr &MI) const {
180   return isTransOnly(MI.getOpcode());
181 }
182 
183 bool R600InstrInfo::isVectorOnly(unsigned Opcode) const {
184   return (get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU);
185 }
186 
187 bool R600InstrInfo::isVectorOnly(const MachineInstr &MI) const {
188   return isVectorOnly(MI.getOpcode());
189 }
190 
191 bool R600InstrInfo::isExport(unsigned Opcode) const {
192   return (get(Opcode).TSFlags & R600_InstFlag::IS_EXPORT);
193 }
194 
195 bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
196   return ST.hasVertexCache() && IS_VTX(get(Opcode));
197 }
198 
199 bool R600InstrInfo::usesVertexCache(const MachineInstr &MI) const {
200   const MachineFunction *MF = MI.getParent()->getParent();
201   return !AMDGPU::isCompute(MF->getFunction()->getCallingConv()) &&
202          usesVertexCache(MI.getOpcode());
203 }
204 
205 bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {
206   return (!ST.hasVertexCache() && IS_VTX(get(Opcode))) || IS_TEX(get(Opcode));
207 }
208 
209 bool R600InstrInfo::usesTextureCache(const MachineInstr &MI) const {
210   const MachineFunction *MF = MI.getParent()->getParent();
211   return (AMDGPU::isCompute(MF->getFunction()->getCallingConv()) &&
212           usesVertexCache(MI.getOpcode())) ||
213          usesTextureCache(MI.getOpcode());
214 }
215 
216 bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const {
217   switch (Opcode) {
218   case AMDGPU::KILLGT:
219   case AMDGPU::GROUP_BARRIER:
220     return true;
221   default:
222     return false;
223   }
224 }
225 
226 bool R600InstrInfo::usesAddressRegister(MachineInstr &MI) const {
227   return MI.findRegisterUseOperandIdx(AMDGPU::AR_X) != -1;
228 }
229 
230 bool R600InstrInfo::definesAddressRegister(MachineInstr &MI) const {
231   return MI.findRegisterDefOperandIdx(AMDGPU::AR_X) != -1;
232 }
233 
234 bool R600InstrInfo::readsLDSSrcReg(const MachineInstr &MI) const {
235   if (!isALUInstr(MI.getOpcode())) {
236     return false;
237   }
238   for (MachineInstr::const_mop_iterator I = MI.operands_begin(),
239                                         E = MI.operands_end();
240        I != E; ++I) {
241     if (!I->isReg() || !I->isUse() ||
242         TargetRegisterInfo::isVirtualRegister(I->getReg()))
243       continue;
244 
245     if (AMDGPU::R600_LDS_SRC_REGRegClass.contains(I->getReg()))
246       return true;
247   }
248   return false;
249 }
250 
251 int R600InstrInfo::getSrcIdx(unsigned Opcode, unsigned SrcNum) const {
252   static const unsigned OpTable[] = {
253     AMDGPU::OpName::src0,
254     AMDGPU::OpName::src1,
255     AMDGPU::OpName::src2
256   };
257 
258   assert (SrcNum < 3);
259   return getOperandIdx(Opcode, OpTable[SrcNum]);
260 }
261 
262 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const {
263   static const unsigned SrcSelTable[][2] = {
264     {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
265     {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
266     {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
267     {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
268     {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
269     {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
270     {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
271     {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
272     {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
273     {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
274     {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W}
275   };
276 
277   for (const auto &Row : SrcSelTable) {
278     if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) {
279       return getOperandIdx(Opcode, Row[1]);
280     }
281   }
282   return -1;
283 }
284 
285 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
286 R600InstrInfo::getSrcs(MachineInstr &MI) const {
287   SmallVector<std::pair<MachineOperand *, int64_t>, 3> Result;
288 
289   if (MI.getOpcode() == AMDGPU::DOT_4) {
290     static const unsigned OpTable[8][2] = {
291       {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
292       {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
293       {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
294       {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
295       {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
296       {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
297       {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
298       {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W},
299     };
300 
301     for (unsigned j = 0; j < 8; j++) {
302       MachineOperand &MO =
303           MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][0]));
304       unsigned Reg = MO.getReg();
305       if (Reg == AMDGPU::ALU_CONST) {
306         MachineOperand &Sel =
307             MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1]));
308         Result.push_back(std::make_pair(&MO, Sel.getImm()));
309         continue;
310       }
311 
312     }
313     return Result;
314   }
315 
316   static const unsigned OpTable[3][2] = {
317     {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
318     {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
319     {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
320   };
321 
322   for (unsigned j = 0; j < 3; j++) {
323     int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]);
324     if (SrcIdx < 0)
325       break;
326     MachineOperand &MO = MI.getOperand(SrcIdx);
327     unsigned Reg = MO.getReg();
328     if (Reg == AMDGPU::ALU_CONST) {
329       MachineOperand &Sel =
330           MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1]));
331       Result.push_back(std::make_pair(&MO, Sel.getImm()));
332       continue;
333     }
334     if (Reg == AMDGPU::ALU_LITERAL_X) {
335       MachineOperand &Operand =
336           MI.getOperand(getOperandIdx(MI.getOpcode(), AMDGPU::OpName::literal));
337       if (Operand.isImm()) {
338         Result.push_back(std::make_pair(&MO, Operand.getImm()));
339         continue;
340       }
341       assert(Operand.isGlobal());
342     }
343     Result.push_back(std::make_pair(&MO, 0));
344   }
345   return Result;
346 }
347 
348 std::vector<std::pair<int, unsigned>>
349 R600InstrInfo::ExtractSrcs(MachineInstr &MI,
350                            const DenseMap<unsigned, unsigned> &PV,
351                            unsigned &ConstCount) const {
352   ConstCount = 0;
353   ArrayRef<std::pair<MachineOperand *, int64_t>> Srcs = getSrcs(MI);
354   const std::pair<int, unsigned> DummyPair(-1, 0);
355   std::vector<std::pair<int, unsigned> > Result;
356   unsigned i = 0;
357   for (unsigned n = Srcs.size(); i < n; ++i) {
358     unsigned Reg = Srcs[i].first->getReg();
359     int Index = RI.getEncodingValue(Reg) & 0xff;
360     if (Reg == AMDGPU::OQAP) {
361       Result.push_back(std::make_pair(Index, 0U));
362     }
363     if (PV.find(Reg) != PV.end()) {
364       // 255 is used to tells its a PS/PV reg
365       Result.push_back(std::make_pair(255, 0U));
366       continue;
367     }
368     if (Index > 127) {
369       ConstCount++;
370       Result.push_back(DummyPair);
371       continue;
372     }
373     unsigned Chan = RI.getHWRegChan(Reg);
374     Result.push_back(std::make_pair(Index, Chan));
375   }
376   for (; i < 3; ++i)
377     Result.push_back(DummyPair);
378   return Result;
379 }
380 
381 static std::vector<std::pair<int, unsigned> >
382 Swizzle(std::vector<std::pair<int, unsigned> > Src,
383         R600InstrInfo::BankSwizzle Swz) {
384   if (Src[0] == Src[1])
385     Src[1].first = -1;
386   switch (Swz) {
387   case R600InstrInfo::ALU_VEC_012_SCL_210:
388     break;
389   case R600InstrInfo::ALU_VEC_021_SCL_122:
390     std::swap(Src[1], Src[2]);
391     break;
392   case R600InstrInfo::ALU_VEC_102_SCL_221:
393     std::swap(Src[0], Src[1]);
394     break;
395   case R600InstrInfo::ALU_VEC_120_SCL_212:
396     std::swap(Src[0], Src[1]);
397     std::swap(Src[0], Src[2]);
398     break;
399   case R600InstrInfo::ALU_VEC_201:
400     std::swap(Src[0], Src[2]);
401     std::swap(Src[0], Src[1]);
402     break;
403   case R600InstrInfo::ALU_VEC_210:
404     std::swap(Src[0], Src[2]);
405     break;
406   }
407   return Src;
408 }
409 
410 static unsigned
411 getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) {
412   switch (Swz) {
413   case R600InstrInfo::ALU_VEC_012_SCL_210: {
414     unsigned Cycles[3] = { 2, 1, 0};
415     return Cycles[Op];
416   }
417   case R600InstrInfo::ALU_VEC_021_SCL_122: {
418     unsigned Cycles[3] = { 1, 2, 2};
419     return Cycles[Op];
420   }
421   case R600InstrInfo::ALU_VEC_120_SCL_212: {
422     unsigned Cycles[3] = { 2, 1, 2};
423     return Cycles[Op];
424   }
425   case R600InstrInfo::ALU_VEC_102_SCL_221: {
426     unsigned Cycles[3] = { 2, 2, 1};
427     return Cycles[Op];
428   }
429   default:
430     llvm_unreachable("Wrong Swizzle for Trans Slot");
431     return 0;
432   }
433 }
434 
435 /// returns how many MIs (whose inputs are represented by IGSrcs) can be packed
436 /// in the same Instruction Group while meeting read port limitations given a
437 /// Swz swizzle sequence.
438 unsigned  R600InstrInfo::isLegalUpTo(
439     const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
440     const std::vector<R600InstrInfo::BankSwizzle> &Swz,
441     const std::vector<std::pair<int, unsigned> > &TransSrcs,
442     R600InstrInfo::BankSwizzle TransSwz) const {
443   int Vector[4][3];
444   memset(Vector, -1, sizeof(Vector));
445   for (unsigned i = 0, e = IGSrcs.size(); i < e; i++) {
446     const std::vector<std::pair<int, unsigned> > &Srcs =
447         Swizzle(IGSrcs[i], Swz[i]);
448     for (unsigned j = 0; j < 3; j++) {
449       const std::pair<int, unsigned> &Src = Srcs[j];
450       if (Src.first < 0 || Src.first == 255)
451         continue;
452       if (Src.first == GET_REG_INDEX(RI.getEncodingValue(AMDGPU::OQAP))) {
453         if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 &&
454             Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) {
455             // The value from output queue A (denoted by register OQAP) can
456             // only be fetched during the first cycle.
457             return false;
458         }
459         // OQAP does not count towards the normal read port restrictions
460         continue;
461       }
462       if (Vector[Src.second][j] < 0)
463         Vector[Src.second][j] = Src.first;
464       if (Vector[Src.second][j] != Src.first)
465         return i;
466     }
467   }
468   // Now check Trans Alu
469   for (unsigned i = 0, e = TransSrcs.size(); i < e; ++i) {
470     const std::pair<int, unsigned> &Src = TransSrcs[i];
471     unsigned Cycle = getTransSwizzle(TransSwz, i);
472     if (Src.first < 0)
473       continue;
474     if (Src.first == 255)
475       continue;
476     if (Vector[Src.second][Cycle] < 0)
477       Vector[Src.second][Cycle] = Src.first;
478     if (Vector[Src.second][Cycle] != Src.first)
479       return IGSrcs.size() - 1;
480   }
481   return IGSrcs.size();
482 }
483 
484 /// Given a swizzle sequence SwzCandidate and an index Idx, returns the next
485 /// (in lexicographic term) swizzle sequence assuming that all swizzles after
486 /// Idx can be skipped
487 static bool
488 NextPossibleSolution(
489     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
490     unsigned Idx) {
491   assert(Idx < SwzCandidate.size());
492   int ResetIdx = Idx;
493   while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210)
494     ResetIdx --;
495   for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) {
496     SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210;
497   }
498   if (ResetIdx == -1)
499     return false;
500   int NextSwizzle = SwzCandidate[ResetIdx] + 1;
501   SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle;
502   return true;
503 }
504 
505 /// Enumerate all possible Swizzle sequence to find one that can meet all
506 /// read port requirements.
507 bool R600InstrInfo::FindSwizzleForVectorSlot(
508     const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
509     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
510     const std::vector<std::pair<int, unsigned> > &TransSrcs,
511     R600InstrInfo::BankSwizzle TransSwz) const {
512   unsigned ValidUpTo = 0;
513   do {
514     ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz);
515     if (ValidUpTo == IGSrcs.size())
516       return true;
517   } while (NextPossibleSolution(SwzCandidate, ValidUpTo));
518   return false;
519 }
520 
521 /// Instructions in Trans slot can't read gpr at cycle 0 if they also read
522 /// a const, and can't read a gpr at cycle 1 if they read 2 const.
523 static bool
524 isConstCompatible(R600InstrInfo::BankSwizzle TransSwz,
525                   const std::vector<std::pair<int, unsigned> > &TransOps,
526                   unsigned ConstCount) {
527   // TransALU can't read 3 constants
528   if (ConstCount > 2)
529     return false;
530   for (unsigned i = 0, e = TransOps.size(); i < e; ++i) {
531     const std::pair<int, unsigned> &Src = TransOps[i];
532     unsigned Cycle = getTransSwizzle(TransSwz, i);
533     if (Src.first < 0)
534       continue;
535     if (ConstCount > 0 && Cycle == 0)
536       return false;
537     if (ConstCount > 1 && Cycle == 1)
538       return false;
539   }
540   return true;
541 }
542 
543 bool
544 R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
545                                        const DenseMap<unsigned, unsigned> &PV,
546                                        std::vector<BankSwizzle> &ValidSwizzle,
547                                        bool isLastAluTrans)
548     const {
549   //Todo : support shared src0 - src1 operand
550 
551   std::vector<std::vector<std::pair<int, unsigned> > > IGSrcs;
552   ValidSwizzle.clear();
553   unsigned ConstCount;
554   BankSwizzle TransBS = ALU_VEC_012_SCL_210;
555   for (unsigned i = 0, e = IG.size(); i < e; ++i) {
556     IGSrcs.push_back(ExtractSrcs(*IG[i], PV, ConstCount));
557     unsigned Op = getOperandIdx(IG[i]->getOpcode(),
558         AMDGPU::OpName::bank_swizzle);
559     ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle)
560         IG[i]->getOperand(Op).getImm());
561   }
562   std::vector<std::pair<int, unsigned> > TransOps;
563   if (!isLastAluTrans)
564     return FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps, TransBS);
565 
566   TransOps = std::move(IGSrcs.back());
567   IGSrcs.pop_back();
568   ValidSwizzle.pop_back();
569 
570   static const R600InstrInfo::BankSwizzle TransSwz[] = {
571     ALU_VEC_012_SCL_210,
572     ALU_VEC_021_SCL_122,
573     ALU_VEC_120_SCL_212,
574     ALU_VEC_102_SCL_221
575   };
576   for (unsigned i = 0; i < 4; i++) {
577     TransBS = TransSwz[i];
578     if (!isConstCompatible(TransBS, TransOps, ConstCount))
579       continue;
580     bool Result = FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps,
581         TransBS);
582     if (Result) {
583       ValidSwizzle.push_back(TransBS);
584       return true;
585     }
586   }
587 
588   return false;
589 }
590 
591 
592 bool
593 R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)
594     const {
595   assert (Consts.size() <= 12 && "Too many operands in instructions group");
596   unsigned Pair1 = 0, Pair2 = 0;
597   for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
598     unsigned ReadConstHalf = Consts[i] & 2;
599     unsigned ReadConstIndex = Consts[i] & (~3);
600     unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
601     if (!Pair1) {
602       Pair1 = ReadHalfConst;
603       continue;
604     }
605     if (Pair1 == ReadHalfConst)
606       continue;
607     if (!Pair2) {
608       Pair2 = ReadHalfConst;
609       continue;
610     }
611     if (Pair2 != ReadHalfConst)
612       return false;
613   }
614   return true;
615 }
616 
617 bool
618 R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs)
619     const {
620   std::vector<unsigned> Consts;
621   SmallSet<int64_t, 4> Literals;
622   for (unsigned i = 0, n = MIs.size(); i < n; i++) {
623     MachineInstr &MI = *MIs[i];
624     if (!isALUInstr(MI.getOpcode()))
625       continue;
626 
627     ArrayRef<std::pair<MachineOperand *, int64_t>> Srcs = getSrcs(MI);
628 
629     for (const auto &Src:Srcs) {
630       if (Src.first->getReg() == AMDGPU::ALU_LITERAL_X)
631         Literals.insert(Src.second);
632       if (Literals.size() > 4)
633         return false;
634       if (Src.first->getReg() == AMDGPU::ALU_CONST)
635         Consts.push_back(Src.second);
636       if (AMDGPU::R600_KC0RegClass.contains(Src.first->getReg()) ||
637           AMDGPU::R600_KC1RegClass.contains(Src.first->getReg())) {
638         unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
639         unsigned Chan = RI.getHWRegChan(Src.first->getReg());
640         Consts.push_back((Index << 2) | Chan);
641       }
642     }
643   }
644   return fitsConstReadLimitations(Consts);
645 }
646 
647 DFAPacketizer *
648 R600InstrInfo::CreateTargetScheduleState(const TargetSubtargetInfo &STI) const {
649   const InstrItineraryData *II = STI.getInstrItineraryData();
650   return static_cast<const R600Subtarget &>(STI).createDFAPacketizer(II);
651 }
652 
653 static bool
654 isPredicateSetter(unsigned Opcode) {
655   switch (Opcode) {
656   case AMDGPU::PRED_X:
657     return true;
658   default:
659     return false;
660   }
661 }
662 
663 static MachineInstr *
664 findFirstPredicateSetterFrom(MachineBasicBlock &MBB,
665                              MachineBasicBlock::iterator I) {
666   while (I != MBB.begin()) {
667     --I;
668     MachineInstr *MI = I;
669     if (isPredicateSetter(MI->getOpcode()))
670       return MI;
671   }
672 
673   return nullptr;
674 }
675 
676 static
677 bool isJump(unsigned Opcode) {
678   return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND;
679 }
680 
681 static bool isBranch(unsigned Opcode) {
682   return Opcode == AMDGPU::BRANCH || Opcode == AMDGPU::BRANCH_COND_i32 ||
683       Opcode == AMDGPU::BRANCH_COND_f32;
684 }
685 
686 bool
687 R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
688                              MachineBasicBlock *&TBB,
689                              MachineBasicBlock *&FBB,
690                              SmallVectorImpl<MachineOperand> &Cond,
691                              bool AllowModify) const {
692   // Most of the following comes from the ARM implementation of AnalyzeBranch
693 
694   // If the block has no terminators, it just falls into the block after it.
695   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
696   if (I == MBB.end())
697     return false;
698 
699   // AMDGPU::BRANCH* instructions are only available after isel and are not
700   // handled
701   if (isBranch(I->getOpcode()))
702     return true;
703   if (!isJump(static_cast<MachineInstr *>(I)->getOpcode())) {
704     return false;
705   }
706 
707   // Remove successive JUMP
708   while (I != MBB.begin() && std::prev(I)->getOpcode() == AMDGPU::JUMP) {
709       MachineBasicBlock::iterator PriorI = std::prev(I);
710       if (AllowModify)
711         I->removeFromParent();
712       I = PriorI;
713   }
714   MachineInstr *LastInst = I;
715 
716   // If there is only one terminator instruction, process it.
717   unsigned LastOpc = LastInst->getOpcode();
718   if (I == MBB.begin() ||
719           !isJump(static_cast<MachineInstr *>(--I)->getOpcode())) {
720     if (LastOpc == AMDGPU::JUMP) {
721       TBB = LastInst->getOperand(0).getMBB();
722       return false;
723     } else if (LastOpc == AMDGPU::JUMP_COND) {
724       MachineInstr *predSet = I;
725       while (!isPredicateSetter(predSet->getOpcode())) {
726         predSet = --I;
727       }
728       TBB = LastInst->getOperand(0).getMBB();
729       Cond.push_back(predSet->getOperand(1));
730       Cond.push_back(predSet->getOperand(2));
731       Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
732       return false;
733     }
734     return true;  // Can't handle indirect branch.
735   }
736 
737   // Get the instruction before it if it is a terminator.
738   MachineInstr *SecondLastInst = I;
739   unsigned SecondLastOpc = SecondLastInst->getOpcode();
740 
741   // If the block ends with a B and a Bcc, handle it.
742   if (SecondLastOpc == AMDGPU::JUMP_COND && LastOpc == AMDGPU::JUMP) {
743     MachineInstr *predSet = --I;
744     while (!isPredicateSetter(predSet->getOpcode())) {
745       predSet = --I;
746     }
747     TBB = SecondLastInst->getOperand(0).getMBB();
748     FBB = LastInst->getOperand(0).getMBB();
749     Cond.push_back(predSet->getOperand(1));
750     Cond.push_back(predSet->getOperand(2));
751     Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
752     return false;
753   }
754 
755   // Otherwise, can't handle this.
756   return true;
757 }
758 
759 static
760 MachineBasicBlock::iterator FindLastAluClause(MachineBasicBlock &MBB) {
761   for (MachineBasicBlock::reverse_iterator It = MBB.rbegin(), E = MBB.rend();
762       It != E; ++It) {
763     if (It->getOpcode() == AMDGPU::CF_ALU ||
764         It->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
765       return std::prev(It.base());
766   }
767   return MBB.end();
768 }
769 
770 unsigned R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
771                                      MachineBasicBlock *TBB,
772                                      MachineBasicBlock *FBB,
773                                      ArrayRef<MachineOperand> Cond,
774                                      const DebugLoc &DL) const {
775   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
776 
777   if (!FBB) {
778     if (Cond.empty()) {
779       BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB);
780       return 1;
781     } else {
782       MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
783       assert(PredSet && "No previous predicate !");
784       addFlag(*PredSet, 0, MO_FLAG_PUSH);
785       PredSet->getOperand(2).setImm(Cond[1].getImm());
786 
787       BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
788              .addMBB(TBB)
789              .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
790       MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
791       if (CfAlu == MBB.end())
792         return 1;
793       assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
794       CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
795       return 1;
796     }
797   } else {
798     MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
799     assert(PredSet && "No previous predicate !");
800     addFlag(*PredSet, 0, MO_FLAG_PUSH);
801     PredSet->getOperand(2).setImm(Cond[1].getImm());
802     BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
803             .addMBB(TBB)
804             .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
805     BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB);
806     MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
807     if (CfAlu == MBB.end())
808       return 2;
809     assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
810     CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
811     return 2;
812   }
813 }
814 
815 unsigned
816 R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
817 
818   // Note : we leave PRED* instructions there.
819   // They may be needed when predicating instructions.
820 
821   MachineBasicBlock::iterator I = MBB.end();
822 
823   if (I == MBB.begin()) {
824     return 0;
825   }
826   --I;
827   switch (I->getOpcode()) {
828   default:
829     return 0;
830   case AMDGPU::JUMP_COND: {
831     MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
832     clearFlag(*predSet, 0, MO_FLAG_PUSH);
833     I->eraseFromParent();
834     MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
835     if (CfAlu == MBB.end())
836       break;
837     assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
838     CfAlu->setDesc(get(AMDGPU::CF_ALU));
839     break;
840   }
841   case AMDGPU::JUMP:
842     I->eraseFromParent();
843     break;
844   }
845   I = MBB.end();
846 
847   if (I == MBB.begin()) {
848     return 1;
849   }
850   --I;
851   switch (I->getOpcode()) {
852     // FIXME: only one case??
853   default:
854     return 1;
855   case AMDGPU::JUMP_COND: {
856     MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
857     clearFlag(*predSet, 0, MO_FLAG_PUSH);
858     I->eraseFromParent();
859     MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
860     if (CfAlu == MBB.end())
861       break;
862     assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
863     CfAlu->setDesc(get(AMDGPU::CF_ALU));
864     break;
865   }
866   case AMDGPU::JUMP:
867     I->eraseFromParent();
868     break;
869   }
870   return 2;
871 }
872 
873 bool R600InstrInfo::isPredicated(const MachineInstr &MI) const {
874   int idx = MI.findFirstPredOperandIdx();
875   if (idx < 0)
876     return false;
877 
878   unsigned Reg = MI.getOperand(idx).getReg();
879   switch (Reg) {
880   default: return false;
881   case AMDGPU::PRED_SEL_ONE:
882   case AMDGPU::PRED_SEL_ZERO:
883   case AMDGPU::PREDICATE_BIT:
884     return true;
885   }
886 }
887 
888 bool R600InstrInfo::isPredicable(MachineInstr &MI) const {
889   // XXX: KILL* instructions can be predicated, but they must be the last
890   // instruction in a clause, so this means any instructions after them cannot
891   // be predicated.  Until we have proper support for instruction clauses in the
892   // backend, we will mark KILL* instructions as unpredicable.
893 
894   if (MI.getOpcode() == AMDGPU::KILLGT) {
895     return false;
896   } else if (MI.getOpcode() == AMDGPU::CF_ALU) {
897     // If the clause start in the middle of MBB then the MBB has more
898     // than a single clause, unable to predicate several clauses.
899     if (MI.getParent()->begin() != MachineBasicBlock::iterator(MI))
900       return false;
901     // TODO: We don't support KC merging atm
902     return MI.getOperand(3).getImm() == 0 && MI.getOperand(4).getImm() == 0;
903   } else if (isVector(MI)) {
904     return false;
905   } else {
906     return AMDGPUInstrInfo::isPredicable(MI);
907   }
908 }
909 
910 
911 bool
912 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
913                                    unsigned NumCyles,
914                                    unsigned ExtraPredCycles,
915                                    BranchProbability Probability) const{
916   return true;
917 }
918 
919 bool
920 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
921                                    unsigned NumTCycles,
922                                    unsigned ExtraTCycles,
923                                    MachineBasicBlock &FMBB,
924                                    unsigned NumFCycles,
925                                    unsigned ExtraFCycles,
926                                    BranchProbability Probability) const {
927   return true;
928 }
929 
930 bool
931 R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
932                                          unsigned NumCyles,
933                                          BranchProbability Probability)
934                                          const {
935   return true;
936 }
937 
938 bool
939 R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
940                                          MachineBasicBlock &FMBB) const {
941   return false;
942 }
943 
944 
945 bool
946 R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
947   MachineOperand &MO = Cond[1];
948   switch (MO.getImm()) {
949   case OPCODE_IS_ZERO_INT:
950     MO.setImm(OPCODE_IS_NOT_ZERO_INT);
951     break;
952   case OPCODE_IS_NOT_ZERO_INT:
953     MO.setImm(OPCODE_IS_ZERO_INT);
954     break;
955   case OPCODE_IS_ZERO:
956     MO.setImm(OPCODE_IS_NOT_ZERO);
957     break;
958   case OPCODE_IS_NOT_ZERO:
959     MO.setImm(OPCODE_IS_ZERO);
960     break;
961   default:
962     return true;
963   }
964 
965   MachineOperand &MO2 = Cond[2];
966   switch (MO2.getReg()) {
967   case AMDGPU::PRED_SEL_ZERO:
968     MO2.setReg(AMDGPU::PRED_SEL_ONE);
969     break;
970   case AMDGPU::PRED_SEL_ONE:
971     MO2.setReg(AMDGPU::PRED_SEL_ZERO);
972     break;
973   default:
974     return true;
975   }
976   return false;
977 }
978 
979 bool R600InstrInfo::DefinesPredicate(MachineInstr &MI,
980                                      std::vector<MachineOperand> &Pred) const {
981   return isPredicateSetter(MI.getOpcode());
982 }
983 
984 
985 bool
986 R600InstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
987                                  ArrayRef<MachineOperand> Pred2) const {
988   return false;
989 }
990 
991 bool R600InstrInfo::PredicateInstruction(MachineInstr &MI,
992                                          ArrayRef<MachineOperand> Pred) const {
993   int PIdx = MI.findFirstPredOperandIdx();
994 
995   if (MI.getOpcode() == AMDGPU::CF_ALU) {
996     MI.getOperand(8).setImm(0);
997     return true;
998   }
999 
1000   if (MI.getOpcode() == AMDGPU::DOT_4) {
1001     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_X))
1002         .setReg(Pred[2].getReg());
1003     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_Y))
1004         .setReg(Pred[2].getReg());
1005     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_Z))
1006         .setReg(Pred[2].getReg());
1007     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_W))
1008         .setReg(Pred[2].getReg());
1009     MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
1010     MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
1011     return true;
1012   }
1013 
1014   if (PIdx != -1) {
1015     MachineOperand &PMO = MI.getOperand(PIdx);
1016     PMO.setReg(Pred[2].getReg());
1017     MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
1018     MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
1019     return true;
1020   }
1021 
1022   return false;
1023 }
1024 
1025 unsigned int R600InstrInfo::getPredicationCost(const MachineInstr &) const {
1026   return 2;
1027 }
1028 
1029 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1030                                             const MachineInstr &,
1031                                             unsigned *PredCost) const {
1032   if (PredCost)
1033     *PredCost = 2;
1034   return 2;
1035 }
1036 
1037 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex,
1038                                                    unsigned Channel) const {
1039   assert(Channel == 0);
1040   return RegIndex;
1041 }
1042 
1043 bool R600InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1044   switch (MI.getOpcode()) {
1045   default: {
1046     MachineBasicBlock *MBB = MI.getParent();
1047     int OffsetOpIdx =
1048         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::addr);
1049     // addr is a custom operand with multiple MI operands, and only the
1050     // first MI operand is given a name.
1051     int RegOpIdx = OffsetOpIdx + 1;
1052     int ChanOpIdx =
1053         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::chan);
1054     if (isRegisterLoad(MI)) {
1055       int DstOpIdx =
1056           AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst);
1057       unsigned RegIndex = MI.getOperand(RegOpIdx).getImm();
1058       unsigned Channel = MI.getOperand(ChanOpIdx).getImm();
1059       unsigned Address = calculateIndirectAddress(RegIndex, Channel);
1060       unsigned OffsetReg = MI.getOperand(OffsetOpIdx).getReg();
1061       if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
1062         buildMovInstr(MBB, MI, MI.getOperand(DstOpIdx).getReg(),
1063                       getIndirectAddrRegClass()->getRegister(Address));
1064       } else {
1065         buildIndirectRead(MBB, MI, MI.getOperand(DstOpIdx).getReg(), Address,
1066                           OffsetReg);
1067       }
1068     } else if (isRegisterStore(MI)) {
1069       int ValOpIdx =
1070           AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::val);
1071       unsigned RegIndex = MI.getOperand(RegOpIdx).getImm();
1072       unsigned Channel = MI.getOperand(ChanOpIdx).getImm();
1073       unsigned Address = calculateIndirectAddress(RegIndex, Channel);
1074       unsigned OffsetReg = MI.getOperand(OffsetOpIdx).getReg();
1075       if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
1076         buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address),
1077                       MI.getOperand(ValOpIdx).getReg());
1078       } else {
1079         buildIndirectWrite(MBB, MI, MI.getOperand(ValOpIdx).getReg(),
1080                            calculateIndirectAddress(RegIndex, Channel),
1081                            OffsetReg);
1082       }
1083     } else {
1084       return false;
1085     }
1086 
1087     MBB->erase(MI);
1088     return true;
1089   }
1090   case AMDGPU::R600_EXTRACT_ELT_V2:
1091   case AMDGPU::R600_EXTRACT_ELT_V4:
1092     buildIndirectRead(MI.getParent(), MI, MI.getOperand(0).getReg(),
1093                       RI.getHWRegIndex(MI.getOperand(1).getReg()), //  Address
1094                       MI.getOperand(2).getReg(),
1095                       RI.getHWRegChan(MI.getOperand(1).getReg()));
1096     break;
1097   case AMDGPU::R600_INSERT_ELT_V2:
1098   case AMDGPU::R600_INSERT_ELT_V4:
1099     buildIndirectWrite(MI.getParent(), MI, MI.getOperand(2).getReg(), // Value
1100                        RI.getHWRegIndex(MI.getOperand(1).getReg()),   // Address
1101                        MI.getOperand(3).getReg(),                     // Offset
1102                        RI.getHWRegChan(MI.getOperand(1).getReg()));   // Channel
1103     break;
1104   }
1105   MI.eraseFromParent();
1106   return true;
1107 }
1108 
1109 void  R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,
1110                                              const MachineFunction &MF) const {
1111   const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
1112   const R600FrameLowering *TFL = ST.getFrameLowering();
1113 
1114   unsigned StackWidth = TFL->getStackWidth(MF);
1115   int End = getIndirectIndexEnd(MF);
1116 
1117   if (End == -1)
1118     return;
1119 
1120   for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
1121     unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
1122     Reserved.set(SuperReg);
1123     for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
1124       unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
1125       Reserved.set(Reg);
1126     }
1127   }
1128 }
1129 
1130 const TargetRegisterClass *R600InstrInfo::getIndirectAddrRegClass() const {
1131   return &AMDGPU::R600_TReg32_XRegClass;
1132 }
1133 
1134 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1135                                        MachineBasicBlock::iterator I,
1136                                        unsigned ValueReg, unsigned Address,
1137                                        unsigned OffsetReg) const {
1138   return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0);
1139 }
1140 
1141 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1142                                        MachineBasicBlock::iterator I,
1143                                        unsigned ValueReg, unsigned Address,
1144                                        unsigned OffsetReg,
1145                                        unsigned AddrChan) const {
1146   unsigned AddrReg;
1147   switch (AddrChan) {
1148     default: llvm_unreachable("Invalid Channel");
1149     case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break;
1150     case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break;
1151     case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break;
1152     case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address); break;
1153   }
1154   MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1155                                                AMDGPU::AR_X, OffsetReg);
1156   setImmOperand(*MOVA, AMDGPU::OpName::write, 0);
1157 
1158   MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1159                                       AddrReg, ValueReg)
1160                                       .addReg(AMDGPU::AR_X,
1161                                            RegState::Implicit | RegState::Kill);
1162   setImmOperand(*Mov, AMDGPU::OpName::dst_rel, 1);
1163   return Mov;
1164 }
1165 
1166 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1167                                        MachineBasicBlock::iterator I,
1168                                        unsigned ValueReg, unsigned Address,
1169                                        unsigned OffsetReg) const {
1170   return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0);
1171 }
1172 
1173 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1174                                        MachineBasicBlock::iterator I,
1175                                        unsigned ValueReg, unsigned Address,
1176                                        unsigned OffsetReg,
1177                                        unsigned AddrChan) const {
1178   unsigned AddrReg;
1179   switch (AddrChan) {
1180     default: llvm_unreachable("Invalid Channel");
1181     case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break;
1182     case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break;
1183     case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break;
1184     case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address); break;
1185   }
1186   MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1187                                                        AMDGPU::AR_X,
1188                                                        OffsetReg);
1189   setImmOperand(*MOVA, AMDGPU::OpName::write, 0);
1190   MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1191                                       ValueReg,
1192                                       AddrReg)
1193                                       .addReg(AMDGPU::AR_X,
1194                                            RegState::Implicit | RegState::Kill);
1195   setImmOperand(*Mov, AMDGPU::OpName::src0_rel, 1);
1196 
1197   return Mov;
1198 }
1199 
1200 unsigned R600InstrInfo::getMaxAlusPerClause() const {
1201   return 115;
1202 }
1203 
1204 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
1205                                                   MachineBasicBlock::iterator I,
1206                                                   unsigned Opcode,
1207                                                   unsigned DstReg,
1208                                                   unsigned Src0Reg,
1209                                                   unsigned Src1Reg) const {
1210   MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
1211     DstReg);           // $dst
1212 
1213   if (Src1Reg) {
1214     MIB.addImm(0)     // $update_exec_mask
1215        .addImm(0);    // $update_predicate
1216   }
1217   MIB.addImm(1)        // $write
1218      .addImm(0)        // $omod
1219      .addImm(0)        // $dst_rel
1220      .addImm(0)        // $dst_clamp
1221      .addReg(Src0Reg)  // $src0
1222      .addImm(0)        // $src0_neg
1223      .addImm(0)        // $src0_rel
1224      .addImm(0)        // $src0_abs
1225      .addImm(-1);       // $src0_sel
1226 
1227   if (Src1Reg) {
1228     MIB.addReg(Src1Reg) // $src1
1229        .addImm(0)       // $src1_neg
1230        .addImm(0)       // $src1_rel
1231        .addImm(0)       // $src1_abs
1232        .addImm(-1);      // $src1_sel
1233   }
1234 
1235   //XXX: The r600g finalizer expects this to be 1, once we've moved the
1236   //scheduling to the backend, we can change the default to 0.
1237   MIB.addImm(1)        // $last
1238       .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
1239       .addImm(0)         // $literal
1240       .addImm(0);        // $bank_swizzle
1241 
1242   return MIB;
1243 }
1244 
1245 #define OPERAND_CASE(Label) \
1246   case Label: { \
1247     static const unsigned Ops[] = \
1248     { \
1249       Label##_X, \
1250       Label##_Y, \
1251       Label##_Z, \
1252       Label##_W \
1253     }; \
1254     return Ops[Slot]; \
1255   }
1256 
1257 static unsigned getSlotedOps(unsigned  Op, unsigned Slot) {
1258   switch (Op) {
1259   OPERAND_CASE(AMDGPU::OpName::update_exec_mask)
1260   OPERAND_CASE(AMDGPU::OpName::update_pred)
1261   OPERAND_CASE(AMDGPU::OpName::write)
1262   OPERAND_CASE(AMDGPU::OpName::omod)
1263   OPERAND_CASE(AMDGPU::OpName::dst_rel)
1264   OPERAND_CASE(AMDGPU::OpName::clamp)
1265   OPERAND_CASE(AMDGPU::OpName::src0)
1266   OPERAND_CASE(AMDGPU::OpName::src0_neg)
1267   OPERAND_CASE(AMDGPU::OpName::src0_rel)
1268   OPERAND_CASE(AMDGPU::OpName::src0_abs)
1269   OPERAND_CASE(AMDGPU::OpName::src0_sel)
1270   OPERAND_CASE(AMDGPU::OpName::src1)
1271   OPERAND_CASE(AMDGPU::OpName::src1_neg)
1272   OPERAND_CASE(AMDGPU::OpName::src1_rel)
1273   OPERAND_CASE(AMDGPU::OpName::src1_abs)
1274   OPERAND_CASE(AMDGPU::OpName::src1_sel)
1275   OPERAND_CASE(AMDGPU::OpName::pred_sel)
1276   default:
1277     llvm_unreachable("Wrong Operand");
1278   }
1279 }
1280 
1281 #undef OPERAND_CASE
1282 
1283 MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction(
1284     MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg)
1285     const {
1286   assert (MI->getOpcode() == AMDGPU::DOT_4 && "Not Implemented");
1287   unsigned Opcode;
1288   if (ST.getGeneration() <= R600Subtarget::R700)
1289     Opcode = AMDGPU::DOT4_r600;
1290   else
1291     Opcode = AMDGPU::DOT4_eg;
1292   MachineBasicBlock::iterator I = MI;
1293   MachineOperand &Src0 = MI->getOperand(
1294       getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot)));
1295   MachineOperand &Src1 = MI->getOperand(
1296       getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot)));
1297   MachineInstr *MIB = buildDefaultInstruction(
1298       MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
1299   static const unsigned  Operands[14] = {
1300     AMDGPU::OpName::update_exec_mask,
1301     AMDGPU::OpName::update_pred,
1302     AMDGPU::OpName::write,
1303     AMDGPU::OpName::omod,
1304     AMDGPU::OpName::dst_rel,
1305     AMDGPU::OpName::clamp,
1306     AMDGPU::OpName::src0_neg,
1307     AMDGPU::OpName::src0_rel,
1308     AMDGPU::OpName::src0_abs,
1309     AMDGPU::OpName::src0_sel,
1310     AMDGPU::OpName::src1_neg,
1311     AMDGPU::OpName::src1_rel,
1312     AMDGPU::OpName::src1_abs,
1313     AMDGPU::OpName::src1_sel,
1314   };
1315 
1316   MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
1317       getSlotedOps(AMDGPU::OpName::pred_sel, Slot)));
1318   MIB->getOperand(getOperandIdx(Opcode, AMDGPU::OpName::pred_sel))
1319       .setReg(MO.getReg());
1320 
1321   for (unsigned i = 0; i < 14; i++) {
1322     MachineOperand &MO = MI->getOperand(
1323         getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
1324     assert (MO.isImm());
1325     setImmOperand(*MIB, Operands[i], MO.getImm());
1326   }
1327   MIB->getOperand(20).setImm(0);
1328   return MIB;
1329 }
1330 
1331 MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
1332                                          MachineBasicBlock::iterator I,
1333                                          unsigned DstReg,
1334                                          uint64_t Imm) const {
1335   MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
1336                                                   AMDGPU::ALU_LITERAL_X);
1337   setImmOperand(*MovImm, AMDGPU::OpName::literal, Imm);
1338   return MovImm;
1339 }
1340 
1341 MachineInstr *R600InstrInfo::buildMovInstr(MachineBasicBlock *MBB,
1342                                        MachineBasicBlock::iterator I,
1343                                        unsigned DstReg, unsigned SrcReg) const {
1344   return buildDefaultInstruction(*MBB, I, AMDGPU::MOV, DstReg, SrcReg);
1345 }
1346 
1347 int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const {
1348   return getOperandIdx(MI.getOpcode(), Op);
1349 }
1350 
1351 int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const {
1352   return AMDGPU::getNamedOperandIdx(Opcode, Op);
1353 }
1354 
1355 void R600InstrInfo::setImmOperand(MachineInstr &MI, unsigned Op,
1356                                   int64_t Imm) const {
1357   int Idx = getOperandIdx(MI, Op);
1358   assert(Idx != -1 && "Operand not supported for this instruction.");
1359   assert(MI.getOperand(Idx).isImm());
1360   MI.getOperand(Idx).setImm(Imm);
1361 }
1362 
1363 //===----------------------------------------------------------------------===//
1364 // Instruction flag getters/setters
1365 //===----------------------------------------------------------------------===//
1366 
1367 bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const {
1368   return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
1369 }
1370 
1371 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx,
1372                                          unsigned Flag) const {
1373   unsigned TargetFlags = get(MI.getOpcode()).TSFlags;
1374   int FlagIndex = 0;
1375   if (Flag != 0) {
1376     // If we pass something other than the default value of Flag to this
1377     // function, it means we are want to set a flag on an instruction
1378     // that uses native encoding.
1379     assert(HAS_NATIVE_OPERANDS(TargetFlags));
1380     bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3;
1381     switch (Flag) {
1382     case MO_FLAG_CLAMP:
1383       FlagIndex = getOperandIdx(MI, AMDGPU::OpName::clamp);
1384       break;
1385     case MO_FLAG_MASK:
1386       FlagIndex = getOperandIdx(MI, AMDGPU::OpName::write);
1387       break;
1388     case MO_FLAG_NOT_LAST:
1389     case MO_FLAG_LAST:
1390       FlagIndex = getOperandIdx(MI, AMDGPU::OpName::last);
1391       break;
1392     case MO_FLAG_NEG:
1393       switch (SrcIdx) {
1394       case 0:
1395         FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src0_neg);
1396         break;
1397       case 1:
1398         FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src1_neg);
1399         break;
1400       case 2:
1401         FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src2_neg);
1402         break;
1403       }
1404       break;
1405 
1406     case MO_FLAG_ABS:
1407       assert(!IsOP3 && "Cannot set absolute value modifier for OP3 "
1408                        "instructions.");
1409       (void)IsOP3;
1410       switch (SrcIdx) {
1411       case 0:
1412         FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src0_abs);
1413         break;
1414       case 1:
1415         FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src1_abs);
1416         break;
1417       }
1418       break;
1419 
1420     default:
1421       FlagIndex = -1;
1422       break;
1423     }
1424     assert(FlagIndex != -1 && "Flag not supported for this instruction");
1425   } else {
1426       FlagIndex = GET_FLAG_OPERAND_IDX(TargetFlags);
1427       assert(FlagIndex != 0 &&
1428          "Instruction flags not supported for this instruction");
1429   }
1430 
1431   MachineOperand &FlagOp = MI.getOperand(FlagIndex);
1432   assert(FlagOp.isImm());
1433   return FlagOp;
1434 }
1435 
1436 void R600InstrInfo::addFlag(MachineInstr &MI, unsigned Operand,
1437                             unsigned Flag) const {
1438   unsigned TargetFlags = get(MI.getOpcode()).TSFlags;
1439   if (Flag == 0) {
1440     return;
1441   }
1442   if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1443     MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1444     if (Flag == MO_FLAG_NOT_LAST) {
1445       clearFlag(MI, Operand, MO_FLAG_LAST);
1446     } else if (Flag == MO_FLAG_MASK) {
1447       clearFlag(MI, Operand, Flag);
1448     } else {
1449       FlagOp.setImm(1);
1450     }
1451   } else {
1452       MachineOperand &FlagOp = getFlagOp(MI, Operand);
1453       FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
1454   }
1455 }
1456 
1457 void R600InstrInfo::clearFlag(MachineInstr &MI, unsigned Operand,
1458                               unsigned Flag) const {
1459   unsigned TargetFlags = get(MI.getOpcode()).TSFlags;
1460   if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1461     MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1462     FlagOp.setImm(0);
1463   } else {
1464     MachineOperand &FlagOp = getFlagOp(MI);
1465     unsigned InstFlags = FlagOp.getImm();
1466     InstFlags &= ~(Flag << (NUM_MO_FLAGS * Operand));
1467     FlagOp.setImm(InstFlags);
1468   }
1469 }
1470 
1471 bool R600InstrInfo::isRegisterStore(const MachineInstr &MI) const {
1472   return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE;
1473 }
1474 
1475 bool R600InstrInfo::isRegisterLoad(const MachineInstr &MI) const {
1476   return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;
1477 }
1478