1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief R600 Implementation of TargetInstrInfo.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "R600InstrInfo.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUSubtarget.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "R600Defines.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 
26 using namespace llvm;
27 
28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "AMDGPUGenDFAPacketizer.inc"
30 
31 R600InstrInfo::R600InstrInfo(const AMDGPUSubtarget &st)
32     : AMDGPUInstrInfo(st), RI() {}
33 
34 const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const {
35   return RI;
36 }
37 
38 bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
39   return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
40 }
41 
42 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
43   return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
44 }
45 
46 void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
47                                 MachineBasicBlock::iterator MI,
48                                 const DebugLoc &DL, unsigned DestReg,
49                                 unsigned SrcReg, bool KillSrc) const {
50   unsigned VectorComponents = 0;
51   if ((AMDGPU::R600_Reg128RegClass.contains(DestReg) ||
52       AMDGPU::R600_Reg128VerticalRegClass.contains(DestReg)) &&
53       (AMDGPU::R600_Reg128RegClass.contains(SrcReg) ||
54        AMDGPU::R600_Reg128VerticalRegClass.contains(SrcReg))) {
55     VectorComponents = 4;
56   } else if((AMDGPU::R600_Reg64RegClass.contains(DestReg) ||
57             AMDGPU::R600_Reg64VerticalRegClass.contains(DestReg)) &&
58             (AMDGPU::R600_Reg64RegClass.contains(SrcReg) ||
59              AMDGPU::R600_Reg64VerticalRegClass.contains(SrcReg))) {
60     VectorComponents = 2;
61   }
62 
63   if (VectorComponents > 0) {
64     for (unsigned I = 0; I < VectorComponents; I++) {
65       unsigned SubRegIndex = RI.getSubRegFromChannel(I);
66       buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
67                               RI.getSubReg(DestReg, SubRegIndex),
68                               RI.getSubReg(SrcReg, SubRegIndex))
69                               .addReg(DestReg,
70                                       RegState::Define | RegState::Implicit);
71     }
72   } else {
73     MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
74                                                   DestReg, SrcReg);
75     NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0))
76                                     .setIsKill(KillSrc);
77   }
78 }
79 
80 /// \returns true if \p MBBI can be moved into a new basic.
81 bool R600InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
82                                        MachineBasicBlock::iterator MBBI) const {
83   for (MachineInstr::const_mop_iterator I = MBBI->operands_begin(),
84                                         E = MBBI->operands_end(); I != E; ++I) {
85     if (I->isReg() && !TargetRegisterInfo::isVirtualRegister(I->getReg()) &&
86         I->isUse() && RI.isPhysRegLiveAcrossClauses(I->getReg()))
87       return false;
88   }
89   return true;
90 }
91 
92 bool R600InstrInfo::isMov(unsigned Opcode) const {
93 
94 
95   switch(Opcode) {
96   default: return false;
97   case AMDGPU::MOV:
98   case AMDGPU::MOV_IMM_F32:
99   case AMDGPU::MOV_IMM_I32:
100     return true;
101   }
102 }
103 
104 // Some instructions act as place holders to emulate operations that the GPU
105 // hardware does automatically. This function can be used to check if
106 // an opcode falls into this category.
107 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {
108   switch (Opcode) {
109   default: return false;
110   case AMDGPU::RETURN:
111     return true;
112   }
113 }
114 
115 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
116   return false;
117 }
118 
119 bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
120   switch(Opcode) {
121     default: return false;
122     case AMDGPU::CUBE_r600_pseudo:
123     case AMDGPU::CUBE_r600_real:
124     case AMDGPU::CUBE_eg_pseudo:
125     case AMDGPU::CUBE_eg_real:
126       return true;
127   }
128 }
129 
130 bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
131   unsigned TargetFlags = get(Opcode).TSFlags;
132 
133   return (TargetFlags & R600_InstFlag::ALU_INST);
134 }
135 
136 bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const {
137   unsigned TargetFlags = get(Opcode).TSFlags;
138 
139   return ((TargetFlags & R600_InstFlag::OP1) |
140           (TargetFlags & R600_InstFlag::OP2) |
141           (TargetFlags & R600_InstFlag::OP3));
142 }
143 
144 bool R600InstrInfo::isLDSInstr(unsigned Opcode) const {
145   unsigned TargetFlags = get(Opcode).TSFlags;
146 
147   return ((TargetFlags & R600_InstFlag::LDS_1A) |
148           (TargetFlags & R600_InstFlag::LDS_1A1D) |
149           (TargetFlags & R600_InstFlag::LDS_1A2D));
150 }
151 
152 bool R600InstrInfo::isLDSNoRetInstr(unsigned Opcode) const {
153   return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) == -1;
154 }
155 
156 bool R600InstrInfo::isLDSRetInstr(unsigned Opcode) const {
157   return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) != -1;
158 }
159 
160 bool R600InstrInfo::canBeConsideredALU(const MachineInstr *MI) const {
161   if (isALUInstr(MI->getOpcode()))
162     return true;
163   if (isVector(*MI) || isCubeOp(MI->getOpcode()))
164     return true;
165   switch (MI->getOpcode()) {
166   case AMDGPU::PRED_X:
167   case AMDGPU::INTERP_PAIR_XY:
168   case AMDGPU::INTERP_PAIR_ZW:
169   case AMDGPU::INTERP_VEC_LOAD:
170   case AMDGPU::COPY:
171   case AMDGPU::DOT_4:
172     return true;
173   default:
174     return false;
175   }
176 }
177 
178 bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
179   if (ST.hasCaymanISA())
180     return false;
181   return (get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU);
182 }
183 
184 bool R600InstrInfo::isTransOnly(const MachineInstr *MI) const {
185   return isTransOnly(MI->getOpcode());
186 }
187 
188 bool R600InstrInfo::isVectorOnly(unsigned Opcode) const {
189   return (get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU);
190 }
191 
192 bool R600InstrInfo::isVectorOnly(const MachineInstr *MI) const {
193   return isVectorOnly(MI->getOpcode());
194 }
195 
196 bool R600InstrInfo::isExport(unsigned Opcode) const {
197   return (get(Opcode).TSFlags & R600_InstFlag::IS_EXPORT);
198 }
199 
200 bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
201   return ST.hasVertexCache() && IS_VTX(get(Opcode));
202 }
203 
204 bool R600InstrInfo::usesVertexCache(const MachineInstr *MI) const {
205   const MachineFunction *MF = MI->getParent()->getParent();
206   return !AMDGPU::isCompute(MF->getFunction()->getCallingConv()) &&
207     usesVertexCache(MI->getOpcode());
208 }
209 
210 bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {
211   return (!ST.hasVertexCache() && IS_VTX(get(Opcode))) || IS_TEX(get(Opcode));
212 }
213 
214 bool R600InstrInfo::usesTextureCache(const MachineInstr *MI) const {
215   const MachineFunction *MF = MI->getParent()->getParent();
216   return (AMDGPU::isCompute(MF->getFunction()->getCallingConv()) &&
217           usesVertexCache(MI->getOpcode())) ||
218     usesTextureCache(MI->getOpcode());
219 }
220 
221 bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const {
222   switch (Opcode) {
223   case AMDGPU::KILLGT:
224   case AMDGPU::GROUP_BARRIER:
225     return true;
226   default:
227     return false;
228   }
229 }
230 
231 bool R600InstrInfo::usesAddressRegister(MachineInstr *MI) const {
232   return  MI->findRegisterUseOperandIdx(AMDGPU::AR_X) != -1;
233 }
234 
235 bool R600InstrInfo::definesAddressRegister(MachineInstr *MI) const {
236   return MI->findRegisterDefOperandIdx(AMDGPU::AR_X) != -1;
237 }
238 
239 bool R600InstrInfo::readsLDSSrcReg(const MachineInstr *MI) const {
240   if (!isALUInstr(MI->getOpcode())) {
241     return false;
242   }
243   for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
244                                         E = MI->operands_end(); I != E; ++I) {
245     if (!I->isReg() || !I->isUse() ||
246         TargetRegisterInfo::isVirtualRegister(I->getReg()))
247       continue;
248 
249     if (AMDGPU::R600_LDS_SRC_REGRegClass.contains(I->getReg()))
250       return true;
251   }
252   return false;
253 }
254 
255 int R600InstrInfo::getSrcIdx(unsigned Opcode, unsigned SrcNum) const {
256   static const unsigned OpTable[] = {
257     AMDGPU::OpName::src0,
258     AMDGPU::OpName::src1,
259     AMDGPU::OpName::src2
260   };
261 
262   assert (SrcNum < 3);
263   return getOperandIdx(Opcode, OpTable[SrcNum]);
264 }
265 
266 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const {
267   static const unsigned SrcSelTable[][2] = {
268     {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
269     {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
270     {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
271     {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
272     {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
273     {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
274     {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
275     {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
276     {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
277     {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
278     {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W}
279   };
280 
281   for (const auto &Row : SrcSelTable) {
282     if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) {
283       return getOperandIdx(Opcode, Row[1]);
284     }
285   }
286   return -1;
287 }
288 
289 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
290 R600InstrInfo::getSrcs(MachineInstr *MI) const {
291   SmallVector<std::pair<MachineOperand *, int64_t>, 3> Result;
292 
293   if (MI->getOpcode() == AMDGPU::DOT_4) {
294     static const unsigned OpTable[8][2] = {
295       {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
296       {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
297       {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
298       {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
299       {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
300       {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
301       {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
302       {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W},
303     };
304 
305     for (unsigned j = 0; j < 8; j++) {
306       MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
307                                                         OpTable[j][0]));
308       unsigned Reg = MO.getReg();
309       if (Reg == AMDGPU::ALU_CONST) {
310         MachineOperand &Sel = MI->getOperand(getOperandIdx(MI->getOpcode(),
311                                                     OpTable[j][1]));
312         Result.push_back(std::make_pair(&MO, Sel.getImm()));
313         continue;
314       }
315 
316     }
317     return Result;
318   }
319 
320   static const unsigned OpTable[3][2] = {
321     {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
322     {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
323     {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
324   };
325 
326   for (unsigned j = 0; j < 3; j++) {
327     int SrcIdx = getOperandIdx(MI->getOpcode(), OpTable[j][0]);
328     if (SrcIdx < 0)
329       break;
330     MachineOperand &MO = MI->getOperand(SrcIdx);
331     unsigned Reg = MO.getReg();
332     if (Reg == AMDGPU::ALU_CONST) {
333       MachineOperand &Sel = MI->getOperand(
334           getOperandIdx(MI->getOpcode(), OpTable[j][1]));
335       Result.push_back(std::make_pair(&MO, Sel.getImm()));
336       continue;
337     }
338     if (Reg == AMDGPU::ALU_LITERAL_X) {
339       MachineOperand &Operand = MI->getOperand(
340           getOperandIdx(MI->getOpcode(), AMDGPU::OpName::literal));
341       if (Operand.isImm()) {
342         Result.push_back(std::make_pair(&MO, Operand.getImm()));
343         continue;
344       }
345       assert(Operand.isGlobal());
346     }
347     Result.push_back(std::make_pair(&MO, 0));
348   }
349   return Result;
350 }
351 
352 std::vector<std::pair<int, unsigned> >
353 R600InstrInfo::ExtractSrcs(MachineInstr *MI,
354                            const DenseMap<unsigned, unsigned> &PV,
355                            unsigned &ConstCount) const {
356   ConstCount = 0;
357   ArrayRef<std::pair<MachineOperand *, int64_t>> Srcs = getSrcs(MI);
358   const std::pair<int, unsigned> DummyPair(-1, 0);
359   std::vector<std::pair<int, unsigned> > Result;
360   unsigned i = 0;
361   for (unsigned n = Srcs.size(); i < n; ++i) {
362     unsigned Reg = Srcs[i].first->getReg();
363     int Index = RI.getEncodingValue(Reg) & 0xff;
364     if (Reg == AMDGPU::OQAP) {
365       Result.push_back(std::make_pair(Index, 0U));
366     }
367     if (PV.find(Reg) != PV.end()) {
368       // 255 is used to tells its a PS/PV reg
369       Result.push_back(std::make_pair(255, 0U));
370       continue;
371     }
372     if (Index > 127) {
373       ConstCount++;
374       Result.push_back(DummyPair);
375       continue;
376     }
377     unsigned Chan = RI.getHWRegChan(Reg);
378     Result.push_back(std::make_pair(Index, Chan));
379   }
380   for (; i < 3; ++i)
381     Result.push_back(DummyPair);
382   return Result;
383 }
384 
385 static std::vector<std::pair<int, unsigned> >
386 Swizzle(std::vector<std::pair<int, unsigned> > Src,
387         R600InstrInfo::BankSwizzle Swz) {
388   if (Src[0] == Src[1])
389     Src[1].first = -1;
390   switch (Swz) {
391   case R600InstrInfo::ALU_VEC_012_SCL_210:
392     break;
393   case R600InstrInfo::ALU_VEC_021_SCL_122:
394     std::swap(Src[1], Src[2]);
395     break;
396   case R600InstrInfo::ALU_VEC_102_SCL_221:
397     std::swap(Src[0], Src[1]);
398     break;
399   case R600InstrInfo::ALU_VEC_120_SCL_212:
400     std::swap(Src[0], Src[1]);
401     std::swap(Src[0], Src[2]);
402     break;
403   case R600InstrInfo::ALU_VEC_201:
404     std::swap(Src[0], Src[2]);
405     std::swap(Src[0], Src[1]);
406     break;
407   case R600InstrInfo::ALU_VEC_210:
408     std::swap(Src[0], Src[2]);
409     break;
410   }
411   return Src;
412 }
413 
414 static unsigned
415 getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) {
416   switch (Swz) {
417   case R600InstrInfo::ALU_VEC_012_SCL_210: {
418     unsigned Cycles[3] = { 2, 1, 0};
419     return Cycles[Op];
420   }
421   case R600InstrInfo::ALU_VEC_021_SCL_122: {
422     unsigned Cycles[3] = { 1, 2, 2};
423     return Cycles[Op];
424   }
425   case R600InstrInfo::ALU_VEC_120_SCL_212: {
426     unsigned Cycles[3] = { 2, 1, 2};
427     return Cycles[Op];
428   }
429   case R600InstrInfo::ALU_VEC_102_SCL_221: {
430     unsigned Cycles[3] = { 2, 2, 1};
431     return Cycles[Op];
432   }
433   default:
434     llvm_unreachable("Wrong Swizzle for Trans Slot");
435     return 0;
436   }
437 }
438 
439 /// returns how many MIs (whose inputs are represented by IGSrcs) can be packed
440 /// in the same Instruction Group while meeting read port limitations given a
441 /// Swz swizzle sequence.
442 unsigned  R600InstrInfo::isLegalUpTo(
443     const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
444     const std::vector<R600InstrInfo::BankSwizzle> &Swz,
445     const std::vector<std::pair<int, unsigned> > &TransSrcs,
446     R600InstrInfo::BankSwizzle TransSwz) const {
447   int Vector[4][3];
448   memset(Vector, -1, sizeof(Vector));
449   for (unsigned i = 0, e = IGSrcs.size(); i < e; i++) {
450     const std::vector<std::pair<int, unsigned> > &Srcs =
451         Swizzle(IGSrcs[i], Swz[i]);
452     for (unsigned j = 0; j < 3; j++) {
453       const std::pair<int, unsigned> &Src = Srcs[j];
454       if (Src.first < 0 || Src.first == 255)
455         continue;
456       if (Src.first == GET_REG_INDEX(RI.getEncodingValue(AMDGPU::OQAP))) {
457         if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 &&
458             Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) {
459             // The value from output queue A (denoted by register OQAP) can
460             // only be fetched during the first cycle.
461             return false;
462         }
463         // OQAP does not count towards the normal read port restrictions
464         continue;
465       }
466       if (Vector[Src.second][j] < 0)
467         Vector[Src.second][j] = Src.first;
468       if (Vector[Src.second][j] != Src.first)
469         return i;
470     }
471   }
472   // Now check Trans Alu
473   for (unsigned i = 0, e = TransSrcs.size(); i < e; ++i) {
474     const std::pair<int, unsigned> &Src = TransSrcs[i];
475     unsigned Cycle = getTransSwizzle(TransSwz, i);
476     if (Src.first < 0)
477       continue;
478     if (Src.first == 255)
479       continue;
480     if (Vector[Src.second][Cycle] < 0)
481       Vector[Src.second][Cycle] = Src.first;
482     if (Vector[Src.second][Cycle] != Src.first)
483       return IGSrcs.size() - 1;
484   }
485   return IGSrcs.size();
486 }
487 
488 /// Given a swizzle sequence SwzCandidate and an index Idx, returns the next
489 /// (in lexicographic term) swizzle sequence assuming that all swizzles after
490 /// Idx can be skipped
491 static bool
492 NextPossibleSolution(
493     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
494     unsigned Idx) {
495   assert(Idx < SwzCandidate.size());
496   int ResetIdx = Idx;
497   while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210)
498     ResetIdx --;
499   for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) {
500     SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210;
501   }
502   if (ResetIdx == -1)
503     return false;
504   int NextSwizzle = SwzCandidate[ResetIdx] + 1;
505   SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle;
506   return true;
507 }
508 
509 /// Enumerate all possible Swizzle sequence to find one that can meet all
510 /// read port requirements.
511 bool R600InstrInfo::FindSwizzleForVectorSlot(
512     const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
513     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
514     const std::vector<std::pair<int, unsigned> > &TransSrcs,
515     R600InstrInfo::BankSwizzle TransSwz) const {
516   unsigned ValidUpTo = 0;
517   do {
518     ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz);
519     if (ValidUpTo == IGSrcs.size())
520       return true;
521   } while (NextPossibleSolution(SwzCandidate, ValidUpTo));
522   return false;
523 }
524 
525 /// Instructions in Trans slot can't read gpr at cycle 0 if they also read
526 /// a const, and can't read a gpr at cycle 1 if they read 2 const.
527 static bool
528 isConstCompatible(R600InstrInfo::BankSwizzle TransSwz,
529                   const std::vector<std::pair<int, unsigned> > &TransOps,
530                   unsigned ConstCount) {
531   // TransALU can't read 3 constants
532   if (ConstCount > 2)
533     return false;
534   for (unsigned i = 0, e = TransOps.size(); i < e; ++i) {
535     const std::pair<int, unsigned> &Src = TransOps[i];
536     unsigned Cycle = getTransSwizzle(TransSwz, i);
537     if (Src.first < 0)
538       continue;
539     if (ConstCount > 0 && Cycle == 0)
540       return false;
541     if (ConstCount > 1 && Cycle == 1)
542       return false;
543   }
544   return true;
545 }
546 
547 bool
548 R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
549                                        const DenseMap<unsigned, unsigned> &PV,
550                                        std::vector<BankSwizzle> &ValidSwizzle,
551                                        bool isLastAluTrans)
552     const {
553   //Todo : support shared src0 - src1 operand
554 
555   std::vector<std::vector<std::pair<int, unsigned> > > IGSrcs;
556   ValidSwizzle.clear();
557   unsigned ConstCount;
558   BankSwizzle TransBS = ALU_VEC_012_SCL_210;
559   for (unsigned i = 0, e = IG.size(); i < e; ++i) {
560     IGSrcs.push_back(ExtractSrcs(IG[i], PV, ConstCount));
561     unsigned Op = getOperandIdx(IG[i]->getOpcode(),
562         AMDGPU::OpName::bank_swizzle);
563     ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle)
564         IG[i]->getOperand(Op).getImm());
565   }
566   std::vector<std::pair<int, unsigned> > TransOps;
567   if (!isLastAluTrans)
568     return FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps, TransBS);
569 
570   TransOps = std::move(IGSrcs.back());
571   IGSrcs.pop_back();
572   ValidSwizzle.pop_back();
573 
574   static const R600InstrInfo::BankSwizzle TransSwz[] = {
575     ALU_VEC_012_SCL_210,
576     ALU_VEC_021_SCL_122,
577     ALU_VEC_120_SCL_212,
578     ALU_VEC_102_SCL_221
579   };
580   for (unsigned i = 0; i < 4; i++) {
581     TransBS = TransSwz[i];
582     if (!isConstCompatible(TransBS, TransOps, ConstCount))
583       continue;
584     bool Result = FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps,
585         TransBS);
586     if (Result) {
587       ValidSwizzle.push_back(TransBS);
588       return true;
589     }
590   }
591 
592   return false;
593 }
594 
595 
596 bool
597 R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)
598     const {
599   assert (Consts.size() <= 12 && "Too many operands in instructions group");
600   unsigned Pair1 = 0, Pair2 = 0;
601   for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
602     unsigned ReadConstHalf = Consts[i] & 2;
603     unsigned ReadConstIndex = Consts[i] & (~3);
604     unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
605     if (!Pair1) {
606       Pair1 = ReadHalfConst;
607       continue;
608     }
609     if (Pair1 == ReadHalfConst)
610       continue;
611     if (!Pair2) {
612       Pair2 = ReadHalfConst;
613       continue;
614     }
615     if (Pair2 != ReadHalfConst)
616       return false;
617   }
618   return true;
619 }
620 
621 bool
622 R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs)
623     const {
624   std::vector<unsigned> Consts;
625   SmallSet<int64_t, 4> Literals;
626   for (unsigned i = 0, n = MIs.size(); i < n; i++) {
627     MachineInstr *MI = MIs[i];
628     if (!isALUInstr(MI->getOpcode()))
629       continue;
630 
631     ArrayRef<std::pair<MachineOperand *, int64_t>> Srcs = getSrcs(MI);
632 
633     for (const auto &Src:Srcs) {
634       if (Src.first->getReg() == AMDGPU::ALU_LITERAL_X)
635         Literals.insert(Src.second);
636       if (Literals.size() > 4)
637         return false;
638       if (Src.first->getReg() == AMDGPU::ALU_CONST)
639         Consts.push_back(Src.second);
640       if (AMDGPU::R600_KC0RegClass.contains(Src.first->getReg()) ||
641           AMDGPU::R600_KC1RegClass.contains(Src.first->getReg())) {
642         unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
643         unsigned Chan = RI.getHWRegChan(Src.first->getReg());
644         Consts.push_back((Index << 2) | Chan);
645       }
646     }
647   }
648   return fitsConstReadLimitations(Consts);
649 }
650 
651 DFAPacketizer *
652 R600InstrInfo::CreateTargetScheduleState(const TargetSubtargetInfo &STI) const {
653   const InstrItineraryData *II = STI.getInstrItineraryData();
654   return static_cast<const AMDGPUSubtarget &>(STI).createDFAPacketizer(II);
655 }
656 
657 static bool
658 isPredicateSetter(unsigned Opcode) {
659   switch (Opcode) {
660   case AMDGPU::PRED_X:
661     return true;
662   default:
663     return false;
664   }
665 }
666 
667 static MachineInstr *
668 findFirstPredicateSetterFrom(MachineBasicBlock &MBB,
669                              MachineBasicBlock::iterator I) {
670   while (I != MBB.begin()) {
671     --I;
672     MachineInstr *MI = I;
673     if (isPredicateSetter(MI->getOpcode()))
674       return MI;
675   }
676 
677   return nullptr;
678 }
679 
680 static
681 bool isJump(unsigned Opcode) {
682   return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND;
683 }
684 
685 static bool isBranch(unsigned Opcode) {
686   return Opcode == AMDGPU::BRANCH || Opcode == AMDGPU::BRANCH_COND_i32 ||
687       Opcode == AMDGPU::BRANCH_COND_f32;
688 }
689 
690 bool
691 R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
692                              MachineBasicBlock *&TBB,
693                              MachineBasicBlock *&FBB,
694                              SmallVectorImpl<MachineOperand> &Cond,
695                              bool AllowModify) const {
696   // Most of the following comes from the ARM implementation of AnalyzeBranch
697 
698   // If the block has no terminators, it just falls into the block after it.
699   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
700   if (I == MBB.end())
701     return false;
702 
703   // AMDGPU::BRANCH* instructions are only available after isel and are not
704   // handled
705   if (isBranch(I->getOpcode()))
706     return true;
707   if (!isJump(static_cast<MachineInstr *>(I)->getOpcode())) {
708     return false;
709   }
710 
711   // Remove successive JUMP
712   while (I != MBB.begin() && std::prev(I)->getOpcode() == AMDGPU::JUMP) {
713       MachineBasicBlock::iterator PriorI = std::prev(I);
714       if (AllowModify)
715         I->removeFromParent();
716       I = PriorI;
717   }
718   MachineInstr *LastInst = I;
719 
720   // If there is only one terminator instruction, process it.
721   unsigned LastOpc = LastInst->getOpcode();
722   if (I == MBB.begin() ||
723           !isJump(static_cast<MachineInstr *>(--I)->getOpcode())) {
724     if (LastOpc == AMDGPU::JUMP) {
725       TBB = LastInst->getOperand(0).getMBB();
726       return false;
727     } else if (LastOpc == AMDGPU::JUMP_COND) {
728       MachineInstr *predSet = I;
729       while (!isPredicateSetter(predSet->getOpcode())) {
730         predSet = --I;
731       }
732       TBB = LastInst->getOperand(0).getMBB();
733       Cond.push_back(predSet->getOperand(1));
734       Cond.push_back(predSet->getOperand(2));
735       Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
736       return false;
737     }
738     return true;  // Can't handle indirect branch.
739   }
740 
741   // Get the instruction before it if it is a terminator.
742   MachineInstr *SecondLastInst = I;
743   unsigned SecondLastOpc = SecondLastInst->getOpcode();
744 
745   // If the block ends with a B and a Bcc, handle it.
746   if (SecondLastOpc == AMDGPU::JUMP_COND && LastOpc == AMDGPU::JUMP) {
747     MachineInstr *predSet = --I;
748     while (!isPredicateSetter(predSet->getOpcode())) {
749       predSet = --I;
750     }
751     TBB = SecondLastInst->getOperand(0).getMBB();
752     FBB = LastInst->getOperand(0).getMBB();
753     Cond.push_back(predSet->getOperand(1));
754     Cond.push_back(predSet->getOperand(2));
755     Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
756     return false;
757   }
758 
759   // Otherwise, can't handle this.
760   return true;
761 }
762 
763 static
764 MachineBasicBlock::iterator FindLastAluClause(MachineBasicBlock &MBB) {
765   for (MachineBasicBlock::reverse_iterator It = MBB.rbegin(), E = MBB.rend();
766       It != E; ++It) {
767     if (It->getOpcode() == AMDGPU::CF_ALU ||
768         It->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
769       return std::prev(It.base());
770   }
771   return MBB.end();
772 }
773 
774 unsigned R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
775                                      MachineBasicBlock *TBB,
776                                      MachineBasicBlock *FBB,
777                                      ArrayRef<MachineOperand> Cond,
778                                      const DebugLoc &DL) const {
779   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
780 
781   if (!FBB) {
782     if (Cond.empty()) {
783       BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB);
784       return 1;
785     } else {
786       MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
787       assert(PredSet && "No previous predicate !");
788       addFlag(PredSet, 0, MO_FLAG_PUSH);
789       PredSet->getOperand(2).setImm(Cond[1].getImm());
790 
791       BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
792              .addMBB(TBB)
793              .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
794       MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
795       if (CfAlu == MBB.end())
796         return 1;
797       assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
798       CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
799       return 1;
800     }
801   } else {
802     MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
803     assert(PredSet && "No previous predicate !");
804     addFlag(PredSet, 0, MO_FLAG_PUSH);
805     PredSet->getOperand(2).setImm(Cond[1].getImm());
806     BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
807             .addMBB(TBB)
808             .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
809     BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB);
810     MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
811     if (CfAlu == MBB.end())
812       return 2;
813     assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
814     CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
815     return 2;
816   }
817 }
818 
819 unsigned
820 R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
821 
822   // Note : we leave PRED* instructions there.
823   // They may be needed when predicating instructions.
824 
825   MachineBasicBlock::iterator I = MBB.end();
826 
827   if (I == MBB.begin()) {
828     return 0;
829   }
830   --I;
831   switch (I->getOpcode()) {
832   default:
833     return 0;
834   case AMDGPU::JUMP_COND: {
835     MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
836     clearFlag(predSet, 0, MO_FLAG_PUSH);
837     I->eraseFromParent();
838     MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
839     if (CfAlu == MBB.end())
840       break;
841     assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
842     CfAlu->setDesc(get(AMDGPU::CF_ALU));
843     break;
844   }
845   case AMDGPU::JUMP:
846     I->eraseFromParent();
847     break;
848   }
849   I = MBB.end();
850 
851   if (I == MBB.begin()) {
852     return 1;
853   }
854   --I;
855   switch (I->getOpcode()) {
856     // FIXME: only one case??
857   default:
858     return 1;
859   case AMDGPU::JUMP_COND: {
860     MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
861     clearFlag(predSet, 0, MO_FLAG_PUSH);
862     I->eraseFromParent();
863     MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
864     if (CfAlu == MBB.end())
865       break;
866     assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
867     CfAlu->setDesc(get(AMDGPU::CF_ALU));
868     break;
869   }
870   case AMDGPU::JUMP:
871     I->eraseFromParent();
872     break;
873   }
874   return 2;
875 }
876 
877 bool R600InstrInfo::isPredicated(const MachineInstr &MI) const {
878   int idx = MI.findFirstPredOperandIdx();
879   if (idx < 0)
880     return false;
881 
882   unsigned Reg = MI.getOperand(idx).getReg();
883   switch (Reg) {
884   default: return false;
885   case AMDGPU::PRED_SEL_ONE:
886   case AMDGPU::PRED_SEL_ZERO:
887   case AMDGPU::PREDICATE_BIT:
888     return true;
889   }
890 }
891 
892 bool R600InstrInfo::isPredicable(MachineInstr &MI) const {
893   // XXX: KILL* instructions can be predicated, but they must be the last
894   // instruction in a clause, so this means any instructions after them cannot
895   // be predicated.  Until we have proper support for instruction clauses in the
896   // backend, we will mark KILL* instructions as unpredicable.
897 
898   if (MI.getOpcode() == AMDGPU::KILLGT) {
899     return false;
900   } else if (MI.getOpcode() == AMDGPU::CF_ALU) {
901     // If the clause start in the middle of MBB then the MBB has more
902     // than a single clause, unable to predicate several clauses.
903     if (MI.getParent()->begin() != MachineBasicBlock::iterator(MI))
904       return false;
905     // TODO: We don't support KC merging atm
906     return MI.getOperand(3).getImm() == 0 && MI.getOperand(4).getImm() == 0;
907   } else if (isVector(MI)) {
908     return false;
909   } else {
910     return AMDGPUInstrInfo::isPredicable(MI);
911   }
912 }
913 
914 
915 bool
916 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
917                                    unsigned NumCyles,
918                                    unsigned ExtraPredCycles,
919                                    BranchProbability Probability) const{
920   return true;
921 }
922 
923 bool
924 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
925                                    unsigned NumTCycles,
926                                    unsigned ExtraTCycles,
927                                    MachineBasicBlock &FMBB,
928                                    unsigned NumFCycles,
929                                    unsigned ExtraFCycles,
930                                    BranchProbability Probability) const {
931   return true;
932 }
933 
934 bool
935 R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
936                                          unsigned NumCyles,
937                                          BranchProbability Probability)
938                                          const {
939   return true;
940 }
941 
942 bool
943 R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
944                                          MachineBasicBlock &FMBB) const {
945   return false;
946 }
947 
948 
949 bool
950 R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
951   MachineOperand &MO = Cond[1];
952   switch (MO.getImm()) {
953   case OPCODE_IS_ZERO_INT:
954     MO.setImm(OPCODE_IS_NOT_ZERO_INT);
955     break;
956   case OPCODE_IS_NOT_ZERO_INT:
957     MO.setImm(OPCODE_IS_ZERO_INT);
958     break;
959   case OPCODE_IS_ZERO:
960     MO.setImm(OPCODE_IS_NOT_ZERO);
961     break;
962   case OPCODE_IS_NOT_ZERO:
963     MO.setImm(OPCODE_IS_ZERO);
964     break;
965   default:
966     return true;
967   }
968 
969   MachineOperand &MO2 = Cond[2];
970   switch (MO2.getReg()) {
971   case AMDGPU::PRED_SEL_ZERO:
972     MO2.setReg(AMDGPU::PRED_SEL_ONE);
973     break;
974   case AMDGPU::PRED_SEL_ONE:
975     MO2.setReg(AMDGPU::PRED_SEL_ZERO);
976     break;
977   default:
978     return true;
979   }
980   return false;
981 }
982 
983 bool R600InstrInfo::DefinesPredicate(MachineInstr &MI,
984                                      std::vector<MachineOperand> &Pred) const {
985   return isPredicateSetter(MI.getOpcode());
986 }
987 
988 
989 bool
990 R600InstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
991                                  ArrayRef<MachineOperand> Pred2) const {
992   return false;
993 }
994 
995 bool R600InstrInfo::PredicateInstruction(MachineInstr &MI,
996                                          ArrayRef<MachineOperand> Pred) const {
997   int PIdx = MI.findFirstPredOperandIdx();
998 
999   if (MI.getOpcode() == AMDGPU::CF_ALU) {
1000     MI.getOperand(8).setImm(0);
1001     return true;
1002   }
1003 
1004   if (MI.getOpcode() == AMDGPU::DOT_4) {
1005     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_X))
1006         .setReg(Pred[2].getReg());
1007     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_Y))
1008         .setReg(Pred[2].getReg());
1009     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_Z))
1010         .setReg(Pred[2].getReg());
1011     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_W))
1012         .setReg(Pred[2].getReg());
1013     MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
1014     MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
1015     return true;
1016   }
1017 
1018   if (PIdx != -1) {
1019     MachineOperand &PMO = MI.getOperand(PIdx);
1020     PMO.setReg(Pred[2].getReg());
1021     MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
1022     MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
1023     return true;
1024   }
1025 
1026   return false;
1027 }
1028 
1029 unsigned int R600InstrInfo::getPredicationCost(const MachineInstr &) const {
1030   return 2;
1031 }
1032 
1033 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1034                                             const MachineInstr *MI,
1035                                             unsigned *PredCost) const {
1036   if (PredCost)
1037     *PredCost = 2;
1038   return 2;
1039 }
1040 
1041 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex,
1042                                                    unsigned Channel) const {
1043   assert(Channel == 0);
1044   return RegIndex;
1045 }
1046 
1047 bool R600InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
1048 
1049   switch(MI->getOpcode()) {
1050   default: {
1051     MachineBasicBlock *MBB = MI->getParent();
1052     int OffsetOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1053                                                  AMDGPU::OpName::addr);
1054      // addr is a custom operand with multiple MI operands, and only the
1055      // first MI operand is given a name.
1056     int RegOpIdx = OffsetOpIdx + 1;
1057     int ChanOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1058                                                AMDGPU::OpName::chan);
1059     if (isRegisterLoad(*MI)) {
1060       int DstOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1061                                                 AMDGPU::OpName::dst);
1062       unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
1063       unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
1064       unsigned Address = calculateIndirectAddress(RegIndex, Channel);
1065       unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
1066       if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
1067         buildMovInstr(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
1068                       getIndirectAddrRegClass()->getRegister(Address));
1069       } else {
1070         buildIndirectRead(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
1071                           Address, OffsetReg);
1072       }
1073     } else if (isRegisterStore(*MI)) {
1074       int ValOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1075                                                 AMDGPU::OpName::val);
1076       unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
1077       unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
1078       unsigned Address = calculateIndirectAddress(RegIndex, Channel);
1079       unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
1080       if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
1081         buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address),
1082                       MI->getOperand(ValOpIdx).getReg());
1083       } else {
1084         buildIndirectWrite(MBB, MI, MI->getOperand(ValOpIdx).getReg(),
1085                            calculateIndirectAddress(RegIndex, Channel),
1086                            OffsetReg);
1087       }
1088     } else {
1089       return false;
1090     }
1091 
1092     MBB->erase(MI);
1093     return true;
1094   }
1095   case AMDGPU::R600_EXTRACT_ELT_V2:
1096   case AMDGPU::R600_EXTRACT_ELT_V4:
1097     buildIndirectRead(MI->getParent(), MI, MI->getOperand(0).getReg(),
1098                       RI.getHWRegIndex(MI->getOperand(1).getReg()), //  Address
1099                       MI->getOperand(2).getReg(),
1100                       RI.getHWRegChan(MI->getOperand(1).getReg()));
1101     break;
1102   case AMDGPU::R600_INSERT_ELT_V2:
1103   case AMDGPU::R600_INSERT_ELT_V4:
1104     buildIndirectWrite(MI->getParent(), MI, MI->getOperand(2).getReg(), // Value
1105                        RI.getHWRegIndex(MI->getOperand(1).getReg()),  // Address
1106                        MI->getOperand(3).getReg(),                    // Offset
1107                        RI.getHWRegChan(MI->getOperand(1).getReg()));  // Channel
1108     break;
1109   }
1110   MI->eraseFromParent();
1111   return true;
1112 }
1113 
1114 void  R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,
1115                                              const MachineFunction &MF) const {
1116   const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>(
1117       MF.getSubtarget().getFrameLowering());
1118 
1119   unsigned StackWidth = TFL->getStackWidth(MF);
1120   int End = getIndirectIndexEnd(MF);
1121 
1122   if (End == -1)
1123     return;
1124 
1125   for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
1126     unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
1127     Reserved.set(SuperReg);
1128     for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
1129       unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
1130       Reserved.set(Reg);
1131     }
1132   }
1133 }
1134 
1135 const TargetRegisterClass *R600InstrInfo::getIndirectAddrRegClass() const {
1136   return &AMDGPU::R600_TReg32_XRegClass;
1137 }
1138 
1139 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1140                                        MachineBasicBlock::iterator I,
1141                                        unsigned ValueReg, unsigned Address,
1142                                        unsigned OffsetReg) const {
1143   return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0);
1144 }
1145 
1146 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1147                                        MachineBasicBlock::iterator I,
1148                                        unsigned ValueReg, unsigned Address,
1149                                        unsigned OffsetReg,
1150                                        unsigned AddrChan) const {
1151   unsigned AddrReg;
1152   switch (AddrChan) {
1153     default: llvm_unreachable("Invalid Channel");
1154     case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break;
1155     case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break;
1156     case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break;
1157     case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address); break;
1158   }
1159   MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1160                                                AMDGPU::AR_X, OffsetReg);
1161   setImmOperand(MOVA, AMDGPU::OpName::write, 0);
1162 
1163   MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1164                                       AddrReg, ValueReg)
1165                                       .addReg(AMDGPU::AR_X,
1166                                            RegState::Implicit | RegState::Kill);
1167   setImmOperand(Mov, AMDGPU::OpName::dst_rel, 1);
1168   return Mov;
1169 }
1170 
1171 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1172                                        MachineBasicBlock::iterator I,
1173                                        unsigned ValueReg, unsigned Address,
1174                                        unsigned OffsetReg) const {
1175   return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0);
1176 }
1177 
1178 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1179                                        MachineBasicBlock::iterator I,
1180                                        unsigned ValueReg, unsigned Address,
1181                                        unsigned OffsetReg,
1182                                        unsigned AddrChan) const {
1183   unsigned AddrReg;
1184   switch (AddrChan) {
1185     default: llvm_unreachable("Invalid Channel");
1186     case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break;
1187     case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break;
1188     case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break;
1189     case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address); break;
1190   }
1191   MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1192                                                        AMDGPU::AR_X,
1193                                                        OffsetReg);
1194   setImmOperand(MOVA, AMDGPU::OpName::write, 0);
1195   MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1196                                       ValueReg,
1197                                       AddrReg)
1198                                       .addReg(AMDGPU::AR_X,
1199                                            RegState::Implicit | RegState::Kill);
1200   setImmOperand(Mov, AMDGPU::OpName::src0_rel, 1);
1201 
1202   return Mov;
1203 }
1204 
1205 unsigned R600InstrInfo::getMaxAlusPerClause() const {
1206   return 115;
1207 }
1208 
1209 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
1210                                                   MachineBasicBlock::iterator I,
1211                                                   unsigned Opcode,
1212                                                   unsigned DstReg,
1213                                                   unsigned Src0Reg,
1214                                                   unsigned Src1Reg) const {
1215   MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
1216     DstReg);           // $dst
1217 
1218   if (Src1Reg) {
1219     MIB.addImm(0)     // $update_exec_mask
1220        .addImm(0);    // $update_predicate
1221   }
1222   MIB.addImm(1)        // $write
1223      .addImm(0)        // $omod
1224      .addImm(0)        // $dst_rel
1225      .addImm(0)        // $dst_clamp
1226      .addReg(Src0Reg)  // $src0
1227      .addImm(0)        // $src0_neg
1228      .addImm(0)        // $src0_rel
1229      .addImm(0)        // $src0_abs
1230      .addImm(-1);       // $src0_sel
1231 
1232   if (Src1Reg) {
1233     MIB.addReg(Src1Reg) // $src1
1234        .addImm(0)       // $src1_neg
1235        .addImm(0)       // $src1_rel
1236        .addImm(0)       // $src1_abs
1237        .addImm(-1);      // $src1_sel
1238   }
1239 
1240   //XXX: The r600g finalizer expects this to be 1, once we've moved the
1241   //scheduling to the backend, we can change the default to 0.
1242   MIB.addImm(1)        // $last
1243       .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
1244       .addImm(0)         // $literal
1245       .addImm(0);        // $bank_swizzle
1246 
1247   return MIB;
1248 }
1249 
1250 #define OPERAND_CASE(Label) \
1251   case Label: { \
1252     static const unsigned Ops[] = \
1253     { \
1254       Label##_X, \
1255       Label##_Y, \
1256       Label##_Z, \
1257       Label##_W \
1258     }; \
1259     return Ops[Slot]; \
1260   }
1261 
1262 static unsigned getSlotedOps(unsigned  Op, unsigned Slot) {
1263   switch (Op) {
1264   OPERAND_CASE(AMDGPU::OpName::update_exec_mask)
1265   OPERAND_CASE(AMDGPU::OpName::update_pred)
1266   OPERAND_CASE(AMDGPU::OpName::write)
1267   OPERAND_CASE(AMDGPU::OpName::omod)
1268   OPERAND_CASE(AMDGPU::OpName::dst_rel)
1269   OPERAND_CASE(AMDGPU::OpName::clamp)
1270   OPERAND_CASE(AMDGPU::OpName::src0)
1271   OPERAND_CASE(AMDGPU::OpName::src0_neg)
1272   OPERAND_CASE(AMDGPU::OpName::src0_rel)
1273   OPERAND_CASE(AMDGPU::OpName::src0_abs)
1274   OPERAND_CASE(AMDGPU::OpName::src0_sel)
1275   OPERAND_CASE(AMDGPU::OpName::src1)
1276   OPERAND_CASE(AMDGPU::OpName::src1_neg)
1277   OPERAND_CASE(AMDGPU::OpName::src1_rel)
1278   OPERAND_CASE(AMDGPU::OpName::src1_abs)
1279   OPERAND_CASE(AMDGPU::OpName::src1_sel)
1280   OPERAND_CASE(AMDGPU::OpName::pred_sel)
1281   default:
1282     llvm_unreachable("Wrong Operand");
1283   }
1284 }
1285 
1286 #undef OPERAND_CASE
1287 
1288 MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction(
1289     MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg)
1290     const {
1291   assert (MI->getOpcode() == AMDGPU::DOT_4 && "Not Implemented");
1292   unsigned Opcode;
1293   if (ST.getGeneration() <= AMDGPUSubtarget::R700)
1294     Opcode = AMDGPU::DOT4_r600;
1295   else
1296     Opcode = AMDGPU::DOT4_eg;
1297   MachineBasicBlock::iterator I = MI;
1298   MachineOperand &Src0 = MI->getOperand(
1299       getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot)));
1300   MachineOperand &Src1 = MI->getOperand(
1301       getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot)));
1302   MachineInstr *MIB = buildDefaultInstruction(
1303       MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
1304   static const unsigned  Operands[14] = {
1305     AMDGPU::OpName::update_exec_mask,
1306     AMDGPU::OpName::update_pred,
1307     AMDGPU::OpName::write,
1308     AMDGPU::OpName::omod,
1309     AMDGPU::OpName::dst_rel,
1310     AMDGPU::OpName::clamp,
1311     AMDGPU::OpName::src0_neg,
1312     AMDGPU::OpName::src0_rel,
1313     AMDGPU::OpName::src0_abs,
1314     AMDGPU::OpName::src0_sel,
1315     AMDGPU::OpName::src1_neg,
1316     AMDGPU::OpName::src1_rel,
1317     AMDGPU::OpName::src1_abs,
1318     AMDGPU::OpName::src1_sel,
1319   };
1320 
1321   MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
1322       getSlotedOps(AMDGPU::OpName::pred_sel, Slot)));
1323   MIB->getOperand(getOperandIdx(Opcode, AMDGPU::OpName::pred_sel))
1324       .setReg(MO.getReg());
1325 
1326   for (unsigned i = 0; i < 14; i++) {
1327     MachineOperand &MO = MI->getOperand(
1328         getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
1329     assert (MO.isImm());
1330     setImmOperand(MIB, Operands[i], MO.getImm());
1331   }
1332   MIB->getOperand(20).setImm(0);
1333   return MIB;
1334 }
1335 
1336 MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
1337                                          MachineBasicBlock::iterator I,
1338                                          unsigned DstReg,
1339                                          uint64_t Imm) const {
1340   MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
1341                                                   AMDGPU::ALU_LITERAL_X);
1342   setImmOperand(MovImm, AMDGPU::OpName::literal, Imm);
1343   return MovImm;
1344 }
1345 
1346 MachineInstr *R600InstrInfo::buildMovInstr(MachineBasicBlock *MBB,
1347                                        MachineBasicBlock::iterator I,
1348                                        unsigned DstReg, unsigned SrcReg) const {
1349   return buildDefaultInstruction(*MBB, I, AMDGPU::MOV, DstReg, SrcReg);
1350 }
1351 
1352 int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const {
1353   return getOperandIdx(MI.getOpcode(), Op);
1354 }
1355 
1356 int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const {
1357   return AMDGPU::getNamedOperandIdx(Opcode, Op);
1358 }
1359 
1360 void R600InstrInfo::setImmOperand(MachineInstr *MI, unsigned Op,
1361                                   int64_t Imm) const {
1362   int Idx = getOperandIdx(*MI, Op);
1363   assert(Idx != -1 && "Operand not supported for this instruction.");
1364   assert(MI->getOperand(Idx).isImm());
1365   MI->getOperand(Idx).setImm(Imm);
1366 }
1367 
1368 //===----------------------------------------------------------------------===//
1369 // Instruction flag getters/setters
1370 //===----------------------------------------------------------------------===//
1371 
1372 bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const {
1373   return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
1374 }
1375 
1376 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr *MI, unsigned SrcIdx,
1377                                          unsigned Flag) const {
1378   unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1379   int FlagIndex = 0;
1380   if (Flag != 0) {
1381     // If we pass something other than the default value of Flag to this
1382     // function, it means we are want to set a flag on an instruction
1383     // that uses native encoding.
1384     assert(HAS_NATIVE_OPERANDS(TargetFlags));
1385     bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3;
1386     switch (Flag) {
1387     case MO_FLAG_CLAMP:
1388       FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::clamp);
1389       break;
1390     case MO_FLAG_MASK:
1391       FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::write);
1392       break;
1393     case MO_FLAG_NOT_LAST:
1394     case MO_FLAG_LAST:
1395       FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::last);
1396       break;
1397     case MO_FLAG_NEG:
1398       switch (SrcIdx) {
1399       case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_neg); break;
1400       case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_neg); break;
1401       case 2: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src2_neg); break;
1402       }
1403       break;
1404 
1405     case MO_FLAG_ABS:
1406       assert(!IsOP3 && "Cannot set absolute value modifier for OP3 "
1407                        "instructions.");
1408       (void)IsOP3;
1409       switch (SrcIdx) {
1410       case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_abs); break;
1411       case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_abs); break;
1412       }
1413       break;
1414 
1415     default:
1416       FlagIndex = -1;
1417       break;
1418     }
1419     assert(FlagIndex != -1 && "Flag not supported for this instruction");
1420   } else {
1421       FlagIndex = GET_FLAG_OPERAND_IDX(TargetFlags);
1422       assert(FlagIndex != 0 &&
1423          "Instruction flags not supported for this instruction");
1424   }
1425 
1426   MachineOperand &FlagOp = MI->getOperand(FlagIndex);
1427   assert(FlagOp.isImm());
1428   return FlagOp;
1429 }
1430 
1431 void R600InstrInfo::addFlag(MachineInstr *MI, unsigned Operand,
1432                             unsigned Flag) const {
1433   unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1434   if (Flag == 0) {
1435     return;
1436   }
1437   if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1438     MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1439     if (Flag == MO_FLAG_NOT_LAST) {
1440       clearFlag(MI, Operand, MO_FLAG_LAST);
1441     } else if (Flag == MO_FLAG_MASK) {
1442       clearFlag(MI, Operand, Flag);
1443     } else {
1444       FlagOp.setImm(1);
1445     }
1446   } else {
1447       MachineOperand &FlagOp = getFlagOp(MI, Operand);
1448       FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
1449   }
1450 }
1451 
1452 void R600InstrInfo::clearFlag(MachineInstr *MI, unsigned Operand,
1453                               unsigned Flag) const {
1454   unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1455   if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1456     MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1457     FlagOp.setImm(0);
1458   } else {
1459     MachineOperand &FlagOp = getFlagOp(MI);
1460     unsigned InstFlags = FlagOp.getImm();
1461     InstFlags &= ~(Flag << (NUM_MO_FLAGS * Operand));
1462     FlagOp.setImm(InstFlags);
1463   }
1464 }
1465 
1466 bool R600InstrInfo::isRegisterStore(const MachineInstr &MI) const {
1467   return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE;
1468 }
1469 
1470 bool R600InstrInfo::isRegisterLoad(const MachineInstr &MI) const {
1471   return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;
1472 }
1473