1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief R600 Implementation of TargetInstrInfo.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "R600InstrInfo.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUSubtarget.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "R600Defines.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 
26 using namespace llvm;
27 
28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "AMDGPUGenDFAPacketizer.inc"
30 
31 R600InstrInfo::R600InstrInfo(const AMDGPUSubtarget &st)
32     : AMDGPUInstrInfo(st), RI() {}
33 
34 const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const {
35   return RI;
36 }
37 
38 bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
39   return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
40 }
41 
42 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
43   return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
44 }
45 
46 void
47 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
48                            MachineBasicBlock::iterator MI, DebugLoc DL,
49                            unsigned DestReg, unsigned SrcReg,
50                            bool KillSrc) const {
51   unsigned VectorComponents = 0;
52   if ((AMDGPU::R600_Reg128RegClass.contains(DestReg) ||
53       AMDGPU::R600_Reg128VerticalRegClass.contains(DestReg)) &&
54       (AMDGPU::R600_Reg128RegClass.contains(SrcReg) ||
55        AMDGPU::R600_Reg128VerticalRegClass.contains(SrcReg))) {
56     VectorComponents = 4;
57   } else if((AMDGPU::R600_Reg64RegClass.contains(DestReg) ||
58             AMDGPU::R600_Reg64VerticalRegClass.contains(DestReg)) &&
59             (AMDGPU::R600_Reg64RegClass.contains(SrcReg) ||
60              AMDGPU::R600_Reg64VerticalRegClass.contains(SrcReg))) {
61     VectorComponents = 2;
62   }
63 
64   if (VectorComponents > 0) {
65     for (unsigned I = 0; I < VectorComponents; I++) {
66       unsigned SubRegIndex = RI.getSubRegFromChannel(I);
67       buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
68                               RI.getSubReg(DestReg, SubRegIndex),
69                               RI.getSubReg(SrcReg, SubRegIndex))
70                               .addReg(DestReg,
71                                       RegState::Define | RegState::Implicit);
72     }
73   } else {
74     MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
75                                                   DestReg, SrcReg);
76     NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0))
77                                     .setIsKill(KillSrc);
78   }
79 }
80 
81 /// \returns true if \p MBBI can be moved into a new basic.
82 bool R600InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
83                                        MachineBasicBlock::iterator MBBI) const {
84   for (MachineInstr::const_mop_iterator I = MBBI->operands_begin(),
85                                         E = MBBI->operands_end(); I != E; ++I) {
86     if (I->isReg() && !TargetRegisterInfo::isVirtualRegister(I->getReg()) &&
87         I->isUse() && RI.isPhysRegLiveAcrossClauses(I->getReg()))
88       return false;
89   }
90   return true;
91 }
92 
93 bool R600InstrInfo::isMov(unsigned Opcode) const {
94 
95 
96   switch(Opcode) {
97   default: return false;
98   case AMDGPU::MOV:
99   case AMDGPU::MOV_IMM_F32:
100   case AMDGPU::MOV_IMM_I32:
101     return true;
102   }
103 }
104 
105 // Some instructions act as place holders to emulate operations that the GPU
106 // hardware does automatically. This function can be used to check if
107 // an opcode falls into this category.
108 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {
109   switch (Opcode) {
110   default: return false;
111   case AMDGPU::RETURN:
112     return true;
113   }
114 }
115 
116 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
117   return false;
118 }
119 
120 bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
121   switch(Opcode) {
122     default: return false;
123     case AMDGPU::CUBE_r600_pseudo:
124     case AMDGPU::CUBE_r600_real:
125     case AMDGPU::CUBE_eg_pseudo:
126     case AMDGPU::CUBE_eg_real:
127       return true;
128   }
129 }
130 
131 bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
132   unsigned TargetFlags = get(Opcode).TSFlags;
133 
134   return (TargetFlags & R600_InstFlag::ALU_INST);
135 }
136 
137 bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const {
138   unsigned TargetFlags = get(Opcode).TSFlags;
139 
140   return ((TargetFlags & R600_InstFlag::OP1) |
141           (TargetFlags & R600_InstFlag::OP2) |
142           (TargetFlags & R600_InstFlag::OP3));
143 }
144 
145 bool R600InstrInfo::isLDSInstr(unsigned Opcode) const {
146   unsigned TargetFlags = get(Opcode).TSFlags;
147 
148   return ((TargetFlags & R600_InstFlag::LDS_1A) |
149           (TargetFlags & R600_InstFlag::LDS_1A1D) |
150           (TargetFlags & R600_InstFlag::LDS_1A2D));
151 }
152 
153 bool R600InstrInfo::isLDSNoRetInstr(unsigned Opcode) const {
154   return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) == -1;
155 }
156 
157 bool R600InstrInfo::isLDSRetInstr(unsigned Opcode) const {
158   return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) != -1;
159 }
160 
161 bool R600InstrInfo::canBeConsideredALU(const MachineInstr *MI) const {
162   if (isALUInstr(MI->getOpcode()))
163     return true;
164   if (isVector(*MI) || isCubeOp(MI->getOpcode()))
165     return true;
166   switch (MI->getOpcode()) {
167   case AMDGPU::PRED_X:
168   case AMDGPU::INTERP_PAIR_XY:
169   case AMDGPU::INTERP_PAIR_ZW:
170   case AMDGPU::INTERP_VEC_LOAD:
171   case AMDGPU::COPY:
172   case AMDGPU::DOT_4:
173     return true;
174   default:
175     return false;
176   }
177 }
178 
179 bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
180   if (ST.hasCaymanISA())
181     return false;
182   return (get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU);
183 }
184 
185 bool R600InstrInfo::isTransOnly(const MachineInstr *MI) const {
186   return isTransOnly(MI->getOpcode());
187 }
188 
189 bool R600InstrInfo::isVectorOnly(unsigned Opcode) const {
190   return (get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU);
191 }
192 
193 bool R600InstrInfo::isVectorOnly(const MachineInstr *MI) const {
194   return isVectorOnly(MI->getOpcode());
195 }
196 
197 bool R600InstrInfo::isExport(unsigned Opcode) const {
198   return (get(Opcode).TSFlags & R600_InstFlag::IS_EXPORT);
199 }
200 
201 bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
202   return ST.hasVertexCache() && IS_VTX(get(Opcode));
203 }
204 
205 bool R600InstrInfo::usesVertexCache(const MachineInstr *MI) const {
206   const MachineFunction *MF = MI->getParent()->getParent();
207   return !AMDGPU::isCompute(MF->getFunction()->getCallingConv()) &&
208     usesVertexCache(MI->getOpcode());
209 }
210 
211 bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {
212   return (!ST.hasVertexCache() && IS_VTX(get(Opcode))) || IS_TEX(get(Opcode));
213 }
214 
215 bool R600InstrInfo::usesTextureCache(const MachineInstr *MI) const {
216   const MachineFunction *MF = MI->getParent()->getParent();
217   return (AMDGPU::isCompute(MF->getFunction()->getCallingConv()) &&
218           usesVertexCache(MI->getOpcode())) ||
219     usesTextureCache(MI->getOpcode());
220 }
221 
222 bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const {
223   switch (Opcode) {
224   case AMDGPU::KILLGT:
225   case AMDGPU::GROUP_BARRIER:
226     return true;
227   default:
228     return false;
229   }
230 }
231 
232 bool R600InstrInfo::usesAddressRegister(MachineInstr *MI) const {
233   return  MI->findRegisterUseOperandIdx(AMDGPU::AR_X) != -1;
234 }
235 
236 bool R600InstrInfo::definesAddressRegister(MachineInstr *MI) const {
237   return MI->findRegisterDefOperandIdx(AMDGPU::AR_X) != -1;
238 }
239 
240 bool R600InstrInfo::readsLDSSrcReg(const MachineInstr *MI) const {
241   if (!isALUInstr(MI->getOpcode())) {
242     return false;
243   }
244   for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
245                                         E = MI->operands_end(); I != E; ++I) {
246     if (!I->isReg() || !I->isUse() ||
247         TargetRegisterInfo::isVirtualRegister(I->getReg()))
248       continue;
249 
250     if (AMDGPU::R600_LDS_SRC_REGRegClass.contains(I->getReg()))
251       return true;
252   }
253   return false;
254 }
255 
256 int R600InstrInfo::getSrcIdx(unsigned Opcode, unsigned SrcNum) const {
257   static const unsigned OpTable[] = {
258     AMDGPU::OpName::src0,
259     AMDGPU::OpName::src1,
260     AMDGPU::OpName::src2
261   };
262 
263   assert (SrcNum < 3);
264   return getOperandIdx(Opcode, OpTable[SrcNum]);
265 }
266 
267 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const {
268   static const unsigned SrcSelTable[][2] = {
269     {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
270     {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
271     {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
272     {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
273     {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
274     {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
275     {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
276     {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
277     {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
278     {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
279     {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W}
280   };
281 
282   for (const auto &Row : SrcSelTable) {
283     if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) {
284       return getOperandIdx(Opcode, Row[1]);
285     }
286   }
287   return -1;
288 }
289 
290 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
291 R600InstrInfo::getSrcs(MachineInstr *MI) const {
292   SmallVector<std::pair<MachineOperand *, int64_t>, 3> Result;
293 
294   if (MI->getOpcode() == AMDGPU::DOT_4) {
295     static const unsigned OpTable[8][2] = {
296       {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
297       {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
298       {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
299       {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
300       {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
301       {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
302       {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
303       {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W},
304     };
305 
306     for (unsigned j = 0; j < 8; j++) {
307       MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
308                                                         OpTable[j][0]));
309       unsigned Reg = MO.getReg();
310       if (Reg == AMDGPU::ALU_CONST) {
311         MachineOperand &Sel = MI->getOperand(getOperandIdx(MI->getOpcode(),
312                                                     OpTable[j][1]));
313         Result.push_back(std::make_pair(&MO, Sel.getImm()));
314         continue;
315       }
316 
317     }
318     return Result;
319   }
320 
321   static const unsigned OpTable[3][2] = {
322     {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
323     {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
324     {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
325   };
326 
327   for (unsigned j = 0; j < 3; j++) {
328     int SrcIdx = getOperandIdx(MI->getOpcode(), OpTable[j][0]);
329     if (SrcIdx < 0)
330       break;
331     MachineOperand &MO = MI->getOperand(SrcIdx);
332     unsigned Reg = MO.getReg();
333     if (Reg == AMDGPU::ALU_CONST) {
334       MachineOperand &Sel = MI->getOperand(
335           getOperandIdx(MI->getOpcode(), OpTable[j][1]));
336       Result.push_back(std::make_pair(&MO, Sel.getImm()));
337       continue;
338     }
339     if (Reg == AMDGPU::ALU_LITERAL_X) {
340       MachineOperand &Imm = MI->getOperand(
341           getOperandIdx(MI->getOpcode(), AMDGPU::OpName::literal));
342       Result.push_back(std::make_pair(&MO, Imm.getImm()));
343       continue;
344     }
345     Result.push_back(std::make_pair(&MO, 0));
346   }
347   return Result;
348 }
349 
350 std::vector<std::pair<int, unsigned> >
351 R600InstrInfo::ExtractSrcs(MachineInstr *MI,
352                            const DenseMap<unsigned, unsigned> &PV,
353                            unsigned &ConstCount) const {
354   ConstCount = 0;
355   ArrayRef<std::pair<MachineOperand *, int64_t>> Srcs = getSrcs(MI);
356   const std::pair<int, unsigned> DummyPair(-1, 0);
357   std::vector<std::pair<int, unsigned> > Result;
358   unsigned i = 0;
359   for (unsigned n = Srcs.size(); i < n; ++i) {
360     unsigned Reg = Srcs[i].first->getReg();
361     int Index = RI.getEncodingValue(Reg) & 0xff;
362     if (Reg == AMDGPU::OQAP) {
363       Result.push_back(std::make_pair(Index, 0U));
364     }
365     if (PV.find(Reg) != PV.end()) {
366       // 255 is used to tells its a PS/PV reg
367       Result.push_back(std::make_pair(255, 0U));
368       continue;
369     }
370     if (Index > 127) {
371       ConstCount++;
372       Result.push_back(DummyPair);
373       continue;
374     }
375     unsigned Chan = RI.getHWRegChan(Reg);
376     Result.push_back(std::make_pair(Index, Chan));
377   }
378   for (; i < 3; ++i)
379     Result.push_back(DummyPair);
380   return Result;
381 }
382 
383 static std::vector<std::pair<int, unsigned> >
384 Swizzle(std::vector<std::pair<int, unsigned> > Src,
385         R600InstrInfo::BankSwizzle Swz) {
386   if (Src[0] == Src[1])
387     Src[1].first = -1;
388   switch (Swz) {
389   case R600InstrInfo::ALU_VEC_012_SCL_210:
390     break;
391   case R600InstrInfo::ALU_VEC_021_SCL_122:
392     std::swap(Src[1], Src[2]);
393     break;
394   case R600InstrInfo::ALU_VEC_102_SCL_221:
395     std::swap(Src[0], Src[1]);
396     break;
397   case R600InstrInfo::ALU_VEC_120_SCL_212:
398     std::swap(Src[0], Src[1]);
399     std::swap(Src[0], Src[2]);
400     break;
401   case R600InstrInfo::ALU_VEC_201:
402     std::swap(Src[0], Src[2]);
403     std::swap(Src[0], Src[1]);
404     break;
405   case R600InstrInfo::ALU_VEC_210:
406     std::swap(Src[0], Src[2]);
407     break;
408   }
409   return Src;
410 }
411 
412 static unsigned
413 getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) {
414   switch (Swz) {
415   case R600InstrInfo::ALU_VEC_012_SCL_210: {
416     unsigned Cycles[3] = { 2, 1, 0};
417     return Cycles[Op];
418   }
419   case R600InstrInfo::ALU_VEC_021_SCL_122: {
420     unsigned Cycles[3] = { 1, 2, 2};
421     return Cycles[Op];
422   }
423   case R600InstrInfo::ALU_VEC_120_SCL_212: {
424     unsigned Cycles[3] = { 2, 1, 2};
425     return Cycles[Op];
426   }
427   case R600InstrInfo::ALU_VEC_102_SCL_221: {
428     unsigned Cycles[3] = { 2, 2, 1};
429     return Cycles[Op];
430   }
431   default:
432     llvm_unreachable("Wrong Swizzle for Trans Slot");
433     return 0;
434   }
435 }
436 
437 /// returns how many MIs (whose inputs are represented by IGSrcs) can be packed
438 /// in the same Instruction Group while meeting read port limitations given a
439 /// Swz swizzle sequence.
440 unsigned  R600InstrInfo::isLegalUpTo(
441     const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
442     const std::vector<R600InstrInfo::BankSwizzle> &Swz,
443     const std::vector<std::pair<int, unsigned> > &TransSrcs,
444     R600InstrInfo::BankSwizzle TransSwz) const {
445   int Vector[4][3];
446   memset(Vector, -1, sizeof(Vector));
447   for (unsigned i = 0, e = IGSrcs.size(); i < e; i++) {
448     const std::vector<std::pair<int, unsigned> > &Srcs =
449         Swizzle(IGSrcs[i], Swz[i]);
450     for (unsigned j = 0; j < 3; j++) {
451       const std::pair<int, unsigned> &Src = Srcs[j];
452       if (Src.first < 0 || Src.first == 255)
453         continue;
454       if (Src.first == GET_REG_INDEX(RI.getEncodingValue(AMDGPU::OQAP))) {
455         if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 &&
456             Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) {
457             // The value from output queue A (denoted by register OQAP) can
458             // only be fetched during the first cycle.
459             return false;
460         }
461         // OQAP does not count towards the normal read port restrictions
462         continue;
463       }
464       if (Vector[Src.second][j] < 0)
465         Vector[Src.second][j] = Src.first;
466       if (Vector[Src.second][j] != Src.first)
467         return i;
468     }
469   }
470   // Now check Trans Alu
471   for (unsigned i = 0, e = TransSrcs.size(); i < e; ++i) {
472     const std::pair<int, unsigned> &Src = TransSrcs[i];
473     unsigned Cycle = getTransSwizzle(TransSwz, i);
474     if (Src.first < 0)
475       continue;
476     if (Src.first == 255)
477       continue;
478     if (Vector[Src.second][Cycle] < 0)
479       Vector[Src.second][Cycle] = Src.first;
480     if (Vector[Src.second][Cycle] != Src.first)
481       return IGSrcs.size() - 1;
482   }
483   return IGSrcs.size();
484 }
485 
486 /// Given a swizzle sequence SwzCandidate and an index Idx, returns the next
487 /// (in lexicographic term) swizzle sequence assuming that all swizzles after
488 /// Idx can be skipped
489 static bool
490 NextPossibleSolution(
491     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
492     unsigned Idx) {
493   assert(Idx < SwzCandidate.size());
494   int ResetIdx = Idx;
495   while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210)
496     ResetIdx --;
497   for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) {
498     SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210;
499   }
500   if (ResetIdx == -1)
501     return false;
502   int NextSwizzle = SwzCandidate[ResetIdx] + 1;
503   SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle;
504   return true;
505 }
506 
507 /// Enumerate all possible Swizzle sequence to find one that can meet all
508 /// read port requirements.
509 bool R600InstrInfo::FindSwizzleForVectorSlot(
510     const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
511     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
512     const std::vector<std::pair<int, unsigned> > &TransSrcs,
513     R600InstrInfo::BankSwizzle TransSwz) const {
514   unsigned ValidUpTo = 0;
515   do {
516     ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz);
517     if (ValidUpTo == IGSrcs.size())
518       return true;
519   } while (NextPossibleSolution(SwzCandidate, ValidUpTo));
520   return false;
521 }
522 
523 /// Instructions in Trans slot can't read gpr at cycle 0 if they also read
524 /// a const, and can't read a gpr at cycle 1 if they read 2 const.
525 static bool
526 isConstCompatible(R600InstrInfo::BankSwizzle TransSwz,
527                   const std::vector<std::pair<int, unsigned> > &TransOps,
528                   unsigned ConstCount) {
529   // TransALU can't read 3 constants
530   if (ConstCount > 2)
531     return false;
532   for (unsigned i = 0, e = TransOps.size(); i < e; ++i) {
533     const std::pair<int, unsigned> &Src = TransOps[i];
534     unsigned Cycle = getTransSwizzle(TransSwz, i);
535     if (Src.first < 0)
536       continue;
537     if (ConstCount > 0 && Cycle == 0)
538       return false;
539     if (ConstCount > 1 && Cycle == 1)
540       return false;
541   }
542   return true;
543 }
544 
545 bool
546 R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
547                                        const DenseMap<unsigned, unsigned> &PV,
548                                        std::vector<BankSwizzle> &ValidSwizzle,
549                                        bool isLastAluTrans)
550     const {
551   //Todo : support shared src0 - src1 operand
552 
553   std::vector<std::vector<std::pair<int, unsigned> > > IGSrcs;
554   ValidSwizzle.clear();
555   unsigned ConstCount;
556   BankSwizzle TransBS = ALU_VEC_012_SCL_210;
557   for (unsigned i = 0, e = IG.size(); i < e; ++i) {
558     IGSrcs.push_back(ExtractSrcs(IG[i], PV, ConstCount));
559     unsigned Op = getOperandIdx(IG[i]->getOpcode(),
560         AMDGPU::OpName::bank_swizzle);
561     ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle)
562         IG[i]->getOperand(Op).getImm());
563   }
564   std::vector<std::pair<int, unsigned> > TransOps;
565   if (!isLastAluTrans)
566     return FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps, TransBS);
567 
568   TransOps = std::move(IGSrcs.back());
569   IGSrcs.pop_back();
570   ValidSwizzle.pop_back();
571 
572   static const R600InstrInfo::BankSwizzle TransSwz[] = {
573     ALU_VEC_012_SCL_210,
574     ALU_VEC_021_SCL_122,
575     ALU_VEC_120_SCL_212,
576     ALU_VEC_102_SCL_221
577   };
578   for (unsigned i = 0; i < 4; i++) {
579     TransBS = TransSwz[i];
580     if (!isConstCompatible(TransBS, TransOps, ConstCount))
581       continue;
582     bool Result = FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps,
583         TransBS);
584     if (Result) {
585       ValidSwizzle.push_back(TransBS);
586       return true;
587     }
588   }
589 
590   return false;
591 }
592 
593 
594 bool
595 R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)
596     const {
597   assert (Consts.size() <= 12 && "Too many operands in instructions group");
598   unsigned Pair1 = 0, Pair2 = 0;
599   for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
600     unsigned ReadConstHalf = Consts[i] & 2;
601     unsigned ReadConstIndex = Consts[i] & (~3);
602     unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
603     if (!Pair1) {
604       Pair1 = ReadHalfConst;
605       continue;
606     }
607     if (Pair1 == ReadHalfConst)
608       continue;
609     if (!Pair2) {
610       Pair2 = ReadHalfConst;
611       continue;
612     }
613     if (Pair2 != ReadHalfConst)
614       return false;
615   }
616   return true;
617 }
618 
619 bool
620 R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs)
621     const {
622   std::vector<unsigned> Consts;
623   SmallSet<int64_t, 4> Literals;
624   for (unsigned i = 0, n = MIs.size(); i < n; i++) {
625     MachineInstr *MI = MIs[i];
626     if (!isALUInstr(MI->getOpcode()))
627       continue;
628 
629     ArrayRef<std::pair<MachineOperand *, int64_t>> Srcs = getSrcs(MI);
630 
631     for (const auto &Src:Srcs) {
632       if (Src.first->getReg() == AMDGPU::ALU_LITERAL_X)
633         Literals.insert(Src.second);
634       if (Literals.size() > 4)
635         return false;
636       if (Src.first->getReg() == AMDGPU::ALU_CONST)
637         Consts.push_back(Src.second);
638       if (AMDGPU::R600_KC0RegClass.contains(Src.first->getReg()) ||
639           AMDGPU::R600_KC1RegClass.contains(Src.first->getReg())) {
640         unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
641         unsigned Chan = RI.getHWRegChan(Src.first->getReg());
642         Consts.push_back((Index << 2) | Chan);
643       }
644     }
645   }
646   return fitsConstReadLimitations(Consts);
647 }
648 
649 DFAPacketizer *
650 R600InstrInfo::CreateTargetScheduleState(const TargetSubtargetInfo &STI) const {
651   const InstrItineraryData *II = STI.getInstrItineraryData();
652   return static_cast<const AMDGPUSubtarget &>(STI).createDFAPacketizer(II);
653 }
654 
655 static bool
656 isPredicateSetter(unsigned Opcode) {
657   switch (Opcode) {
658   case AMDGPU::PRED_X:
659     return true;
660   default:
661     return false;
662   }
663 }
664 
665 static MachineInstr *
666 findFirstPredicateSetterFrom(MachineBasicBlock &MBB,
667                              MachineBasicBlock::iterator I) {
668   while (I != MBB.begin()) {
669     --I;
670     MachineInstr *MI = I;
671     if (isPredicateSetter(MI->getOpcode()))
672       return MI;
673   }
674 
675   return nullptr;
676 }
677 
678 static
679 bool isJump(unsigned Opcode) {
680   return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND;
681 }
682 
683 static bool isBranch(unsigned Opcode) {
684   return Opcode == AMDGPU::BRANCH || Opcode == AMDGPU::BRANCH_COND_i32 ||
685       Opcode == AMDGPU::BRANCH_COND_f32;
686 }
687 
688 bool
689 R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
690                              MachineBasicBlock *&TBB,
691                              MachineBasicBlock *&FBB,
692                              SmallVectorImpl<MachineOperand> &Cond,
693                              bool AllowModify) const {
694   // Most of the following comes from the ARM implementation of AnalyzeBranch
695 
696   // If the block has no terminators, it just falls into the block after it.
697   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
698   if (I == MBB.end())
699     return false;
700 
701   // AMDGPU::BRANCH* instructions are only available after isel and are not
702   // handled
703   if (isBranch(I->getOpcode()))
704     return true;
705   if (!isJump(static_cast<MachineInstr *>(I)->getOpcode())) {
706     return false;
707   }
708 
709   // Remove successive JUMP
710   while (I != MBB.begin() && std::prev(I)->getOpcode() == AMDGPU::JUMP) {
711       MachineBasicBlock::iterator PriorI = std::prev(I);
712       if (AllowModify)
713         I->removeFromParent();
714       I = PriorI;
715   }
716   MachineInstr *LastInst = I;
717 
718   // If there is only one terminator instruction, process it.
719   unsigned LastOpc = LastInst->getOpcode();
720   if (I == MBB.begin() ||
721           !isJump(static_cast<MachineInstr *>(--I)->getOpcode())) {
722     if (LastOpc == AMDGPU::JUMP) {
723       TBB = LastInst->getOperand(0).getMBB();
724       return false;
725     } else if (LastOpc == AMDGPU::JUMP_COND) {
726       MachineInstr *predSet = I;
727       while (!isPredicateSetter(predSet->getOpcode())) {
728         predSet = --I;
729       }
730       TBB = LastInst->getOperand(0).getMBB();
731       Cond.push_back(predSet->getOperand(1));
732       Cond.push_back(predSet->getOperand(2));
733       Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
734       return false;
735     }
736     return true;  // Can't handle indirect branch.
737   }
738 
739   // Get the instruction before it if it is a terminator.
740   MachineInstr *SecondLastInst = I;
741   unsigned SecondLastOpc = SecondLastInst->getOpcode();
742 
743   // If the block ends with a B and a Bcc, handle it.
744   if (SecondLastOpc == AMDGPU::JUMP_COND && LastOpc == AMDGPU::JUMP) {
745     MachineInstr *predSet = --I;
746     while (!isPredicateSetter(predSet->getOpcode())) {
747       predSet = --I;
748     }
749     TBB = SecondLastInst->getOperand(0).getMBB();
750     FBB = LastInst->getOperand(0).getMBB();
751     Cond.push_back(predSet->getOperand(1));
752     Cond.push_back(predSet->getOperand(2));
753     Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
754     return false;
755   }
756 
757   // Otherwise, can't handle this.
758   return true;
759 }
760 
761 static
762 MachineBasicBlock::iterator FindLastAluClause(MachineBasicBlock &MBB) {
763   for (MachineBasicBlock::reverse_iterator It = MBB.rbegin(), E = MBB.rend();
764       It != E; ++It) {
765     if (It->getOpcode() == AMDGPU::CF_ALU ||
766         It->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
767       return std::prev(It.base());
768   }
769   return MBB.end();
770 }
771 
772 unsigned
773 R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
774                             MachineBasicBlock *TBB,
775                             MachineBasicBlock *FBB,
776                             ArrayRef<MachineOperand> Cond,
777                             DebugLoc DL) const {
778   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
779 
780   if (!FBB) {
781     if (Cond.empty()) {
782       BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB);
783       return 1;
784     } else {
785       MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
786       assert(PredSet && "No previous predicate !");
787       addFlag(PredSet, 0, MO_FLAG_PUSH);
788       PredSet->getOperand(2).setImm(Cond[1].getImm());
789 
790       BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
791              .addMBB(TBB)
792              .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
793       MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
794       if (CfAlu == MBB.end())
795         return 1;
796       assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
797       CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
798       return 1;
799     }
800   } else {
801     MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
802     assert(PredSet && "No previous predicate !");
803     addFlag(PredSet, 0, MO_FLAG_PUSH);
804     PredSet->getOperand(2).setImm(Cond[1].getImm());
805     BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
806             .addMBB(TBB)
807             .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
808     BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB);
809     MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
810     if (CfAlu == MBB.end())
811       return 2;
812     assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
813     CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
814     return 2;
815   }
816 }
817 
818 unsigned
819 R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
820 
821   // Note : we leave PRED* instructions there.
822   // They may be needed when predicating instructions.
823 
824   MachineBasicBlock::iterator I = MBB.end();
825 
826   if (I == MBB.begin()) {
827     return 0;
828   }
829   --I;
830   switch (I->getOpcode()) {
831   default:
832     return 0;
833   case AMDGPU::JUMP_COND: {
834     MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
835     clearFlag(predSet, 0, MO_FLAG_PUSH);
836     I->eraseFromParent();
837     MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
838     if (CfAlu == MBB.end())
839       break;
840     assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
841     CfAlu->setDesc(get(AMDGPU::CF_ALU));
842     break;
843   }
844   case AMDGPU::JUMP:
845     I->eraseFromParent();
846     break;
847   }
848   I = MBB.end();
849 
850   if (I == MBB.begin()) {
851     return 1;
852   }
853   --I;
854   switch (I->getOpcode()) {
855     // FIXME: only one case??
856   default:
857     return 1;
858   case AMDGPU::JUMP_COND: {
859     MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
860     clearFlag(predSet, 0, MO_FLAG_PUSH);
861     I->eraseFromParent();
862     MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
863     if (CfAlu == MBB.end())
864       break;
865     assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
866     CfAlu->setDesc(get(AMDGPU::CF_ALU));
867     break;
868   }
869   case AMDGPU::JUMP:
870     I->eraseFromParent();
871     break;
872   }
873   return 2;
874 }
875 
876 bool R600InstrInfo::isPredicated(const MachineInstr &MI) const {
877   int idx = MI.findFirstPredOperandIdx();
878   if (idx < 0)
879     return false;
880 
881   unsigned Reg = MI.getOperand(idx).getReg();
882   switch (Reg) {
883   default: return false;
884   case AMDGPU::PRED_SEL_ONE:
885   case AMDGPU::PRED_SEL_ZERO:
886   case AMDGPU::PREDICATE_BIT:
887     return true;
888   }
889 }
890 
891 bool R600InstrInfo::isPredicable(MachineInstr &MI) const {
892   // XXX: KILL* instructions can be predicated, but they must be the last
893   // instruction in a clause, so this means any instructions after them cannot
894   // be predicated.  Until we have proper support for instruction clauses in the
895   // backend, we will mark KILL* instructions as unpredicable.
896 
897   if (MI.getOpcode() == AMDGPU::KILLGT) {
898     return false;
899   } else if (MI.getOpcode() == AMDGPU::CF_ALU) {
900     // If the clause start in the middle of MBB then the MBB has more
901     // than a single clause, unable to predicate several clauses.
902     if (MI.getParent()->begin() != MachineBasicBlock::iterator(MI))
903       return false;
904     // TODO: We don't support KC merging atm
905     return MI.getOperand(3).getImm() == 0 && MI.getOperand(4).getImm() == 0;
906   } else if (isVector(MI)) {
907     return false;
908   } else {
909     return AMDGPUInstrInfo::isPredicable(MI);
910   }
911 }
912 
913 
914 bool
915 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
916                                    unsigned NumCyles,
917                                    unsigned ExtraPredCycles,
918                                    BranchProbability Probability) const{
919   return true;
920 }
921 
922 bool
923 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
924                                    unsigned NumTCycles,
925                                    unsigned ExtraTCycles,
926                                    MachineBasicBlock &FMBB,
927                                    unsigned NumFCycles,
928                                    unsigned ExtraFCycles,
929                                    BranchProbability Probability) const {
930   return true;
931 }
932 
933 bool
934 R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
935                                          unsigned NumCyles,
936                                          BranchProbability Probability)
937                                          const {
938   return true;
939 }
940 
941 bool
942 R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
943                                          MachineBasicBlock &FMBB) const {
944   return false;
945 }
946 
947 
948 bool
949 R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
950   MachineOperand &MO = Cond[1];
951   switch (MO.getImm()) {
952   case OPCODE_IS_ZERO_INT:
953     MO.setImm(OPCODE_IS_NOT_ZERO_INT);
954     break;
955   case OPCODE_IS_NOT_ZERO_INT:
956     MO.setImm(OPCODE_IS_ZERO_INT);
957     break;
958   case OPCODE_IS_ZERO:
959     MO.setImm(OPCODE_IS_NOT_ZERO);
960     break;
961   case OPCODE_IS_NOT_ZERO:
962     MO.setImm(OPCODE_IS_ZERO);
963     break;
964   default:
965     return true;
966   }
967 
968   MachineOperand &MO2 = Cond[2];
969   switch (MO2.getReg()) {
970   case AMDGPU::PRED_SEL_ZERO:
971     MO2.setReg(AMDGPU::PRED_SEL_ONE);
972     break;
973   case AMDGPU::PRED_SEL_ONE:
974     MO2.setReg(AMDGPU::PRED_SEL_ZERO);
975     break;
976   default:
977     return true;
978   }
979   return false;
980 }
981 
982 bool R600InstrInfo::DefinesPredicate(MachineInstr &MI,
983                                      std::vector<MachineOperand> &Pred) const {
984   return isPredicateSetter(MI.getOpcode());
985 }
986 
987 
988 bool
989 R600InstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
990                                  ArrayRef<MachineOperand> Pred2) const {
991   return false;
992 }
993 
994 bool R600InstrInfo::PredicateInstruction(MachineInstr &MI,
995                                          ArrayRef<MachineOperand> Pred) const {
996   int PIdx = MI.findFirstPredOperandIdx();
997 
998   if (MI.getOpcode() == AMDGPU::CF_ALU) {
999     MI.getOperand(8).setImm(0);
1000     return true;
1001   }
1002 
1003   if (MI.getOpcode() == AMDGPU::DOT_4) {
1004     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_X))
1005         .setReg(Pred[2].getReg());
1006     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_Y))
1007         .setReg(Pred[2].getReg());
1008     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_Z))
1009         .setReg(Pred[2].getReg());
1010     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_W))
1011         .setReg(Pred[2].getReg());
1012     MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
1013     MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
1014     return true;
1015   }
1016 
1017   if (PIdx != -1) {
1018     MachineOperand &PMO = MI.getOperand(PIdx);
1019     PMO.setReg(Pred[2].getReg());
1020     MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
1021     MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
1022     return true;
1023   }
1024 
1025   return false;
1026 }
1027 
1028 unsigned int R600InstrInfo::getPredicationCost(const MachineInstr &) const {
1029   return 2;
1030 }
1031 
1032 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1033                                             const MachineInstr *MI,
1034                                             unsigned *PredCost) const {
1035   if (PredCost)
1036     *PredCost = 2;
1037   return 2;
1038 }
1039 
1040 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex,
1041                                                    unsigned Channel) const {
1042   assert(Channel == 0);
1043   return RegIndex;
1044 }
1045 
1046 bool R600InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
1047 
1048   switch(MI->getOpcode()) {
1049   default: {
1050     MachineBasicBlock *MBB = MI->getParent();
1051     int OffsetOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1052                                                  AMDGPU::OpName::addr);
1053      // addr is a custom operand with multiple MI operands, and only the
1054      // first MI operand is given a name.
1055     int RegOpIdx = OffsetOpIdx + 1;
1056     int ChanOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1057                                                AMDGPU::OpName::chan);
1058     if (isRegisterLoad(*MI)) {
1059       int DstOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1060                                                 AMDGPU::OpName::dst);
1061       unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
1062       unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
1063       unsigned Address = calculateIndirectAddress(RegIndex, Channel);
1064       unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
1065       if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
1066         buildMovInstr(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
1067                       getIndirectAddrRegClass()->getRegister(Address));
1068       } else {
1069         buildIndirectRead(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
1070                           Address, OffsetReg);
1071       }
1072     } else if (isRegisterStore(*MI)) {
1073       int ValOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1074                                                 AMDGPU::OpName::val);
1075       unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
1076       unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
1077       unsigned Address = calculateIndirectAddress(RegIndex, Channel);
1078       unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
1079       if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
1080         buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address),
1081                       MI->getOperand(ValOpIdx).getReg());
1082       } else {
1083         buildIndirectWrite(MBB, MI, MI->getOperand(ValOpIdx).getReg(),
1084                            calculateIndirectAddress(RegIndex, Channel),
1085                            OffsetReg);
1086       }
1087     } else {
1088       return false;
1089     }
1090 
1091     MBB->erase(MI);
1092     return true;
1093   }
1094   case AMDGPU::R600_EXTRACT_ELT_V2:
1095   case AMDGPU::R600_EXTRACT_ELT_V4:
1096     buildIndirectRead(MI->getParent(), MI, MI->getOperand(0).getReg(),
1097                       RI.getHWRegIndex(MI->getOperand(1).getReg()), //  Address
1098                       MI->getOperand(2).getReg(),
1099                       RI.getHWRegChan(MI->getOperand(1).getReg()));
1100     break;
1101   case AMDGPU::R600_INSERT_ELT_V2:
1102   case AMDGPU::R600_INSERT_ELT_V4:
1103     buildIndirectWrite(MI->getParent(), MI, MI->getOperand(2).getReg(), // Value
1104                        RI.getHWRegIndex(MI->getOperand(1).getReg()),  // Address
1105                        MI->getOperand(3).getReg(),                    // Offset
1106                        RI.getHWRegChan(MI->getOperand(1).getReg()));  // Channel
1107     break;
1108   }
1109   MI->eraseFromParent();
1110   return true;
1111 }
1112 
1113 void  R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,
1114                                              const MachineFunction &MF) const {
1115   const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>(
1116       MF.getSubtarget().getFrameLowering());
1117 
1118   unsigned StackWidth = TFL->getStackWidth(MF);
1119   int End = getIndirectIndexEnd(MF);
1120 
1121   if (End == -1)
1122     return;
1123 
1124   for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
1125     unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
1126     Reserved.set(SuperReg);
1127     for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
1128       unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
1129       Reserved.set(Reg);
1130     }
1131   }
1132 }
1133 
1134 const TargetRegisterClass *R600InstrInfo::getIndirectAddrRegClass() const {
1135   return &AMDGPU::R600_TReg32_XRegClass;
1136 }
1137 
1138 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1139                                        MachineBasicBlock::iterator I,
1140                                        unsigned ValueReg, unsigned Address,
1141                                        unsigned OffsetReg) const {
1142   return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0);
1143 }
1144 
1145 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1146                                        MachineBasicBlock::iterator I,
1147                                        unsigned ValueReg, unsigned Address,
1148                                        unsigned OffsetReg,
1149                                        unsigned AddrChan) const {
1150   unsigned AddrReg;
1151   switch (AddrChan) {
1152     default: llvm_unreachable("Invalid Channel");
1153     case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break;
1154     case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break;
1155     case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break;
1156     case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address); break;
1157   }
1158   MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1159                                                AMDGPU::AR_X, OffsetReg);
1160   setImmOperand(MOVA, AMDGPU::OpName::write, 0);
1161 
1162   MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1163                                       AddrReg, ValueReg)
1164                                       .addReg(AMDGPU::AR_X,
1165                                            RegState::Implicit | RegState::Kill);
1166   setImmOperand(Mov, AMDGPU::OpName::dst_rel, 1);
1167   return Mov;
1168 }
1169 
1170 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1171                                        MachineBasicBlock::iterator I,
1172                                        unsigned ValueReg, unsigned Address,
1173                                        unsigned OffsetReg) const {
1174   return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0);
1175 }
1176 
1177 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1178                                        MachineBasicBlock::iterator I,
1179                                        unsigned ValueReg, unsigned Address,
1180                                        unsigned OffsetReg,
1181                                        unsigned AddrChan) const {
1182   unsigned AddrReg;
1183   switch (AddrChan) {
1184     default: llvm_unreachable("Invalid Channel");
1185     case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break;
1186     case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break;
1187     case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break;
1188     case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address); break;
1189   }
1190   MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1191                                                        AMDGPU::AR_X,
1192                                                        OffsetReg);
1193   setImmOperand(MOVA, AMDGPU::OpName::write, 0);
1194   MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1195                                       ValueReg,
1196                                       AddrReg)
1197                                       .addReg(AMDGPU::AR_X,
1198                                            RegState::Implicit | RegState::Kill);
1199   setImmOperand(Mov, AMDGPU::OpName::src0_rel, 1);
1200 
1201   return Mov;
1202 }
1203 
1204 unsigned R600InstrInfo::getMaxAlusPerClause() const {
1205   return 115;
1206 }
1207 
1208 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
1209                                                   MachineBasicBlock::iterator I,
1210                                                   unsigned Opcode,
1211                                                   unsigned DstReg,
1212                                                   unsigned Src0Reg,
1213                                                   unsigned Src1Reg) const {
1214   MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
1215     DstReg);           // $dst
1216 
1217   if (Src1Reg) {
1218     MIB.addImm(0)     // $update_exec_mask
1219        .addImm(0);    // $update_predicate
1220   }
1221   MIB.addImm(1)        // $write
1222      .addImm(0)        // $omod
1223      .addImm(0)        // $dst_rel
1224      .addImm(0)        // $dst_clamp
1225      .addReg(Src0Reg)  // $src0
1226      .addImm(0)        // $src0_neg
1227      .addImm(0)        // $src0_rel
1228      .addImm(0)        // $src0_abs
1229      .addImm(-1);       // $src0_sel
1230 
1231   if (Src1Reg) {
1232     MIB.addReg(Src1Reg) // $src1
1233        .addImm(0)       // $src1_neg
1234        .addImm(0)       // $src1_rel
1235        .addImm(0)       // $src1_abs
1236        .addImm(-1);      // $src1_sel
1237   }
1238 
1239   //XXX: The r600g finalizer expects this to be 1, once we've moved the
1240   //scheduling to the backend, we can change the default to 0.
1241   MIB.addImm(1)        // $last
1242       .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
1243       .addImm(0)         // $literal
1244       .addImm(0);        // $bank_swizzle
1245 
1246   return MIB;
1247 }
1248 
1249 #define OPERAND_CASE(Label) \
1250   case Label: { \
1251     static const unsigned Ops[] = \
1252     { \
1253       Label##_X, \
1254       Label##_Y, \
1255       Label##_Z, \
1256       Label##_W \
1257     }; \
1258     return Ops[Slot]; \
1259   }
1260 
1261 static unsigned getSlotedOps(unsigned  Op, unsigned Slot) {
1262   switch (Op) {
1263   OPERAND_CASE(AMDGPU::OpName::update_exec_mask)
1264   OPERAND_CASE(AMDGPU::OpName::update_pred)
1265   OPERAND_CASE(AMDGPU::OpName::write)
1266   OPERAND_CASE(AMDGPU::OpName::omod)
1267   OPERAND_CASE(AMDGPU::OpName::dst_rel)
1268   OPERAND_CASE(AMDGPU::OpName::clamp)
1269   OPERAND_CASE(AMDGPU::OpName::src0)
1270   OPERAND_CASE(AMDGPU::OpName::src0_neg)
1271   OPERAND_CASE(AMDGPU::OpName::src0_rel)
1272   OPERAND_CASE(AMDGPU::OpName::src0_abs)
1273   OPERAND_CASE(AMDGPU::OpName::src0_sel)
1274   OPERAND_CASE(AMDGPU::OpName::src1)
1275   OPERAND_CASE(AMDGPU::OpName::src1_neg)
1276   OPERAND_CASE(AMDGPU::OpName::src1_rel)
1277   OPERAND_CASE(AMDGPU::OpName::src1_abs)
1278   OPERAND_CASE(AMDGPU::OpName::src1_sel)
1279   OPERAND_CASE(AMDGPU::OpName::pred_sel)
1280   default:
1281     llvm_unreachable("Wrong Operand");
1282   }
1283 }
1284 
1285 #undef OPERAND_CASE
1286 
1287 MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction(
1288     MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg)
1289     const {
1290   assert (MI->getOpcode() == AMDGPU::DOT_4 && "Not Implemented");
1291   unsigned Opcode;
1292   if (ST.getGeneration() <= AMDGPUSubtarget::R700)
1293     Opcode = AMDGPU::DOT4_r600;
1294   else
1295     Opcode = AMDGPU::DOT4_eg;
1296   MachineBasicBlock::iterator I = MI;
1297   MachineOperand &Src0 = MI->getOperand(
1298       getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot)));
1299   MachineOperand &Src1 = MI->getOperand(
1300       getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot)));
1301   MachineInstr *MIB = buildDefaultInstruction(
1302       MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
1303   static const unsigned  Operands[14] = {
1304     AMDGPU::OpName::update_exec_mask,
1305     AMDGPU::OpName::update_pred,
1306     AMDGPU::OpName::write,
1307     AMDGPU::OpName::omod,
1308     AMDGPU::OpName::dst_rel,
1309     AMDGPU::OpName::clamp,
1310     AMDGPU::OpName::src0_neg,
1311     AMDGPU::OpName::src0_rel,
1312     AMDGPU::OpName::src0_abs,
1313     AMDGPU::OpName::src0_sel,
1314     AMDGPU::OpName::src1_neg,
1315     AMDGPU::OpName::src1_rel,
1316     AMDGPU::OpName::src1_abs,
1317     AMDGPU::OpName::src1_sel,
1318   };
1319 
1320   MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
1321       getSlotedOps(AMDGPU::OpName::pred_sel, Slot)));
1322   MIB->getOperand(getOperandIdx(Opcode, AMDGPU::OpName::pred_sel))
1323       .setReg(MO.getReg());
1324 
1325   for (unsigned i = 0; i < 14; i++) {
1326     MachineOperand &MO = MI->getOperand(
1327         getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
1328     assert (MO.isImm());
1329     setImmOperand(MIB, Operands[i], MO.getImm());
1330   }
1331   MIB->getOperand(20).setImm(0);
1332   return MIB;
1333 }
1334 
1335 MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
1336                                          MachineBasicBlock::iterator I,
1337                                          unsigned DstReg,
1338                                          uint64_t Imm) const {
1339   MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
1340                                                   AMDGPU::ALU_LITERAL_X);
1341   setImmOperand(MovImm, AMDGPU::OpName::literal, Imm);
1342   return MovImm;
1343 }
1344 
1345 MachineInstr *R600InstrInfo::buildMovInstr(MachineBasicBlock *MBB,
1346                                        MachineBasicBlock::iterator I,
1347                                        unsigned DstReg, unsigned SrcReg) const {
1348   return buildDefaultInstruction(*MBB, I, AMDGPU::MOV, DstReg, SrcReg);
1349 }
1350 
1351 int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const {
1352   return getOperandIdx(MI.getOpcode(), Op);
1353 }
1354 
1355 int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const {
1356   return AMDGPU::getNamedOperandIdx(Opcode, Op);
1357 }
1358 
1359 void R600InstrInfo::setImmOperand(MachineInstr *MI, unsigned Op,
1360                                   int64_t Imm) const {
1361   int Idx = getOperandIdx(*MI, Op);
1362   assert(Idx != -1 && "Operand not supported for this instruction.");
1363   assert(MI->getOperand(Idx).isImm());
1364   MI->getOperand(Idx).setImm(Imm);
1365 }
1366 
1367 //===----------------------------------------------------------------------===//
1368 // Instruction flag getters/setters
1369 //===----------------------------------------------------------------------===//
1370 
1371 bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const {
1372   return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
1373 }
1374 
1375 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr *MI, unsigned SrcIdx,
1376                                          unsigned Flag) const {
1377   unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1378   int FlagIndex = 0;
1379   if (Flag != 0) {
1380     // If we pass something other than the default value of Flag to this
1381     // function, it means we are want to set a flag on an instruction
1382     // that uses native encoding.
1383     assert(HAS_NATIVE_OPERANDS(TargetFlags));
1384     bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3;
1385     switch (Flag) {
1386     case MO_FLAG_CLAMP:
1387       FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::clamp);
1388       break;
1389     case MO_FLAG_MASK:
1390       FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::write);
1391       break;
1392     case MO_FLAG_NOT_LAST:
1393     case MO_FLAG_LAST:
1394       FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::last);
1395       break;
1396     case MO_FLAG_NEG:
1397       switch (SrcIdx) {
1398       case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_neg); break;
1399       case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_neg); break;
1400       case 2: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src2_neg); break;
1401       }
1402       break;
1403 
1404     case MO_FLAG_ABS:
1405       assert(!IsOP3 && "Cannot set absolute value modifier for OP3 "
1406                        "instructions.");
1407       (void)IsOP3;
1408       switch (SrcIdx) {
1409       case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_abs); break;
1410       case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_abs); break;
1411       }
1412       break;
1413 
1414     default:
1415       FlagIndex = -1;
1416       break;
1417     }
1418     assert(FlagIndex != -1 && "Flag not supported for this instruction");
1419   } else {
1420       FlagIndex = GET_FLAG_OPERAND_IDX(TargetFlags);
1421       assert(FlagIndex != 0 &&
1422          "Instruction flags not supported for this instruction");
1423   }
1424 
1425   MachineOperand &FlagOp = MI->getOperand(FlagIndex);
1426   assert(FlagOp.isImm());
1427   return FlagOp;
1428 }
1429 
1430 void R600InstrInfo::addFlag(MachineInstr *MI, unsigned Operand,
1431                             unsigned Flag) const {
1432   unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1433   if (Flag == 0) {
1434     return;
1435   }
1436   if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1437     MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1438     if (Flag == MO_FLAG_NOT_LAST) {
1439       clearFlag(MI, Operand, MO_FLAG_LAST);
1440     } else if (Flag == MO_FLAG_MASK) {
1441       clearFlag(MI, Operand, Flag);
1442     } else {
1443       FlagOp.setImm(1);
1444     }
1445   } else {
1446       MachineOperand &FlagOp = getFlagOp(MI, Operand);
1447       FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
1448   }
1449 }
1450 
1451 void R600InstrInfo::clearFlag(MachineInstr *MI, unsigned Operand,
1452                               unsigned Flag) const {
1453   unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1454   if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1455     MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1456     FlagOp.setImm(0);
1457   } else {
1458     MachineOperand &FlagOp = getFlagOp(MI);
1459     unsigned InstFlags = FlagOp.getImm();
1460     InstFlags &= ~(Flag << (NUM_MO_FLAGS * Operand));
1461     FlagOp.setImm(InstFlags);
1462   }
1463 }
1464 
1465 bool R600InstrInfo::isRegisterStore(const MachineInstr &MI) const {
1466   return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE;
1467 }
1468 
1469 bool R600InstrInfo::isRegisterLoad(const MachineInstr &MI) const {
1470   return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;
1471 }
1472