1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Custom DAG lowering for R600
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "R600ISelLowering.h"
16 #include "AMDGPUFrameLowering.h"
17 #include "AMDGPUIntrinsicInfo.h"
18 #include "AMDGPUSubtarget.h"
19 #include "R600Defines.h"
20 #include "R600FrameLowering.h"
21 #include "R600InstrInfo.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "Utils/AMDGPUBaseInfo.h"
24 #include "llvm/ADT/APFloat.h"
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/CodeGen/CallingConvLower.h"
30 #include "llvm/CodeGen/DAGCombine.h"
31 #include "llvm/CodeGen/ISDOpcodes.h"
32 #include "llvm/CodeGen/MachineBasicBlock.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstr.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineMemOperand.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/MachineValueType.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/Support/Casting.h"
43 #include "llvm/Support/Compiler.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include <cassert>
46 #include <cstdint>
47 #include <iterator>
48 #include <utility>
49 #include <vector>
50 
51 using namespace llvm;
52 
53 R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
54                                        const R600Subtarget &STI)
55     : AMDGPUTargetLowering(TM, STI), Gen(STI.getGeneration()) {
56   addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
57   addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
58   addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
59   addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
60   addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
61   addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
62 
63   computeRegisterProperties(STI.getRegisterInfo());
64 
65   // Legalize loads and stores to the private address space.
66   setOperationAction(ISD::LOAD, MVT::i32, Custom);
67   setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
68   setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
69 
70   // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address
71   // spaces, so it is custom lowered to handle those where it isn't.
72   for (MVT VT : MVT::integer_valuetypes()) {
73     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
74     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom);
75     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Custom);
76 
77     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
78     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom);
79     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom);
80 
81     setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
82     setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom);
83     setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom);
84   }
85 
86   // Workaround for LegalizeDAG asserting on expansion of i1 vector loads.
87   setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, MVT::v2i1, Expand);
88   setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, MVT::v2i1, Expand);
89   setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, MVT::v2i1, Expand);
90 
91   setLoadExtAction(ISD::EXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
92   setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
93   setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
94 
95   setOperationAction(ISD::STORE, MVT::i8, Custom);
96   setOperationAction(ISD::STORE, MVT::i32, Custom);
97   setOperationAction(ISD::STORE, MVT::v2i32, Custom);
98   setOperationAction(ISD::STORE, MVT::v4i32, Custom);
99 
100   setTruncStoreAction(MVT::i32, MVT::i8, Custom);
101   setTruncStoreAction(MVT::i32, MVT::i16, Custom);
102 
103   // Workaround for LegalizeDAG asserting on expansion of i1 vector stores.
104   setTruncStoreAction(MVT::v2i32, MVT::v2i1, Expand);
105   setTruncStoreAction(MVT::v4i32, MVT::v4i1, Expand);
106 
107   // Set condition code actions
108   setCondCodeAction(ISD::SETO,   MVT::f32, Expand);
109   setCondCodeAction(ISD::SETUO,  MVT::f32, Expand);
110   setCondCodeAction(ISD::SETLT,  MVT::f32, Expand);
111   setCondCodeAction(ISD::SETLE,  MVT::f32, Expand);
112   setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
113   setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
114   setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
115   setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
116   setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
117   setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
118   setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
119   setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
120 
121   setCondCodeAction(ISD::SETLE, MVT::i32, Expand);
122   setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
123   setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
124   setCondCodeAction(ISD::SETULT, MVT::i32, Expand);
125 
126   setOperationAction(ISD::FCOS, MVT::f32, Custom);
127   setOperationAction(ISD::FSIN, MVT::f32, Custom);
128 
129   setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
130   setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
131 
132   setOperationAction(ISD::BR_CC, MVT::i32, Expand);
133   setOperationAction(ISD::BR_CC, MVT::f32, Expand);
134   setOperationAction(ISD::BRCOND, MVT::Other, Custom);
135 
136   setOperationAction(ISD::FSUB, MVT::f32, Expand);
137 
138   setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
139   setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
140 
141   setOperationAction(ISD::SETCC, MVT::i32, Expand);
142   setOperationAction(ISD::SETCC, MVT::f32, Expand);
143   setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
144   setOperationAction(ISD::FP_TO_SINT, MVT::i1, Custom);
145   setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
146   setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
147 
148   setOperationAction(ISD::SELECT, MVT::i32, Expand);
149   setOperationAction(ISD::SELECT, MVT::f32, Expand);
150   setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
151   setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
152 
153   // ADD, SUB overflow.
154   // TODO: turn these into Legal?
155   if (Subtarget->hasCARRY())
156     setOperationAction(ISD::UADDO, MVT::i32, Custom);
157 
158   if (Subtarget->hasBORROW())
159     setOperationAction(ISD::USUBO, MVT::i32, Custom);
160 
161   // Expand sign extension of vectors
162   if (!Subtarget->hasBFE())
163     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
164 
165   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand);
166   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand);
167 
168   if (!Subtarget->hasBFE())
169     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
170   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand);
171   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand);
172 
173   if (!Subtarget->hasBFE())
174     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
175   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand);
176   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
177 
178   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
179   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand);
180   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
181 
182   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
183 
184   setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
185 
186   setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom);
187   setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom);
188   setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
189   setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
190 
191   setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom);
192   setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom);
193   setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
194   setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
195 
196   // We don't have 64-bit shifts. Thus we need either SHX i64 or SHX_PARTS i32
197   //  to be Legal/Custom in order to avoid library calls.
198   setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
199   setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
200   setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
201 
202   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
203 
204   const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
205   for (MVT VT : ScalarIntVTs) {
206     setOperationAction(ISD::ADDC, VT, Expand);
207     setOperationAction(ISD::SUBC, VT, Expand);
208     setOperationAction(ISD::ADDE, VT, Expand);
209     setOperationAction(ISD::SUBE, VT, Expand);
210   }
211 
212   setSchedulingPreference(Sched::Source);
213 
214   setTargetDAGCombine(ISD::FP_ROUND);
215   setTargetDAGCombine(ISD::FP_TO_SINT);
216   setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
217   setTargetDAGCombine(ISD::SELECT_CC);
218   setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
219   setTargetDAGCombine(ISD::LOAD);
220 }
221 
222 const R600Subtarget *R600TargetLowering::getSubtarget() const {
223   return static_cast<const R600Subtarget *>(Subtarget);
224 }
225 
226 static inline bool isEOP(MachineBasicBlock::iterator I) {
227   if (std::next(I) == I->getParent()->end())
228     return false;
229   return std::next(I)->getOpcode() == AMDGPU::RETURN;
230 }
231 
232 MachineBasicBlock *
233 R600TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
234                                                 MachineBasicBlock *BB) const {
235   MachineFunction *MF = BB->getParent();
236   MachineRegisterInfo &MRI = MF->getRegInfo();
237   MachineBasicBlock::iterator I = MI;
238   const R600InstrInfo *TII = getSubtarget()->getInstrInfo();
239 
240   switch (MI.getOpcode()) {
241   default:
242     // Replace LDS_*_RET instruction that don't have any uses with the
243     // equivalent LDS_*_NORET instruction.
244     if (TII->isLDSRetInstr(MI.getOpcode())) {
245       int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst);
246       assert(DstIdx != -1);
247       MachineInstrBuilder NewMI;
248       // FIXME: getLDSNoRetOp method only handles LDS_1A1D LDS ops. Add
249       //        LDS_1A2D support and remove this special case.
250       if (!MRI.use_empty(MI.getOperand(DstIdx).getReg()) ||
251           MI.getOpcode() == AMDGPU::LDS_CMPST_RET)
252         return BB;
253 
254       NewMI = BuildMI(*BB, I, BB->findDebugLoc(I),
255                       TII->get(AMDGPU::getLDSNoRetOp(MI.getOpcode())));
256       for (unsigned i = 1, e = MI.getNumOperands(); i < e; ++i) {
257         NewMI.addOperand(MI.getOperand(i));
258       }
259     } else {
260       return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
261     }
262     break;
263   case AMDGPU::CLAMP_R600: {
264     MachineInstr *NewMI = TII->buildDefaultInstruction(
265         *BB, I, AMDGPU::MOV, MI.getOperand(0).getReg(),
266         MI.getOperand(1).getReg());
267     TII->addFlag(*NewMI, 0, MO_FLAG_CLAMP);
268     break;
269   }
270 
271   case AMDGPU::FABS_R600: {
272     MachineInstr *NewMI = TII->buildDefaultInstruction(
273         *BB, I, AMDGPU::MOV, MI.getOperand(0).getReg(),
274         MI.getOperand(1).getReg());
275     TII->addFlag(*NewMI, 0, MO_FLAG_ABS);
276     break;
277   }
278 
279   case AMDGPU::FNEG_R600: {
280     MachineInstr *NewMI = TII->buildDefaultInstruction(
281         *BB, I, AMDGPU::MOV, MI.getOperand(0).getReg(),
282         MI.getOperand(1).getReg());
283     TII->addFlag(*NewMI, 0, MO_FLAG_NEG);
284     break;
285   }
286 
287   case AMDGPU::MASK_WRITE: {
288     unsigned maskedRegister = MI.getOperand(0).getReg();
289     assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
290     MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
291     TII->addFlag(*defInstr, 0, MO_FLAG_MASK);
292     break;
293   }
294 
295   case AMDGPU::MOV_IMM_F32:
296     TII->buildMovImm(*BB, I, MI.getOperand(0).getReg(), MI.getOperand(1)
297                                                             .getFPImm()
298                                                             ->getValueAPF()
299                                                             .bitcastToAPInt()
300                                                             .getZExtValue());
301     break;
302 
303   case AMDGPU::MOV_IMM_I32:
304     TII->buildMovImm(*BB, I, MI.getOperand(0).getReg(),
305                      MI.getOperand(1).getImm());
306     break;
307 
308   case AMDGPU::MOV_IMM_GLOBAL_ADDR: {
309     //TODO: Perhaps combine this instruction with the next if possible
310     auto MIB = TII->buildDefaultInstruction(
311         *BB, MI, AMDGPU::MOV, MI.getOperand(0).getReg(), AMDGPU::ALU_LITERAL_X);
312     int Idx = TII->getOperandIdx(*MIB, AMDGPU::OpName::literal);
313     //TODO: Ugh this is rather ugly
314     MIB->getOperand(Idx) = MI.getOperand(1);
315     break;
316   }
317 
318   case AMDGPU::CONST_COPY: {
319     MachineInstr *NewMI = TII->buildDefaultInstruction(
320         *BB, MI, AMDGPU::MOV, MI.getOperand(0).getReg(), AMDGPU::ALU_CONST);
321     TII->setImmOperand(*NewMI, AMDGPU::OpName::src0_sel,
322                        MI.getOperand(1).getImm());
323     break;
324   }
325 
326   case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
327   case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
328   case AMDGPU::RAT_WRITE_CACHELESS_128_eg:
329     BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode()))
330         .addOperand(MI.getOperand(0))
331         .addOperand(MI.getOperand(1))
332         .addImm(isEOP(I)); // Set End of program bit
333     break;
334 
335   case AMDGPU::RAT_STORE_TYPED_eg:
336     BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode()))
337         .addOperand(MI.getOperand(0))
338         .addOperand(MI.getOperand(1))
339         .addOperand(MI.getOperand(2))
340         .addImm(isEOP(I)); // Set End of program bit
341     break;
342 
343   case AMDGPU::BRANCH:
344     BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
345         .addOperand(MI.getOperand(0));
346     break;
347 
348   case AMDGPU::BRANCH_COND_f32: {
349     MachineInstr *NewMI =
350         BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
351                 AMDGPU::PREDICATE_BIT)
352             .addOperand(MI.getOperand(1))
353             .addImm(AMDGPU::PRED_SETNE)
354             .addImm(0); // Flags
355     TII->addFlag(*NewMI, 0, MO_FLAG_PUSH);
356     BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
357         .addOperand(MI.getOperand(0))
358         .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
359     break;
360   }
361 
362   case AMDGPU::BRANCH_COND_i32: {
363     MachineInstr *NewMI =
364         BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
365                 AMDGPU::PREDICATE_BIT)
366             .addOperand(MI.getOperand(1))
367             .addImm(AMDGPU::PRED_SETNE_INT)
368             .addImm(0); // Flags
369     TII->addFlag(*NewMI, 0, MO_FLAG_PUSH);
370     BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
371         .addOperand(MI.getOperand(0))
372         .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
373     break;
374   }
375 
376   case AMDGPU::EG_ExportSwz:
377   case AMDGPU::R600_ExportSwz: {
378     // Instruction is left unmodified if its not the last one of its type
379     bool isLastInstructionOfItsType = true;
380     unsigned InstExportType = MI.getOperand(1).getImm();
381     for (MachineBasicBlock::iterator NextExportInst = std::next(I),
382          EndBlock = BB->end(); NextExportInst != EndBlock;
383          NextExportInst = std::next(NextExportInst)) {
384       if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
385           NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
386         unsigned CurrentInstExportType = NextExportInst->getOperand(1)
387             .getImm();
388         if (CurrentInstExportType == InstExportType) {
389           isLastInstructionOfItsType = false;
390           break;
391         }
392       }
393     }
394     bool EOP = isEOP(I);
395     if (!EOP && !isLastInstructionOfItsType)
396       return BB;
397     unsigned CfInst = (MI.getOpcode() == AMDGPU::EG_ExportSwz) ? 84 : 40;
398     BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode()))
399         .addOperand(MI.getOperand(0))
400         .addOperand(MI.getOperand(1))
401         .addOperand(MI.getOperand(2))
402         .addOperand(MI.getOperand(3))
403         .addOperand(MI.getOperand(4))
404         .addOperand(MI.getOperand(5))
405         .addOperand(MI.getOperand(6))
406         .addImm(CfInst)
407         .addImm(EOP);
408     break;
409   }
410   case AMDGPU::RETURN: {
411     return BB;
412   }
413   }
414 
415   MI.eraseFromParent();
416   return BB;
417 }
418 
419 //===----------------------------------------------------------------------===//
420 // Custom DAG Lowering Operations
421 //===----------------------------------------------------------------------===//
422 
423 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
424   MachineFunction &MF = DAG.getMachineFunction();
425   R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
426   switch (Op.getOpcode()) {
427   default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
428   case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
429   case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
430   case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
431   case ISD::SRA_PARTS:
432   case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
433   case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY);
434   case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW);
435   case ISD::FCOS:
436   case ISD::FSIN: return LowerTrig(Op, DAG);
437   case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
438   case ISD::STORE: return LowerSTORE(Op, DAG);
439   case ISD::LOAD: {
440     SDValue Result = LowerLOAD(Op, DAG);
441     assert((!Result.getNode() ||
442             Result.getNode()->getNumValues() == 2) &&
443            "Load should return a value and a chain");
444     return Result;
445   }
446 
447   case ISD::BRCOND: return LowerBRCOND(Op, DAG);
448   case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
449   case ISD::FrameIndex: return lowerFrameIndex(Op, DAG);
450   case ISD::INTRINSIC_VOID: {
451     SDValue Chain = Op.getOperand(0);
452     unsigned IntrinsicID =
453                          cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
454     switch (IntrinsicID) {
455     case AMDGPUIntrinsic::r600_store_swizzle: {
456       SDLoc DL(Op);
457       const SDValue Args[8] = {
458         Chain,
459         Op.getOperand(2), // Export Value
460         Op.getOperand(3), // ArrayBase
461         Op.getOperand(4), // Type
462         DAG.getConstant(0, DL, MVT::i32), // SWZ_X
463         DAG.getConstant(1, DL, MVT::i32), // SWZ_Y
464         DAG.getConstant(2, DL, MVT::i32), // SWZ_Z
465         DAG.getConstant(3, DL, MVT::i32) // SWZ_W
466       };
467       return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, Op.getValueType(), Args);
468     }
469 
470     // default for switch(IntrinsicID)
471     default: break;
472     }
473     // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
474     break;
475   }
476   case ISD::INTRINSIC_WO_CHAIN: {
477     unsigned IntrinsicID =
478                          cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
479     EVT VT = Op.getValueType();
480     SDLoc DL(Op);
481     switch(IntrinsicID) {
482     default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
483     case AMDGPUIntrinsic::r600_tex:
484     case AMDGPUIntrinsic::r600_texc: {
485       unsigned TextureOp;
486       switch (IntrinsicID) {
487       case AMDGPUIntrinsic::r600_tex:
488         TextureOp = 0;
489         break;
490       case AMDGPUIntrinsic::r600_texc:
491         TextureOp = 1;
492         break;
493       default:
494         llvm_unreachable("unhandled texture operation");
495       }
496 
497       SDValue TexArgs[19] = {
498         DAG.getConstant(TextureOp, DL, MVT::i32),
499         Op.getOperand(1),
500         DAG.getConstant(0, DL, MVT::i32),
501         DAG.getConstant(1, DL, MVT::i32),
502         DAG.getConstant(2, DL, MVT::i32),
503         DAG.getConstant(3, DL, MVT::i32),
504         Op.getOperand(2),
505         Op.getOperand(3),
506         Op.getOperand(4),
507         DAG.getConstant(0, DL, MVT::i32),
508         DAG.getConstant(1, DL, MVT::i32),
509         DAG.getConstant(2, DL, MVT::i32),
510         DAG.getConstant(3, DL, MVT::i32),
511         Op.getOperand(5),
512         Op.getOperand(6),
513         Op.getOperand(7),
514         Op.getOperand(8),
515         Op.getOperand(9),
516         Op.getOperand(10)
517       };
518       return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
519     }
520     case AMDGPUIntrinsic::r600_dot4: {
521       SDValue Args[8] = {
522       DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
523           DAG.getConstant(0, DL, MVT::i32)),
524       DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
525           DAG.getConstant(0, DL, MVT::i32)),
526       DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
527           DAG.getConstant(1, DL, MVT::i32)),
528       DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
529           DAG.getConstant(1, DL, MVT::i32)),
530       DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
531           DAG.getConstant(2, DL, MVT::i32)),
532       DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
533           DAG.getConstant(2, DL, MVT::i32)),
534       DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
535           DAG.getConstant(3, DL, MVT::i32)),
536       DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
537           DAG.getConstant(3, DL, MVT::i32))
538       };
539       return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args);
540     }
541 
542     case Intrinsic::r600_implicitarg_ptr: {
543       MVT PtrVT = getPointerTy(DAG.getDataLayout(), AMDGPUAS::PARAM_I_ADDRESS);
544       uint32_t ByteOffset = getImplicitParameterOffset(MFI, FIRST_IMPLICIT);
545       return DAG.getConstant(ByteOffset, DL, PtrVT);
546     }
547     case Intrinsic::r600_read_ngroups_x:
548       return LowerImplicitParameter(DAG, VT, DL, 0);
549     case Intrinsic::r600_read_ngroups_y:
550       return LowerImplicitParameter(DAG, VT, DL, 1);
551     case Intrinsic::r600_read_ngroups_z:
552       return LowerImplicitParameter(DAG, VT, DL, 2);
553     case Intrinsic::r600_read_global_size_x:
554       return LowerImplicitParameter(DAG, VT, DL, 3);
555     case Intrinsic::r600_read_global_size_y:
556       return LowerImplicitParameter(DAG, VT, DL, 4);
557     case Intrinsic::r600_read_global_size_z:
558       return LowerImplicitParameter(DAG, VT, DL, 5);
559     case Intrinsic::r600_read_local_size_x:
560       return LowerImplicitParameter(DAG, VT, DL, 6);
561     case Intrinsic::r600_read_local_size_y:
562       return LowerImplicitParameter(DAG, VT, DL, 7);
563     case Intrinsic::r600_read_local_size_z:
564       return LowerImplicitParameter(DAG, VT, DL, 8);
565 
566     case Intrinsic::r600_read_tgid_x:
567       return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
568                                   AMDGPU::T1_X, VT);
569     case Intrinsic::r600_read_tgid_y:
570       return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
571                                   AMDGPU::T1_Y, VT);
572     case Intrinsic::r600_read_tgid_z:
573       return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
574                                   AMDGPU::T1_Z, VT);
575     case Intrinsic::r600_read_tidig_x:
576       return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
577                                   AMDGPU::T0_X, VT);
578     case Intrinsic::r600_read_tidig_y:
579       return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
580                                   AMDGPU::T0_Y, VT);
581     case Intrinsic::r600_read_tidig_z:
582       return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
583                                   AMDGPU::T0_Z, VT);
584 
585     case Intrinsic::r600_recipsqrt_ieee:
586       return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
587 
588     case Intrinsic::r600_recipsqrt_clamped:
589       return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1));
590     }
591 
592     // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
593     break;
594   }
595   } // end switch(Op.getOpcode())
596   return SDValue();
597 }
598 
599 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
600                                             SmallVectorImpl<SDValue> &Results,
601                                             SelectionDAG &DAG) const {
602   switch (N->getOpcode()) {
603   default:
604     AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG);
605     return;
606   case ISD::FP_TO_UINT:
607     if (N->getValueType(0) == MVT::i1) {
608       Results.push_back(lowerFP_TO_UINT(N->getOperand(0), DAG));
609       return;
610     }
611     // Since we don't care about out of bounds values we can use FP_TO_SINT for
612     // uints too. The DAGLegalizer code for uint considers some extra cases
613     // which are not necessary here.
614     LLVM_FALLTHROUGH;
615   case ISD::FP_TO_SINT: {
616     if (N->getValueType(0) == MVT::i1) {
617       Results.push_back(lowerFP_TO_SINT(N->getOperand(0), DAG));
618       return;
619     }
620 
621     SDValue Result;
622     if (expandFP_TO_SINT(N, Result, DAG))
623       Results.push_back(Result);
624     return;
625   }
626   case ISD::SDIVREM: {
627     SDValue Op = SDValue(N, 1);
628     SDValue RES = LowerSDIVREM(Op, DAG);
629     Results.push_back(RES);
630     Results.push_back(RES.getValue(1));
631     break;
632   }
633   case ISD::UDIVREM: {
634     SDValue Op = SDValue(N, 0);
635     LowerUDIVREM64(Op, DAG, Results);
636     break;
637   }
638   }
639 }
640 
641 SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG,
642                                                    SDValue Vector) const {
643   SDLoc DL(Vector);
644   EVT VecVT = Vector.getValueType();
645   EVT EltVT = VecVT.getVectorElementType();
646   SmallVector<SDValue, 8> Args;
647 
648   for (unsigned i = 0, e = VecVT.getVectorNumElements(); i != e; ++i) {
649     Args.push_back(DAG.getNode(
650         ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vector,
651         DAG.getConstant(i, DL, getVectorIdxTy(DAG.getDataLayout()))));
652   }
653 
654   return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args);
655 }
656 
657 SDValue R600TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
658                                                     SelectionDAG &DAG) const {
659   SDLoc DL(Op);
660   SDValue Vector = Op.getOperand(0);
661   SDValue Index = Op.getOperand(1);
662 
663   if (isa<ConstantSDNode>(Index) ||
664       Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
665     return Op;
666 
667   Vector = vectorToVerticalVector(DAG, Vector);
668   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(),
669                      Vector, Index);
670 }
671 
672 SDValue R600TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
673                                                    SelectionDAG &DAG) const {
674   SDLoc DL(Op);
675   SDValue Vector = Op.getOperand(0);
676   SDValue Value = Op.getOperand(1);
677   SDValue Index = Op.getOperand(2);
678 
679   if (isa<ConstantSDNode>(Index) ||
680       Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
681     return Op;
682 
683   Vector = vectorToVerticalVector(DAG, Vector);
684   SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(),
685                                Vector, Value, Index);
686   return vectorToVerticalVector(DAG, Insert);
687 }
688 
689 SDValue R600TargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
690                                                SDValue Op,
691                                                SelectionDAG &DAG) const {
692   GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
693   if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
694     return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
695 
696   const DataLayout &DL = DAG.getDataLayout();
697   const GlobalValue *GV = GSD->getGlobal();
698   MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
699 
700   SDValue GA = DAG.getTargetGlobalAddress(GV, SDLoc(GSD), ConstPtrVT);
701   return DAG.getNode(AMDGPUISD::CONST_DATA_PTR, SDLoc(GSD), ConstPtrVT, GA);
702 }
703 
704 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
705   // On hw >= R700, COS/SIN input must be between -1. and 1.
706   // Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
707   EVT VT = Op.getValueType();
708   SDValue Arg = Op.getOperand(0);
709   SDLoc DL(Op);
710 
711   // TODO: Should this propagate fast-math-flags?
712   SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT,
713       DAG.getNode(ISD::FADD, DL, VT,
714         DAG.getNode(ISD::FMUL, DL, VT, Arg,
715           DAG.getConstantFP(0.15915494309, DL, MVT::f32)),
716         DAG.getConstantFP(0.5, DL, MVT::f32)));
717   unsigned TrigNode;
718   switch (Op.getOpcode()) {
719   case ISD::FCOS:
720     TrigNode = AMDGPUISD::COS_HW;
721     break;
722   case ISD::FSIN:
723     TrigNode = AMDGPUISD::SIN_HW;
724     break;
725   default:
726     llvm_unreachable("Wrong trig opcode");
727   }
728   SDValue TrigVal = DAG.getNode(TrigNode, DL, VT,
729       DAG.getNode(ISD::FADD, DL, VT, FractPart,
730         DAG.getConstantFP(-0.5, DL, MVT::f32)));
731   if (Gen >= R600Subtarget::R700)
732     return TrigVal;
733   // On R600 hw, COS/SIN input must be between -Pi and Pi.
734   return DAG.getNode(ISD::FMUL, DL, VT, TrigVal,
735       DAG.getConstantFP(3.14159265359, DL, MVT::f32));
736 }
737 
738 SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const {
739   SDLoc DL(Op);
740   EVT VT = Op.getValueType();
741 
742   SDValue Lo = Op.getOperand(0);
743   SDValue Hi = Op.getOperand(1);
744   SDValue Shift = Op.getOperand(2);
745   SDValue Zero = DAG.getConstant(0, DL, VT);
746   SDValue One  = DAG.getConstant(1, DL, VT);
747 
748   SDValue Width  = DAG.getConstant(VT.getSizeInBits(), DL, VT);
749   SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT);
750   SDValue BigShift  = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
751   SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
752 
753   // The dance around Width1 is necessary for 0 special case.
754   // Without it the CompShift might be 32, producing incorrect results in
755   // Overflow. So we do the shift in two steps, the alternative is to
756   // add a conditional to filter the special case.
757 
758   SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift);
759   Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One);
760 
761   SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift);
762   HiSmall = DAG.getNode(ISD::OR, DL, VT, HiSmall, Overflow);
763   SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift);
764 
765   SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift);
766   SDValue LoBig = Zero;
767 
768   Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
769   Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
770 
771   return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
772 }
773 
774 SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const {
775   SDLoc DL(Op);
776   EVT VT = Op.getValueType();
777 
778   SDValue Lo = Op.getOperand(0);
779   SDValue Hi = Op.getOperand(1);
780   SDValue Shift = Op.getOperand(2);
781   SDValue Zero = DAG.getConstant(0, DL, VT);
782   SDValue One  = DAG.getConstant(1, DL, VT);
783 
784   const bool SRA = Op.getOpcode() == ISD::SRA_PARTS;
785 
786   SDValue Width  = DAG.getConstant(VT.getSizeInBits(), DL, VT);
787   SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT);
788   SDValue BigShift  = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
789   SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
790 
791   // The dance around Width1 is necessary for 0 special case.
792   // Without it the CompShift might be 32, producing incorrect results in
793   // Overflow. So we do the shift in two steps, the alternative is to
794   // add a conditional to filter the special case.
795 
796   SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift);
797   Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One);
798 
799   SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift);
800   SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift);
801   LoSmall = DAG.getNode(ISD::OR, DL, VT, LoSmall, Overflow);
802 
803   SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift);
804   SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero;
805 
806   Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
807   Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
808 
809   return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
810 }
811 
812 SDValue R600TargetLowering::LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
813                                           unsigned mainop, unsigned ovf) const {
814   SDLoc DL(Op);
815   EVT VT = Op.getValueType();
816 
817   SDValue Lo = Op.getOperand(0);
818   SDValue Hi = Op.getOperand(1);
819 
820   SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi);
821   // Extend sign.
822   OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF,
823                     DAG.getValueType(MVT::i1));
824 
825   SDValue Res = DAG.getNode(mainop, DL, VT, Lo, Hi);
826 
827   return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF);
828 }
829 
830 SDValue R600TargetLowering::lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const {
831   SDLoc DL(Op);
832   return DAG.getNode(
833       ISD::SETCC,
834       DL,
835       MVT::i1,
836       Op, DAG.getConstantFP(1.0f, DL, MVT::f32),
837       DAG.getCondCode(ISD::SETEQ));
838 }
839 
840 SDValue R600TargetLowering::lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const {
841   SDLoc DL(Op);
842   return DAG.getNode(
843       ISD::SETCC,
844       DL,
845       MVT::i1,
846       Op, DAG.getConstantFP(-1.0f, DL, MVT::f32),
847       DAG.getCondCode(ISD::SETEQ));
848 }
849 
850 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
851                                                    const SDLoc &DL,
852                                                    unsigned DwordOffset) const {
853   unsigned ByteOffset = DwordOffset * 4;
854   PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
855                                       AMDGPUAS::CONSTANT_BUFFER_0);
856 
857   // We shouldn't be using an offset wider than 16-bits for implicit parameters.
858   assert(isInt<16>(ByteOffset));
859 
860   return DAG.getLoad(VT, DL, DAG.getEntryNode(),
861                      DAG.getConstant(ByteOffset, DL, MVT::i32), // PTR
862                      MachinePointerInfo(ConstantPointerNull::get(PtrType)));
863 }
864 
865 bool R600TargetLowering::isZero(SDValue Op) const {
866   if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
867     return Cst->isNullValue();
868   } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
869     return CstFP->isZero();
870   } else {
871     return false;
872   }
873 }
874 
875 bool R600TargetLowering::isHWTrueValue(SDValue Op) const {
876   if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
877     return CFP->isExactlyValue(1.0);
878   }
879   return isAllOnesConstant(Op);
880 }
881 
882 bool R600TargetLowering::isHWFalseValue(SDValue Op) const {
883   if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
884     return CFP->getValueAPF().isZero();
885   }
886   return isNullConstant(Op);
887 }
888 
889 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
890   SDLoc DL(Op);
891   EVT VT = Op.getValueType();
892 
893   SDValue LHS = Op.getOperand(0);
894   SDValue RHS = Op.getOperand(1);
895   SDValue True = Op.getOperand(2);
896   SDValue False = Op.getOperand(3);
897   SDValue CC = Op.getOperand(4);
898   SDValue Temp;
899 
900   if (VT == MVT::f32) {
901     DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
902     SDValue MinMax = CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
903     if (MinMax)
904       return MinMax;
905   }
906 
907   // LHS and RHS are guaranteed to be the same value type
908   EVT CompareVT = LHS.getValueType();
909 
910   // Check if we can lower this to a native operation.
911 
912   // Try to lower to a SET* instruction:
913   //
914   // SET* can match the following patterns:
915   //
916   // select_cc f32, f32, -1,  0, cc_supported
917   // select_cc f32, f32, 1.0f, 0.0f, cc_supported
918   // select_cc i32, i32, -1,  0, cc_supported
919   //
920 
921   // Move hardware True/False values to the correct operand.
922   ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
923   ISD::CondCode InverseCC =
924      ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
925   if (isHWTrueValue(False) && isHWFalseValue(True)) {
926     if (isCondCodeLegal(InverseCC, CompareVT.getSimpleVT())) {
927       std::swap(False, True);
928       CC = DAG.getCondCode(InverseCC);
929     } else {
930       ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InverseCC);
931       if (isCondCodeLegal(SwapInvCC, CompareVT.getSimpleVT())) {
932         std::swap(False, True);
933         std::swap(LHS, RHS);
934         CC = DAG.getCondCode(SwapInvCC);
935       }
936     }
937   }
938 
939   if (isHWTrueValue(True) && isHWFalseValue(False) &&
940       (CompareVT == VT || VT == MVT::i32)) {
941     // This can be matched by a SET* instruction.
942     return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
943   }
944 
945   // Try to lower to a CND* instruction:
946   //
947   // CND* can match the following patterns:
948   //
949   // select_cc f32, 0.0, f32, f32, cc_supported
950   // select_cc f32, 0.0, i32, i32, cc_supported
951   // select_cc i32, 0,   f32, f32, cc_supported
952   // select_cc i32, 0,   i32, i32, cc_supported
953   //
954 
955   // Try to move the zero value to the RHS
956   if (isZero(LHS)) {
957     ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
958     // Try swapping the operands
959     ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(CCOpcode);
960     if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
961       std::swap(LHS, RHS);
962       CC = DAG.getCondCode(CCSwapped);
963     } else {
964       // Try inverting the conditon and then swapping the operands
965       ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT.isInteger());
966       CCSwapped = ISD::getSetCCSwappedOperands(CCInv);
967       if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
968         std::swap(True, False);
969         std::swap(LHS, RHS);
970         CC = DAG.getCondCode(CCSwapped);
971       }
972     }
973   }
974   if (isZero(RHS)) {
975     SDValue Cond = LHS;
976     SDValue Zero = RHS;
977     ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
978     if (CompareVT != VT) {
979       // Bitcast True / False to the correct types.  This will end up being
980       // a nop, but it allows us to define only a single pattern in the
981       // .TD files for each CND* instruction rather than having to have
982       // one pattern for integer True/False and one for fp True/False
983       True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
984       False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
985     }
986 
987     switch (CCOpcode) {
988     case ISD::SETONE:
989     case ISD::SETUNE:
990     case ISD::SETNE:
991       CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
992       Temp = True;
993       True = False;
994       False = Temp;
995       break;
996     default:
997       break;
998     }
999     SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
1000         Cond, Zero,
1001         True, False,
1002         DAG.getCondCode(CCOpcode));
1003     return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
1004   }
1005 
1006   // If we make it this for it means we have no native instructions to handle
1007   // this SELECT_CC, so we must lower it.
1008   SDValue HWTrue, HWFalse;
1009 
1010   if (CompareVT == MVT::f32) {
1011     HWTrue = DAG.getConstantFP(1.0f, DL, CompareVT);
1012     HWFalse = DAG.getConstantFP(0.0f, DL, CompareVT);
1013   } else if (CompareVT == MVT::i32) {
1014     HWTrue = DAG.getConstant(-1, DL, CompareVT);
1015     HWFalse = DAG.getConstant(0, DL, CompareVT);
1016   }
1017   else {
1018     llvm_unreachable("Unhandled value type in LowerSELECT_CC");
1019   }
1020 
1021   // Lower this unsupported SELECT_CC into a combination of two supported
1022   // SELECT_CC operations.
1023   SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
1024 
1025   return DAG.getNode(ISD::SELECT_CC, DL, VT,
1026       Cond, HWFalse,
1027       True, False,
1028       DAG.getCondCode(ISD::SETNE));
1029 }
1030 
1031 /// LLVM generates byte-addressed pointers.  For indirect addressing, we need to
1032 /// convert these pointers to a register index.  Each register holds
1033 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
1034 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
1035 /// for indirect addressing.
1036 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
1037                                                unsigned StackWidth,
1038                                                SelectionDAG &DAG) const {
1039   unsigned SRLPad;
1040   switch(StackWidth) {
1041   case 1:
1042     SRLPad = 2;
1043     break;
1044   case 2:
1045     SRLPad = 3;
1046     break;
1047   case 4:
1048     SRLPad = 4;
1049     break;
1050   default: llvm_unreachable("Invalid stack width");
1051   }
1052 
1053   SDLoc DL(Ptr);
1054   return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr,
1055                      DAG.getConstant(SRLPad, DL, MVT::i32));
1056 }
1057 
1058 void R600TargetLowering::getStackAddress(unsigned StackWidth,
1059                                          unsigned ElemIdx,
1060                                          unsigned &Channel,
1061                                          unsigned &PtrIncr) const {
1062   switch (StackWidth) {
1063   default:
1064   case 1:
1065     Channel = 0;
1066     if (ElemIdx > 0) {
1067       PtrIncr = 1;
1068     } else {
1069       PtrIncr = 0;
1070     }
1071     break;
1072   case 2:
1073     Channel = ElemIdx % 2;
1074     if (ElemIdx == 2) {
1075       PtrIncr = 1;
1076     } else {
1077       PtrIncr = 0;
1078     }
1079     break;
1080   case 4:
1081     Channel = ElemIdx;
1082     PtrIncr = 0;
1083     break;
1084   }
1085 }
1086 
1087 SDValue R600TargetLowering::lowerPrivateTruncStore(StoreSDNode *Store,
1088                                                    SelectionDAG &DAG) const {
1089   SDLoc DL(Store);
1090 
1091   unsigned Mask = 0;
1092   if (Store->getMemoryVT() == MVT::i8) {
1093     Mask = 0xff;
1094   } else if (Store->getMemoryVT() == MVT::i16) {
1095     Mask = 0xffff;
1096   }
1097 
1098   SDValue Chain = Store->getChain();
1099   SDValue BasePtr = Store->getBasePtr();
1100   EVT MemVT = Store->getMemoryVT();
1101 
1102   SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1103                             DAG.getConstant(2, DL, MVT::i32));
1104   SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1105                             Chain, Ptr,
1106                             DAG.getTargetConstant(0, DL, MVT::i32));
1107 
1108   SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1109                                 DAG.getConstant(0x3, DL, MVT::i32));
1110 
1111   SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1112                                  DAG.getConstant(3, DL, MVT::i32));
1113 
1114   SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1115                                   Store->getValue());
1116 
1117   SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1118 
1119   SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1120                                      MaskedValue, ShiftAmt);
1121 
1122   SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32,
1123                                 DAG.getConstant(Mask, DL, MVT::i32),
1124                                 ShiftAmt);
1125   DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1126                         DAG.getConstant(0xffffffff, DL, MVT::i32));
1127   Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1128 
1129   SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1130   return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1131                      Chain, Value, Ptr,
1132                      DAG.getTargetConstant(0, DL, MVT::i32));
1133 }
1134 
1135 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1136   StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
1137   unsigned AS = StoreNode->getAddressSpace();
1138   SDValue Value = StoreNode->getValue();
1139   EVT ValueVT = Value.getValueType();
1140   EVT MemVT = StoreNode->getMemoryVT();
1141   unsigned Align = StoreNode->getAlignment();
1142 
1143   if ((AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::PRIVATE_ADDRESS) &&
1144       ValueVT.isVector()) {
1145     return SplitVectorStore(Op, DAG);
1146   }
1147 
1148   // Private AS needs special fixes
1149   if (Align < MemVT.getStoreSize() && (AS != AMDGPUAS::PRIVATE_ADDRESS) &&
1150       !allowsMisalignedMemoryAccesses(MemVT, AS, Align, nullptr)) {
1151     return expandUnalignedStore(StoreNode, DAG);
1152   }
1153 
1154   SDLoc DL(Op);
1155   SDValue Chain = StoreNode->getChain();
1156   SDValue Ptr = StoreNode->getBasePtr();
1157 
1158   if (AS == AMDGPUAS::GLOBAL_ADDRESS) {
1159     // It is beneficial to create MSKOR here instead of combiner to avoid
1160     // artificial dependencies introduced by RMW
1161     if (StoreNode->isTruncatingStore()) {
1162       EVT VT = Value.getValueType();
1163       assert(VT.bitsLE(MVT::i32));
1164       SDValue MaskConstant;
1165       if (MemVT == MVT::i8) {
1166         MaskConstant = DAG.getConstant(0xFF, DL, MVT::i32);
1167       } else {
1168         assert(MemVT == MVT::i16);
1169         assert(StoreNode->getAlignment() >= 2);
1170         MaskConstant = DAG.getConstant(0xFFFF, DL, MVT::i32);
1171       }
1172       SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr,
1173                                       DAG.getConstant(2, DL, MVT::i32));
1174       SDValue ByteIndex = DAG.getNode(ISD::AND, DL, Ptr.getValueType(), Ptr,
1175                                       DAG.getConstant(0x00000003, DL, VT));
1176       SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant);
1177       SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
1178                                    DAG.getConstant(3, DL, VT));
1179       SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, Shift);
1180       SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, Shift);
1181       // XXX: If we add a 64-bit ZW register class, then we could use a 2 x i32
1182       // vector instead.
1183       SDValue Src[4] = {
1184         ShiftedValue,
1185         DAG.getConstant(0, DL, MVT::i32),
1186         DAG.getConstant(0, DL, MVT::i32),
1187         Mask
1188       };
1189       SDValue Input = DAG.getBuildVector(MVT::v4i32, DL, Src);
1190       SDValue Args[3] = { Chain, Input, DWordAddr };
1191       return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL,
1192                                      Op->getVTList(), Args, MemVT,
1193                                      StoreNode->getMemOperand());
1194     } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR &&
1195                ValueVT.bitsGE(MVT::i32)) {
1196       // Convert pointer from byte address to dword address.
1197       Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
1198                         DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
1199                                     Ptr, DAG.getConstant(2, DL, MVT::i32)));
1200 
1201       if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
1202         llvm_unreachable("Truncated and indexed stores not supported yet");
1203       } else {
1204         Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1205       }
1206       return Chain;
1207     }
1208   }
1209 
1210   if (AS != AMDGPUAS::PRIVATE_ADDRESS)
1211     return SDValue();
1212 
1213   if (MemVT.bitsLT(MVT::i32))
1214     return lowerPrivateTruncStore(StoreNode, DAG);
1215 
1216   // Lowering for indirect addressing
1217   const MachineFunction &MF = DAG.getMachineFunction();
1218   const R600FrameLowering *TFL = getSubtarget()->getFrameLowering();
1219   unsigned StackWidth = TFL->getStackWidth(MF);
1220 
1221   Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1222 
1223   if (ValueVT.isVector()) {
1224     unsigned NumElemVT = ValueVT.getVectorNumElements();
1225     EVT ElemVT = ValueVT.getVectorElementType();
1226     SmallVector<SDValue, 4> Stores(NumElemVT);
1227 
1228     assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1229                                       "vector width in load");
1230 
1231     for (unsigned i = 0; i < NumElemVT; ++i) {
1232       unsigned Channel, PtrIncr;
1233       getStackAddress(StackWidth, i, Channel, PtrIncr);
1234       Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1235                         DAG.getConstant(PtrIncr, DL, MVT::i32));
1236       SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
1237                                  Value, DAG.getConstant(i, DL, MVT::i32));
1238 
1239       Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1240                               Chain, Elem, Ptr,
1241                               DAG.getTargetConstant(Channel, DL, MVT::i32));
1242     }
1243      Chain =  DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores);
1244    } else {
1245     if (ValueVT == MVT::i8) {
1246       Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1247     }
1248     Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
1249     DAG.getTargetConstant(0, DL, MVT::i32)); // Channel
1250   }
1251 
1252   return Chain;
1253 }
1254 
1255 // return (512 + (kc_bank << 12)
1256 static int
1257 ConstantAddressBlock(unsigned AddressSpace) {
1258   switch (AddressSpace) {
1259   case AMDGPUAS::CONSTANT_BUFFER_0:
1260     return 512;
1261   case AMDGPUAS::CONSTANT_BUFFER_1:
1262     return 512 + 4096;
1263   case AMDGPUAS::CONSTANT_BUFFER_2:
1264     return 512 + 4096 * 2;
1265   case AMDGPUAS::CONSTANT_BUFFER_3:
1266     return 512 + 4096 * 3;
1267   case AMDGPUAS::CONSTANT_BUFFER_4:
1268     return 512 + 4096 * 4;
1269   case AMDGPUAS::CONSTANT_BUFFER_5:
1270     return 512 + 4096 * 5;
1271   case AMDGPUAS::CONSTANT_BUFFER_6:
1272     return 512 + 4096 * 6;
1273   case AMDGPUAS::CONSTANT_BUFFER_7:
1274     return 512 + 4096 * 7;
1275   case AMDGPUAS::CONSTANT_BUFFER_8:
1276     return 512 + 4096 * 8;
1277   case AMDGPUAS::CONSTANT_BUFFER_9:
1278     return 512 + 4096 * 9;
1279   case AMDGPUAS::CONSTANT_BUFFER_10:
1280     return 512 + 4096 * 10;
1281   case AMDGPUAS::CONSTANT_BUFFER_11:
1282     return 512 + 4096 * 11;
1283   case AMDGPUAS::CONSTANT_BUFFER_12:
1284     return 512 + 4096 * 12;
1285   case AMDGPUAS::CONSTANT_BUFFER_13:
1286     return 512 + 4096 * 13;
1287   case AMDGPUAS::CONSTANT_BUFFER_14:
1288     return 512 + 4096 * 14;
1289   case AMDGPUAS::CONSTANT_BUFFER_15:
1290     return 512 + 4096 * 15;
1291   default:
1292     return -1;
1293   }
1294 }
1295 
1296 SDValue R600TargetLowering::lowerPrivateExtLoad(SDValue Op,
1297                                                 SelectionDAG &DAG) const {
1298   SDLoc DL(Op);
1299   LoadSDNode *Load = cast<LoadSDNode>(Op);
1300   ISD::LoadExtType ExtType = Load->getExtensionType();
1301   EVT MemVT = Load->getMemoryVT();
1302 
1303   // <SI && AS=PRIVATE && EXTLOAD && size < 32bit,
1304   // register (2-)byte extract.
1305 
1306   // Get Register holding the target.
1307   SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1308                             DAG.getConstant(2, DL, MVT::i32));
1309   // Load the Register.
1310   SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1311                             Load->getChain(),
1312                             Ptr,
1313                             DAG.getTargetConstant(0, DL, MVT::i32),
1314                             Op.getOperand(2));
1315 
1316   // Get offset within the register.
1317   SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1318                                 Load->getBasePtr(),
1319                                 DAG.getConstant(0x3, DL, MVT::i32));
1320 
1321   // Bit offset of target byte (byteIdx * 8).
1322   SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1323                                  DAG.getConstant(3, DL, MVT::i32));
1324 
1325   // Shift to the right.
1326   Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1327 
1328   // Eliminate the upper bits by setting them to ...
1329   EVT MemEltVT = MemVT.getScalarType();
1330 
1331   // ... ones.
1332   if (ExtType == ISD::SEXTLOAD) {
1333     SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1334 
1335     SDValue Ops[] = {
1336       DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1337       Load->getChain()
1338     };
1339 
1340     return DAG.getMergeValues(Ops, DL);
1341   }
1342 
1343   // ... or zeros.
1344   SDValue Ops[] = {
1345     DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1346     Load->getChain()
1347   };
1348 
1349   return DAG.getMergeValues(Ops, DL);
1350 }
1351 
1352 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1353   LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1354   unsigned AS = LoadNode->getAddressSpace();
1355   EVT MemVT = LoadNode->getMemoryVT();
1356   ISD::LoadExtType ExtType = LoadNode->getExtensionType();
1357 
1358   if (AS == AMDGPUAS::PRIVATE_ADDRESS &&
1359       ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(MVT::i32)) {
1360     return lowerPrivateExtLoad(Op, DAG);
1361   }
1362 
1363   SDLoc DL(Op);
1364   EVT VT = Op.getValueType();
1365   SDValue Chain = LoadNode->getChain();
1366   SDValue Ptr = LoadNode->getBasePtr();
1367 
1368   if (LoadNode->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS && VT.isVector()) {
1369     SDValue MergedValues[2] = {
1370       scalarizeVectorLoad(LoadNode, DAG),
1371       Chain
1372     };
1373     return DAG.getMergeValues(MergedValues, DL);
1374   }
1375 
1376   int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
1377   if (ConstantBlock > -1 &&
1378       ((LoadNode->getExtensionType() == ISD::NON_EXTLOAD) ||
1379        (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) {
1380     SDValue Result;
1381     if (isa<ConstantExpr>(LoadNode->getMemOperand()->getValue()) ||
1382         isa<Constant>(LoadNode->getMemOperand()->getValue()) ||
1383         isa<ConstantSDNode>(Ptr)) {
1384       SDValue Slots[4];
1385       for (unsigned i = 0; i < 4; i++) {
1386         // We want Const position encoded with the following formula :
1387         // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1388         // const_index is Ptr computed by llvm using an alignment of 16.
1389         // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1390         // then div by 4 at the ISel step
1391         SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1392             DAG.getConstant(4 * i + ConstantBlock * 16, DL, MVT::i32));
1393         Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1394       }
1395       EVT NewVT = MVT::v4i32;
1396       unsigned NumElements = 4;
1397       if (VT.isVector()) {
1398         NewVT = VT;
1399         NumElements = VT.getVectorNumElements();
1400       }
1401       Result = DAG.getBuildVector(NewVT, DL, makeArrayRef(Slots, NumElements));
1402     } else {
1403       // non-constant ptr can't be folded, keeps it as a v4f32 load
1404       Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1405           DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1406                       DAG.getConstant(4, DL, MVT::i32)),
1407                       DAG.getConstant(LoadNode->getAddressSpace() -
1408                                       AMDGPUAS::CONSTANT_BUFFER_0, DL, MVT::i32)
1409           );
1410     }
1411 
1412     if (!VT.isVector()) {
1413       Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1414                            DAG.getConstant(0, DL, MVT::i32));
1415     }
1416 
1417     SDValue MergedValues[2] = {
1418       Result,
1419       Chain
1420     };
1421     return DAG.getMergeValues(MergedValues, DL);
1422   }
1423 
1424   SDValue LoweredLoad;
1425 
1426   // For most operations returning SDValue() will result in the node being
1427   // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so we
1428   // need to manually expand loads that may be legal in some address spaces and
1429   // illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported for
1430   // compute shaders, since the data is sign extended when it is uploaded to the
1431   // buffer. However SEXT loads from other address spaces are not supported, so
1432   // we need to expand them here.
1433   if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1434     EVT MemVT = LoadNode->getMemoryVT();
1435     assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1436     SDValue NewLoad = DAG.getExtLoad(
1437         ISD::EXTLOAD, DL, VT, Chain, Ptr, LoadNode->getPointerInfo(), MemVT,
1438         LoadNode->getAlignment(), LoadNode->getMemOperand()->getFlags());
1439     SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, NewLoad,
1440                               DAG.getValueType(MemVT));
1441 
1442     SDValue MergedValues[2] = { Res, Chain };
1443     return DAG.getMergeValues(MergedValues, DL);
1444   }
1445 
1446   if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1447     return SDValue();
1448   }
1449 
1450   // Lowering for indirect addressing
1451   const MachineFunction &MF = DAG.getMachineFunction();
1452   const R600FrameLowering *TFL = getSubtarget()->getFrameLowering();
1453   unsigned StackWidth = TFL->getStackWidth(MF);
1454 
1455   Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1456 
1457   if (VT.isVector()) {
1458     unsigned NumElemVT = VT.getVectorNumElements();
1459     EVT ElemVT = VT.getVectorElementType();
1460     SDValue Loads[4];
1461 
1462     assert(NumElemVT <= 4);
1463     assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1464                                       "vector width in load");
1465 
1466     for (unsigned i = 0; i < NumElemVT; ++i) {
1467       unsigned Channel, PtrIncr;
1468       getStackAddress(StackWidth, i, Channel, PtrIncr);
1469       Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1470                         DAG.getConstant(PtrIncr, DL, MVT::i32));
1471       Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
1472                              Chain, Ptr,
1473                              DAG.getTargetConstant(Channel, DL, MVT::i32),
1474                              Op.getOperand(2));
1475     }
1476     EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, NumElemVT);
1477     LoweredLoad = DAG.getBuildVector(TargetVT, DL, makeArrayRef(Loads, NumElemVT));
1478   } else {
1479     LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
1480                               Chain, Ptr,
1481                               DAG.getTargetConstant(0, DL, MVT::i32), // Channel
1482                               Op.getOperand(2));
1483   }
1484 
1485   SDValue Ops[2] = {
1486     LoweredLoad,
1487     Chain
1488   };
1489 
1490   return DAG.getMergeValues(Ops, DL);
1491 }
1492 
1493 SDValue R600TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1494   SDValue Chain = Op.getOperand(0);
1495   SDValue Cond  = Op.getOperand(1);
1496   SDValue Jump  = Op.getOperand(2);
1497 
1498   return DAG.getNode(AMDGPUISD::BRANCH_COND, SDLoc(Op), Op.getValueType(),
1499                      Chain, Jump, Cond);
1500 }
1501 
1502 SDValue R600TargetLowering::lowerFrameIndex(SDValue Op,
1503                                             SelectionDAG &DAG) const {
1504   MachineFunction &MF = DAG.getMachineFunction();
1505   const R600FrameLowering *TFL = getSubtarget()->getFrameLowering();
1506 
1507   FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
1508 
1509   unsigned FrameIndex = FIN->getIndex();
1510   unsigned IgnoredFrameReg;
1511   unsigned Offset =
1512     TFL->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
1513   return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), SDLoc(Op),
1514                          Op.getValueType());
1515 }
1516 
1517 /// XXX Only kernel functions are supported, so we can assume for now that
1518 /// every function is a kernel function, but in the future we should use
1519 /// separate calling conventions for kernel and non-kernel functions.
1520 SDValue R600TargetLowering::LowerFormalArguments(
1521     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1522     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
1523     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1524   SmallVector<CCValAssign, 16> ArgLocs;
1525   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1526                  *DAG.getContext());
1527   MachineFunction &MF = DAG.getMachineFunction();
1528   R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
1529 
1530   SmallVector<ISD::InputArg, 8> LocalIns;
1531 
1532   if (AMDGPU::isShader(CallConv)) {
1533     AnalyzeFormalArguments(CCInfo, Ins);
1534   } else {
1535     analyzeFormalArgumentsCompute(CCInfo, Ins);
1536   }
1537 
1538   for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1539     CCValAssign &VA = ArgLocs[i];
1540     const ISD::InputArg &In = Ins[i];
1541     EVT VT = In.VT;
1542     EVT MemVT = VA.getLocVT();
1543     if (!VT.isVector() && MemVT.isVector()) {
1544       // Get load source type if scalarized.
1545       MemVT = MemVT.getVectorElementType();
1546     }
1547 
1548     if (AMDGPU::isShader(CallConv)) {
1549       unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass);
1550       SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT);
1551       InVals.push_back(Register);
1552       continue;
1553     }
1554 
1555     PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1556                                           AMDGPUAS::CONSTANT_BUFFER_0);
1557 
1558     // i64 isn't a legal type, so the register type used ends up as i32, which
1559     // isn't expected here. It attempts to create this sextload, but it ends up
1560     // being invalid. Somehow this seems to work with i64 arguments, but breaks
1561     // for <1 x i64>.
1562 
1563     // The first 36 bytes of the input buffer contains information about
1564     // thread group and global sizes.
1565     ISD::LoadExtType Ext = ISD::NON_EXTLOAD;
1566     if (MemVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) {
1567       // FIXME: This should really check the extload type, but the handling of
1568       // extload vector parameters seems to be broken.
1569 
1570       // Ext = In.Flags.isSExt() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
1571       Ext = ISD::SEXTLOAD;
1572     }
1573 
1574     // Compute the offset from the value.
1575     // XXX - I think PartOffset should give you this, but it seems to give the
1576     // size of the register which isn't useful.
1577 
1578     unsigned ValBase = ArgLocs[In.getOrigArgIndex()].getLocMemOffset();
1579     unsigned PartOffset = VA.getLocMemOffset();
1580     unsigned Offset = Subtarget->getExplicitKernelArgOffset() + VA.getLocMemOffset();
1581 
1582     MachinePointerInfo PtrInfo(UndefValue::get(PtrTy), PartOffset - ValBase);
1583     SDValue Arg = DAG.getLoad(
1584         ISD::UNINDEXED, Ext, VT, DL, Chain,
1585         DAG.getConstant(Offset, DL, MVT::i32), DAG.getUNDEF(MVT::i32), PtrInfo,
1586         MemVT, /* Alignment = */ 4, MachineMemOperand::MONonTemporal |
1587                                         MachineMemOperand::MODereferenceable |
1588                                         MachineMemOperand::MOInvariant);
1589 
1590     // 4 is the preferred alignment for the CONSTANT memory space.
1591     InVals.push_back(Arg);
1592     MFI->setABIArgOffset(Offset + MemVT.getStoreSize());
1593   }
1594   return Chain;
1595 }
1596 
1597 EVT R600TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1598                                            EVT VT) const {
1599    if (!VT.isVector())
1600      return MVT::i32;
1601    return VT.changeVectorElementTypeToInteger();
1602 }
1603 
1604 bool R600TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1605                                                         unsigned AddrSpace,
1606                                                         unsigned Align,
1607                                                         bool *IsFast) const {
1608   if (IsFast)
1609     *IsFast = false;
1610 
1611   if (!VT.isSimple() || VT == MVT::Other)
1612     return false;
1613 
1614   if (VT.bitsLT(MVT::i32))
1615     return false;
1616 
1617   // TODO: This is a rough estimate.
1618   if (IsFast)
1619     *IsFast = true;
1620 
1621   return VT.bitsGT(MVT::i32) && Align % 4 == 0;
1622 }
1623 
1624 static SDValue CompactSwizzlableVector(
1625   SelectionDAG &DAG, SDValue VectorEntry,
1626   DenseMap<unsigned, unsigned> &RemapSwizzle) {
1627   assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1628   assert(RemapSwizzle.empty());
1629   SDValue NewBldVec[4] = {
1630     VectorEntry.getOperand(0),
1631     VectorEntry.getOperand(1),
1632     VectorEntry.getOperand(2),
1633     VectorEntry.getOperand(3)
1634   };
1635 
1636   for (unsigned i = 0; i < 4; i++) {
1637     if (NewBldVec[i].isUndef())
1638       // We mask write here to teach later passes that the ith element of this
1639       // vector is undef. Thus we can use it to reduce 128 bits reg usage,
1640       // break false dependencies and additionnaly make assembly easier to read.
1641       RemapSwizzle[i] = 7; // SEL_MASK_WRITE
1642     if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) {
1643       if (C->isZero()) {
1644         RemapSwizzle[i] = 4; // SEL_0
1645         NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1646       } else if (C->isExactlyValue(1.0)) {
1647         RemapSwizzle[i] = 5; // SEL_1
1648         NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1649       }
1650     }
1651 
1652     if (NewBldVec[i].isUndef())
1653       continue;
1654     for (unsigned j = 0; j < i; j++) {
1655       if (NewBldVec[i] == NewBldVec[j]) {
1656         NewBldVec[i] = DAG.getUNDEF(NewBldVec[i].getValueType());
1657         RemapSwizzle[i] = j;
1658         break;
1659       }
1660     }
1661   }
1662 
1663   return DAG.getBuildVector(VectorEntry.getValueType(), SDLoc(VectorEntry),
1664                             NewBldVec);
1665 }
1666 
1667 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1668                                 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1669   assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1670   assert(RemapSwizzle.empty());
1671   SDValue NewBldVec[4] = {
1672       VectorEntry.getOperand(0),
1673       VectorEntry.getOperand(1),
1674       VectorEntry.getOperand(2),
1675       VectorEntry.getOperand(3)
1676   };
1677   bool isUnmovable[4] = { false, false, false, false };
1678   for (unsigned i = 0; i < 4; i++) {
1679     RemapSwizzle[i] = i;
1680     if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1681       unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1682           ->getZExtValue();
1683       if (i == Idx)
1684         isUnmovable[Idx] = true;
1685     }
1686   }
1687 
1688   for (unsigned i = 0; i < 4; i++) {
1689     if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1690       unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1691           ->getZExtValue();
1692       if (isUnmovable[Idx])
1693         continue;
1694       // Swap i and Idx
1695       std::swap(NewBldVec[Idx], NewBldVec[i]);
1696       std::swap(RemapSwizzle[i], RemapSwizzle[Idx]);
1697       break;
1698     }
1699   }
1700 
1701   return DAG.getBuildVector(VectorEntry.getValueType(), SDLoc(VectorEntry),
1702                             NewBldVec);
1703 }
1704 
1705 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector, SDValue Swz[4],
1706                                             SelectionDAG &DAG,
1707                                             const SDLoc &DL) const {
1708   assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);
1709   // Old -> New swizzle values
1710   DenseMap<unsigned, unsigned> SwizzleRemap;
1711 
1712   BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
1713   for (unsigned i = 0; i < 4; i++) {
1714     unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
1715     if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1716       Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
1717   }
1718 
1719   SwizzleRemap.clear();
1720   BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
1721   for (unsigned i = 0; i < 4; i++) {
1722     unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
1723     if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1724       Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
1725   }
1726 
1727   return BuildVector;
1728 }
1729 
1730 //===----------------------------------------------------------------------===//
1731 // Custom DAG Optimizations
1732 //===----------------------------------------------------------------------===//
1733 
1734 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1735                                               DAGCombinerInfo &DCI) const {
1736   SelectionDAG &DAG = DCI.DAG;
1737   SDLoc DL(N);
1738 
1739   switch (N->getOpcode()) {
1740   // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1741   case ISD::FP_ROUND: {
1742       SDValue Arg = N->getOperand(0);
1743       if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1744         return DAG.getNode(ISD::UINT_TO_FP, DL, N->getValueType(0),
1745                            Arg.getOperand(0));
1746       }
1747       break;
1748     }
1749 
1750   // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1751   // (i32 select_cc f32, f32, -1, 0 cc)
1752   //
1753   // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1754   // this to one of the SET*_DX10 instructions.
1755   case ISD::FP_TO_SINT: {
1756     SDValue FNeg = N->getOperand(0);
1757     if (FNeg.getOpcode() != ISD::FNEG) {
1758       return SDValue();
1759     }
1760     SDValue SelectCC = FNeg.getOperand(0);
1761     if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1762         SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1763         SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1764         !isHWTrueValue(SelectCC.getOperand(2)) ||
1765         !isHWFalseValue(SelectCC.getOperand(3))) {
1766       return SDValue();
1767     }
1768 
1769     return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0),
1770                            SelectCC.getOperand(0), // LHS
1771                            SelectCC.getOperand(1), // RHS
1772                            DAG.getConstant(-1, DL, MVT::i32), // True
1773                            DAG.getConstant(0, DL, MVT::i32),  // False
1774                            SelectCC.getOperand(4)); // CC
1775 
1776     break;
1777   }
1778 
1779   // insert_vector_elt (build_vector elt0, ... , eltN), NewEltIdx, idx
1780   // => build_vector elt0, ... , NewEltIdx, ... , eltN
1781   case ISD::INSERT_VECTOR_ELT: {
1782     SDValue InVec = N->getOperand(0);
1783     SDValue InVal = N->getOperand(1);
1784     SDValue EltNo = N->getOperand(2);
1785 
1786     // If the inserted element is an UNDEF, just use the input vector.
1787     if (InVal.isUndef())
1788       return InVec;
1789 
1790     EVT VT = InVec.getValueType();
1791 
1792     // If we can't generate a legal BUILD_VECTOR, exit
1793     if (!isOperationLegal(ISD::BUILD_VECTOR, VT))
1794       return SDValue();
1795 
1796     // Check that we know which element is being inserted
1797     if (!isa<ConstantSDNode>(EltNo))
1798       return SDValue();
1799     unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
1800 
1801     // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
1802     // be converted to a BUILD_VECTOR).  Fill in the Ops vector with the
1803     // vector elements.
1804     SmallVector<SDValue, 8> Ops;
1805     if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1806       Ops.append(InVec.getNode()->op_begin(),
1807                  InVec.getNode()->op_end());
1808     } else if (InVec.isUndef()) {
1809       unsigned NElts = VT.getVectorNumElements();
1810       Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
1811     } else {
1812       return SDValue();
1813     }
1814 
1815     // Insert the element
1816     if (Elt < Ops.size()) {
1817       // All the operands of BUILD_VECTOR must have the same type;
1818       // we enforce that here.
1819       EVT OpVT = Ops[0].getValueType();
1820       if (InVal.getValueType() != OpVT)
1821         InVal = OpVT.bitsGT(InVal.getValueType()) ?
1822           DAG.getNode(ISD::ANY_EXTEND, DL, OpVT, InVal) :
1823           DAG.getNode(ISD::TRUNCATE, DL, OpVT, InVal);
1824       Ops[Elt] = InVal;
1825     }
1826 
1827     // Return the new vector
1828     return DAG.getBuildVector(VT, DL, Ops);
1829   }
1830 
1831   // Extract_vec (Build_vector) generated by custom lowering
1832   // also needs to be customly combined
1833   case ISD::EXTRACT_VECTOR_ELT: {
1834     SDValue Arg = N->getOperand(0);
1835     if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1836       if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1837         unsigned Element = Const->getZExtValue();
1838         return Arg->getOperand(Element);
1839       }
1840     }
1841     if (Arg.getOpcode() == ISD::BITCAST &&
1842         Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
1843         (Arg.getOperand(0).getValueType().getVectorNumElements() ==
1844          Arg.getValueType().getVectorNumElements())) {
1845       if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1846         unsigned Element = Const->getZExtValue();
1847         return DAG.getNode(ISD::BITCAST, DL, N->getVTList(),
1848                            Arg->getOperand(0).getOperand(Element));
1849       }
1850     }
1851     break;
1852   }
1853 
1854   case ISD::SELECT_CC: {
1855     // Try common optimizations
1856     if (SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI))
1857       return Ret;
1858 
1859     // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1860     //      selectcc x, y, a, b, inv(cc)
1861     //
1862     // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1863     //      selectcc x, y, a, b, cc
1864     SDValue LHS = N->getOperand(0);
1865     if (LHS.getOpcode() != ISD::SELECT_CC) {
1866       return SDValue();
1867     }
1868 
1869     SDValue RHS = N->getOperand(1);
1870     SDValue True = N->getOperand(2);
1871     SDValue False = N->getOperand(3);
1872     ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1873 
1874     if (LHS.getOperand(2).getNode() != True.getNode() ||
1875         LHS.getOperand(3).getNode() != False.getNode() ||
1876         RHS.getNode() != False.getNode()) {
1877       return SDValue();
1878     }
1879 
1880     switch (NCC) {
1881     default: return SDValue();
1882     case ISD::SETNE: return LHS;
1883     case ISD::SETEQ: {
1884       ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1885       LHSCC = ISD::getSetCCInverse(LHSCC,
1886                                   LHS.getOperand(0).getValueType().isInteger());
1887       if (DCI.isBeforeLegalizeOps() ||
1888           isCondCodeLegal(LHSCC, LHS.getOperand(0).getSimpleValueType()))
1889         return DAG.getSelectCC(DL,
1890                                LHS.getOperand(0),
1891                                LHS.getOperand(1),
1892                                LHS.getOperand(2),
1893                                LHS.getOperand(3),
1894                                LHSCC);
1895       break;
1896     }
1897     }
1898     return SDValue();
1899   }
1900 
1901   case AMDGPUISD::R600_EXPORT: {
1902     SDValue Arg = N->getOperand(1);
1903     if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1904       break;
1905 
1906     SDValue NewArgs[8] = {
1907       N->getOperand(0), // Chain
1908       SDValue(),
1909       N->getOperand(2), // ArrayBase
1910       N->getOperand(3), // Type
1911       N->getOperand(4), // SWZ_X
1912       N->getOperand(5), // SWZ_Y
1913       N->getOperand(6), // SWZ_Z
1914       N->getOperand(7) // SWZ_W
1915     };
1916     NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG, DL);
1917     return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, N->getVTList(), NewArgs);
1918   }
1919   case AMDGPUISD::TEXTURE_FETCH: {
1920     SDValue Arg = N->getOperand(1);
1921     if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1922       break;
1923 
1924     SDValue NewArgs[19] = {
1925       N->getOperand(0),
1926       N->getOperand(1),
1927       N->getOperand(2),
1928       N->getOperand(3),
1929       N->getOperand(4),
1930       N->getOperand(5),
1931       N->getOperand(6),
1932       N->getOperand(7),
1933       N->getOperand(8),
1934       N->getOperand(9),
1935       N->getOperand(10),
1936       N->getOperand(11),
1937       N->getOperand(12),
1938       N->getOperand(13),
1939       N->getOperand(14),
1940       N->getOperand(15),
1941       N->getOperand(16),
1942       N->getOperand(17),
1943       N->getOperand(18),
1944     };
1945     NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG, DL);
1946     return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, N->getVTList(), NewArgs);
1947   }
1948   default: break;
1949   }
1950 
1951   return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1952 }
1953 
1954 bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx,
1955                                      SDValue &Src, SDValue &Neg, SDValue &Abs,
1956                                      SDValue &Sel, SDValue &Imm,
1957                                      SelectionDAG &DAG) const {
1958   const R600InstrInfo *TII = getSubtarget()->getInstrInfo();
1959   if (!Src.isMachineOpcode())
1960     return false;
1961 
1962   switch (Src.getMachineOpcode()) {
1963   case AMDGPU::FNEG_R600:
1964     if (!Neg.getNode())
1965       return false;
1966     Src = Src.getOperand(0);
1967     Neg = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32);
1968     return true;
1969   case AMDGPU::FABS_R600:
1970     if (!Abs.getNode())
1971       return false;
1972     Src = Src.getOperand(0);
1973     Abs = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32);
1974     return true;
1975   case AMDGPU::CONST_COPY: {
1976     unsigned Opcode = ParentNode->getMachineOpcode();
1977     bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
1978 
1979     if (!Sel.getNode())
1980       return false;
1981 
1982     SDValue CstOffset = Src.getOperand(0);
1983     if (ParentNode->getValueType(0).isVector())
1984       return false;
1985 
1986     // Gather constants values
1987     int SrcIndices[] = {
1988       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
1989       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
1990       TII->getOperandIdx(Opcode, AMDGPU::OpName::src2),
1991       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
1992       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
1993       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
1994       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
1995       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
1996       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
1997       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
1998       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
1999     };
2000     std::vector<unsigned> Consts;
2001     for (int OtherSrcIdx : SrcIndices) {
2002       int OtherSelIdx = TII->getSelIdx(Opcode, OtherSrcIdx);
2003       if (OtherSrcIdx < 0 || OtherSelIdx < 0)
2004         continue;
2005       if (HasDst) {
2006         OtherSrcIdx--;
2007         OtherSelIdx--;
2008       }
2009       if (RegisterSDNode *Reg =
2010           dyn_cast<RegisterSDNode>(ParentNode->getOperand(OtherSrcIdx))) {
2011         if (Reg->getReg() == AMDGPU::ALU_CONST) {
2012           ConstantSDNode *Cst
2013             = cast<ConstantSDNode>(ParentNode->getOperand(OtherSelIdx));
2014           Consts.push_back(Cst->getZExtValue());
2015         }
2016       }
2017     }
2018 
2019     ConstantSDNode *Cst = cast<ConstantSDNode>(CstOffset);
2020     Consts.push_back(Cst->getZExtValue());
2021     if (!TII->fitsConstReadLimitations(Consts)) {
2022       return false;
2023     }
2024 
2025     Sel = CstOffset;
2026     Src = DAG.getRegister(AMDGPU::ALU_CONST, MVT::f32);
2027     return true;
2028   }
2029   case AMDGPU::MOV_IMM_GLOBAL_ADDR:
2030     // Check if the Imm slot is used. Taken from below.
2031     if (cast<ConstantSDNode>(Imm)->getZExtValue())
2032       return false;
2033     Imm = Src.getOperand(0);
2034     Src = DAG.getRegister(AMDGPU::ALU_LITERAL_X, MVT::i32);
2035     return true;
2036   case AMDGPU::MOV_IMM_I32:
2037   case AMDGPU::MOV_IMM_F32: {
2038     unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
2039     uint64_t ImmValue = 0;
2040 
2041     if (Src.getMachineOpcode() == AMDGPU::MOV_IMM_F32) {
2042       ConstantFPSDNode *FPC = dyn_cast<ConstantFPSDNode>(Src.getOperand(0));
2043       float FloatValue = FPC->getValueAPF().convertToFloat();
2044       if (FloatValue == 0.0) {
2045         ImmReg = AMDGPU::ZERO;
2046       } else if (FloatValue == 0.5) {
2047         ImmReg = AMDGPU::HALF;
2048       } else if (FloatValue == 1.0) {
2049         ImmReg = AMDGPU::ONE;
2050       } else {
2051         ImmValue = FPC->getValueAPF().bitcastToAPInt().getZExtValue();
2052       }
2053     } else {
2054       ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src.getOperand(0));
2055       uint64_t Value = C->getZExtValue();
2056       if (Value == 0) {
2057         ImmReg = AMDGPU::ZERO;
2058       } else if (Value == 1) {
2059         ImmReg = AMDGPU::ONE_INT;
2060       } else {
2061         ImmValue = Value;
2062       }
2063     }
2064 
2065     // Check that we aren't already using an immediate.
2066     // XXX: It's possible for an instruction to have more than one
2067     // immediate operand, but this is not supported yet.
2068     if (ImmReg == AMDGPU::ALU_LITERAL_X) {
2069       if (!Imm.getNode())
2070         return false;
2071       ConstantSDNode *C = dyn_cast<ConstantSDNode>(Imm);
2072       assert(C);
2073       if (C->getZExtValue())
2074         return false;
2075       Imm = DAG.getTargetConstant(ImmValue, SDLoc(ParentNode), MVT::i32);
2076     }
2077     Src = DAG.getRegister(ImmReg, MVT::i32);
2078     return true;
2079   }
2080   default:
2081     return false;
2082   }
2083 }
2084 
2085 /// \brief Fold the instructions after selecting them
2086 SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node,
2087                                             SelectionDAG &DAG) const {
2088   const R600InstrInfo *TII = getSubtarget()->getInstrInfo();
2089   if (!Node->isMachineOpcode())
2090     return Node;
2091 
2092   unsigned Opcode = Node->getMachineOpcode();
2093   SDValue FakeOp;
2094 
2095   std::vector<SDValue> Ops(Node->op_begin(), Node->op_end());
2096 
2097   if (Opcode == AMDGPU::DOT_4) {
2098     int OperandIdx[] = {
2099       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
2100       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
2101       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
2102       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
2103       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
2104       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
2105       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
2106       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
2107         };
2108     int NegIdx[] = {
2109       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_X),
2110       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Y),
2111       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Z),
2112       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_W),
2113       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_X),
2114       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Y),
2115       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Z),
2116       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_W)
2117     };
2118     int AbsIdx[] = {
2119       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_X),
2120       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Y),
2121       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Z),
2122       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_W),
2123       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_X),
2124       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Y),
2125       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Z),
2126       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_W)
2127     };
2128     for (unsigned i = 0; i < 8; i++) {
2129       if (OperandIdx[i] < 0)
2130         return Node;
2131       SDValue &Src = Ops[OperandIdx[i] - 1];
2132       SDValue &Neg = Ops[NegIdx[i] - 1];
2133       SDValue &Abs = Ops[AbsIdx[i] - 1];
2134       bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2135       int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2136       if (HasDst)
2137         SelIdx--;
2138       SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2139       if (FoldOperand(Node, i, Src, Neg, Abs, Sel, FakeOp, DAG))
2140         return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2141     }
2142   } else if (Opcode == AMDGPU::REG_SEQUENCE) {
2143     for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) {
2144       SDValue &Src = Ops[i];
2145       if (FoldOperand(Node, i, Src, FakeOp, FakeOp, FakeOp, FakeOp, DAG))
2146         return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2147     }
2148   } else if (Opcode == AMDGPU::CLAMP_R600) {
2149     SDValue Src = Node->getOperand(0);
2150     if (!Src.isMachineOpcode() ||
2151         !TII->hasInstrModifiers(Src.getMachineOpcode()))
2152       return Node;
2153     int ClampIdx = TII->getOperandIdx(Src.getMachineOpcode(),
2154         AMDGPU::OpName::clamp);
2155     if (ClampIdx < 0)
2156       return Node;
2157     SDLoc DL(Node);
2158     std::vector<SDValue> Ops(Src->op_begin(), Src->op_end());
2159     Ops[ClampIdx - 1] = DAG.getTargetConstant(1, DL, MVT::i32);
2160     return DAG.getMachineNode(Src.getMachineOpcode(), DL,
2161                               Node->getVTList(), Ops);
2162   } else {
2163     if (!TII->hasInstrModifiers(Opcode))
2164       return Node;
2165     int OperandIdx[] = {
2166       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
2167       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
2168       TII->getOperandIdx(Opcode, AMDGPU::OpName::src2)
2169     };
2170     int NegIdx[] = {
2171       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg),
2172       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg),
2173       TII->getOperandIdx(Opcode, AMDGPU::OpName::src2_neg)
2174     };
2175     int AbsIdx[] = {
2176       TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs),
2177       TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs),
2178       -1
2179     };
2180     for (unsigned i = 0; i < 3; i++) {
2181       if (OperandIdx[i] < 0)
2182         return Node;
2183       SDValue &Src = Ops[OperandIdx[i] - 1];
2184       SDValue &Neg = Ops[NegIdx[i] - 1];
2185       SDValue FakeAbs;
2186       SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
2187       bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2188       int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2189       int ImmIdx = TII->getOperandIdx(Opcode, AMDGPU::OpName::literal);
2190       if (HasDst) {
2191         SelIdx--;
2192         ImmIdx--;
2193       }
2194       SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2195       SDValue &Imm = Ops[ImmIdx];
2196       if (FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG))
2197         return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2198     }
2199   }
2200 
2201   return Node;
2202 }
2203