1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Custom DAG lowering for R600
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "R600ISelLowering.h"
15 #include "AMDGPUFrameLowering.h"
16 #include "AMDGPUSubtarget.h"
17 #include "R600Defines.h"
18 #include "R600FrameLowering.h"
19 #include "R600InstrInfo.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
22 #include "Utils/AMDGPUBaseInfo.h"
23 #include "llvm/ADT/APFloat.h"
24 #include "llvm/ADT/APInt.h"
25 #include "llvm/ADT/ArrayRef.h"
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/DAGCombine.h"
30 #include "llvm/CodeGen/ISDOpcodes.h"
31 #include "llvm/CodeGen/MachineBasicBlock.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstr.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineMemOperand.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/Support/Casting.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/MachineValueType.h"
44 #include "llvm/Support/MathExtras.h"
45 #include <cassert>
46 #include <cstdint>
47 #include <iterator>
48 #include <utility>
49 #include <vector>
50 
51 using namespace llvm;
52 
53 #include "R600GenCallingConv.inc"
54 
55 R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
56                                        const R600Subtarget &STI)
57     : AMDGPUTargetLowering(TM, STI), Subtarget(&STI), Gen(STI.getGeneration()) {
58   addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass);
59   addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass);
60   addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass);
61   addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass);
62   addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass);
63   addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass);
64 
65   setBooleanContents(ZeroOrNegativeOneBooleanContent);
66   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
67 
68   computeRegisterProperties(Subtarget->getRegisterInfo());
69 
70   // Legalize loads and stores to the private address space.
71   setOperationAction(ISD::LOAD, MVT::i32, Custom);
72   setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
73   setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
74 
75   // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address
76   // spaces, so it is custom lowered to handle those where it isn't.
77   for (MVT VT : MVT::integer_valuetypes()) {
78     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
79     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom);
80     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Custom);
81 
82     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
83     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom);
84     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom);
85 
86     setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
87     setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom);
88     setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom);
89   }
90 
91   // Workaround for LegalizeDAG asserting on expansion of i1 vector loads.
92   setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, MVT::v2i1, Expand);
93   setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, MVT::v2i1, Expand);
94   setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, MVT::v2i1, Expand);
95 
96   setLoadExtAction(ISD::EXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
97   setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
98   setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
99 
100   setOperationAction(ISD::STORE, MVT::i8, Custom);
101   setOperationAction(ISD::STORE, MVT::i32, Custom);
102   setOperationAction(ISD::STORE, MVT::v2i32, Custom);
103   setOperationAction(ISD::STORE, MVT::v4i32, Custom);
104 
105   setTruncStoreAction(MVT::i32, MVT::i8, Custom);
106   setTruncStoreAction(MVT::i32, MVT::i16, Custom);
107   // We need to include these since trunc STORES to PRIVATE need
108   // special handling to accommodate RMW
109   setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
110   setTruncStoreAction(MVT::v4i32, MVT::v4i16, Custom);
111   setTruncStoreAction(MVT::v8i32, MVT::v8i16, Custom);
112   setTruncStoreAction(MVT::v16i32, MVT::v16i16, Custom);
113   setTruncStoreAction(MVT::v32i32, MVT::v32i16, Custom);
114   setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
115   setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
116   setTruncStoreAction(MVT::v8i32, MVT::v8i8, Custom);
117   setTruncStoreAction(MVT::v16i32, MVT::v16i8, Custom);
118   setTruncStoreAction(MVT::v32i32, MVT::v32i8, Custom);
119 
120   // Workaround for LegalizeDAG asserting on expansion of i1 vector stores.
121   setTruncStoreAction(MVT::v2i32, MVT::v2i1, Expand);
122   setTruncStoreAction(MVT::v4i32, MVT::v4i1, Expand);
123 
124   // Set condition code actions
125   setCondCodeAction(ISD::SETO,   MVT::f32, Expand);
126   setCondCodeAction(ISD::SETUO,  MVT::f32, Expand);
127   setCondCodeAction(ISD::SETLT,  MVT::f32, Expand);
128   setCondCodeAction(ISD::SETLE,  MVT::f32, Expand);
129   setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
130   setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
131   setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
132   setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
133   setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
134   setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
135   setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
136   setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
137 
138   setCondCodeAction(ISD::SETLE, MVT::i32, Expand);
139   setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
140   setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
141   setCondCodeAction(ISD::SETULT, MVT::i32, Expand);
142 
143   setOperationAction(ISD::FCOS, MVT::f32, Custom);
144   setOperationAction(ISD::FSIN, MVT::f32, Custom);
145 
146   setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
147   setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
148 
149   setOperationAction(ISD::BR_CC, MVT::i32, Expand);
150   setOperationAction(ISD::BR_CC, MVT::f32, Expand);
151   setOperationAction(ISD::BRCOND, MVT::Other, Custom);
152 
153   setOperationAction(ISD::FSUB, MVT::f32, Expand);
154 
155   setOperationAction(ISD::FCEIL, MVT::f64, Custom);
156   setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
157   setOperationAction(ISD::FRINT, MVT::f64, Custom);
158   setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
159 
160   setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
161   setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
162 
163   setOperationAction(ISD::SETCC, MVT::i32, Expand);
164   setOperationAction(ISD::SETCC, MVT::f32, Expand);
165   setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
166   setOperationAction(ISD::FP_TO_SINT, MVT::i1, Custom);
167   setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
168   setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
169 
170   setOperationAction(ISD::SELECT, MVT::i32, Expand);
171   setOperationAction(ISD::SELECT, MVT::f32, Expand);
172   setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
173   setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
174 
175   // ADD, SUB overflow.
176   // TODO: turn these into Legal?
177   if (Subtarget->hasCARRY())
178     setOperationAction(ISD::UADDO, MVT::i32, Custom);
179 
180   if (Subtarget->hasBORROW())
181     setOperationAction(ISD::USUBO, MVT::i32, Custom);
182 
183   // Expand sign extension of vectors
184   if (!Subtarget->hasBFE())
185     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
186 
187   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand);
188   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand);
189 
190   if (!Subtarget->hasBFE())
191     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
192   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand);
193   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand);
194 
195   if (!Subtarget->hasBFE())
196     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
197   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand);
198   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
199 
200   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
201   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand);
202   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
203 
204   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
205 
206   setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
207 
208   setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom);
209   setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom);
210   setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
211   setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
212 
213   setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom);
214   setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom);
215   setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
216   setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
217 
218   // We don't have 64-bit shifts. Thus we need either SHX i64 or SHX_PARTS i32
219   //  to be Legal/Custom in order to avoid library calls.
220   setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
221   setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
222   setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
223 
224   if (!Subtarget->hasFMA()) {
225     setOperationAction(ISD::FMA, MVT::f32, Expand);
226     setOperationAction(ISD::FMA, MVT::f64, Expand);
227   }
228 
229   // FIXME: May need no denormals check
230   setOperationAction(ISD::FMAD, MVT::f32, Legal);
231 
232   if (!Subtarget->hasBFI()) {
233     // fcopysign can be done in a single instruction with BFI.
234     setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
235     setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
236   }
237 
238   if (!Subtarget->hasBCNT(32))
239     setOperationAction(ISD::CTPOP, MVT::i32, Expand);
240 
241   if (!Subtarget->hasBCNT(64))
242     setOperationAction(ISD::CTPOP, MVT::i64, Expand);
243 
244   if (Subtarget->hasFFBH())
245     setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom);
246 
247   if (Subtarget->hasFFBL())
248     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Custom);
249 
250   // FIXME: This was moved from AMDGPUTargetLowering, I'm not sure if we
251   // need it for R600.
252   if (Subtarget->hasBFE())
253     setHasExtractBitsInsn(true);
254 
255   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
256 
257   const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
258   for (MVT VT : ScalarIntVTs) {
259     setOperationAction(ISD::ADDC, VT, Expand);
260     setOperationAction(ISD::SUBC, VT, Expand);
261     setOperationAction(ISD::ADDE, VT, Expand);
262     setOperationAction(ISD::SUBE, VT, Expand);
263   }
264 
265   // LLVM will expand these to atomic_cmp_swap(0)
266   // and atomic_swap, respectively.
267   setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
268   setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
269 
270   // We need to custom lower some of the intrinsics
271   setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
272   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
273 
274   setSchedulingPreference(Sched::Source);
275 
276   setTargetDAGCombine(ISD::FP_ROUND);
277   setTargetDAGCombine(ISD::FP_TO_SINT);
278   setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
279   setTargetDAGCombine(ISD::SELECT_CC);
280   setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
281   setTargetDAGCombine(ISD::LOAD);
282 }
283 
284 static inline bool isEOP(MachineBasicBlock::iterator I) {
285   if (std::next(I) == I->getParent()->end())
286     return false;
287   return std::next(I)->getOpcode() == R600::RETURN;
288 }
289 
290 MachineBasicBlock *
291 R600TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
292                                                 MachineBasicBlock *BB) const {
293   MachineFunction *MF = BB->getParent();
294   MachineRegisterInfo &MRI = MF->getRegInfo();
295   MachineBasicBlock::iterator I = MI;
296   const R600InstrInfo *TII = Subtarget->getInstrInfo();
297 
298   switch (MI.getOpcode()) {
299   default:
300     // Replace LDS_*_RET instruction that don't have any uses with the
301     // equivalent LDS_*_NORET instruction.
302     if (TII->isLDSRetInstr(MI.getOpcode())) {
303       int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst);
304       assert(DstIdx != -1);
305       MachineInstrBuilder NewMI;
306       // FIXME: getLDSNoRetOp method only handles LDS_1A1D LDS ops. Add
307       //        LDS_1A2D support and remove this special case.
308       if (!MRI.use_empty(MI.getOperand(DstIdx).getReg()) ||
309           MI.getOpcode() == R600::LDS_CMPST_RET)
310         return BB;
311 
312       NewMI = BuildMI(*BB, I, BB->findDebugLoc(I),
313                       TII->get(R600::getLDSNoRetOp(MI.getOpcode())));
314       for (unsigned i = 1, e = MI.getNumOperands(); i < e; ++i) {
315         NewMI.add(MI.getOperand(i));
316       }
317     } else {
318       return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
319     }
320     break;
321 
322   case R600::FABS_R600: {
323     MachineInstr *NewMI = TII->buildDefaultInstruction(
324         *BB, I, R600::MOV, MI.getOperand(0).getReg(),
325         MI.getOperand(1).getReg());
326     TII->addFlag(*NewMI, 0, MO_FLAG_ABS);
327     break;
328   }
329 
330   case R600::FNEG_R600: {
331     MachineInstr *NewMI = TII->buildDefaultInstruction(
332         *BB, I, R600::MOV, MI.getOperand(0).getReg(),
333         MI.getOperand(1).getReg());
334     TII->addFlag(*NewMI, 0, MO_FLAG_NEG);
335     break;
336   }
337 
338   case R600::MASK_WRITE: {
339     Register maskedRegister = MI.getOperand(0).getReg();
340     assert(Register::isVirtualRegister(maskedRegister));
341     MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
342     TII->addFlag(*defInstr, 0, MO_FLAG_MASK);
343     break;
344   }
345 
346   case R600::MOV_IMM_F32:
347     TII->buildMovImm(*BB, I, MI.getOperand(0).getReg(), MI.getOperand(1)
348                                                             .getFPImm()
349                                                             ->getValueAPF()
350                                                             .bitcastToAPInt()
351                                                             .getZExtValue());
352     break;
353 
354   case R600::MOV_IMM_I32:
355     TII->buildMovImm(*BB, I, MI.getOperand(0).getReg(),
356                      MI.getOperand(1).getImm());
357     break;
358 
359   case R600::MOV_IMM_GLOBAL_ADDR: {
360     //TODO: Perhaps combine this instruction with the next if possible
361     auto MIB = TII->buildDefaultInstruction(
362         *BB, MI, R600::MOV, MI.getOperand(0).getReg(), R600::ALU_LITERAL_X);
363     int Idx = TII->getOperandIdx(*MIB, R600::OpName::literal);
364     //TODO: Ugh this is rather ugly
365     MIB->getOperand(Idx) = MI.getOperand(1);
366     break;
367   }
368 
369   case R600::CONST_COPY: {
370     MachineInstr *NewMI = TII->buildDefaultInstruction(
371         *BB, MI, R600::MOV, MI.getOperand(0).getReg(), R600::ALU_CONST);
372     TII->setImmOperand(*NewMI, R600::OpName::src0_sel,
373                        MI.getOperand(1).getImm());
374     break;
375   }
376 
377   case R600::RAT_WRITE_CACHELESS_32_eg:
378   case R600::RAT_WRITE_CACHELESS_64_eg:
379   case R600::RAT_WRITE_CACHELESS_128_eg:
380     BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode()))
381         .add(MI.getOperand(0))
382         .add(MI.getOperand(1))
383         .addImm(isEOP(I)); // Set End of program bit
384     break;
385 
386   case R600::RAT_STORE_TYPED_eg:
387     BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode()))
388         .add(MI.getOperand(0))
389         .add(MI.getOperand(1))
390         .add(MI.getOperand(2))
391         .addImm(isEOP(I)); // Set End of program bit
392     break;
393 
394   case R600::BRANCH:
395     BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::JUMP))
396         .add(MI.getOperand(0));
397     break;
398 
399   case R600::BRANCH_COND_f32: {
400     MachineInstr *NewMI =
401         BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::PRED_X),
402                 R600::PREDICATE_BIT)
403             .add(MI.getOperand(1))
404             .addImm(R600::PRED_SETNE)
405             .addImm(0); // Flags
406     TII->addFlag(*NewMI, 0, MO_FLAG_PUSH);
407     BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::JUMP_COND))
408         .add(MI.getOperand(0))
409         .addReg(R600::PREDICATE_BIT, RegState::Kill);
410     break;
411   }
412 
413   case R600::BRANCH_COND_i32: {
414     MachineInstr *NewMI =
415         BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::PRED_X),
416                 R600::PREDICATE_BIT)
417             .add(MI.getOperand(1))
418             .addImm(R600::PRED_SETNE_INT)
419             .addImm(0); // Flags
420     TII->addFlag(*NewMI, 0, MO_FLAG_PUSH);
421     BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::JUMP_COND))
422         .add(MI.getOperand(0))
423         .addReg(R600::PREDICATE_BIT, RegState::Kill);
424     break;
425   }
426 
427   case R600::EG_ExportSwz:
428   case R600::R600_ExportSwz: {
429     // Instruction is left unmodified if its not the last one of its type
430     bool isLastInstructionOfItsType = true;
431     unsigned InstExportType = MI.getOperand(1).getImm();
432     for (MachineBasicBlock::iterator NextExportInst = std::next(I),
433          EndBlock = BB->end(); NextExportInst != EndBlock;
434          NextExportInst = std::next(NextExportInst)) {
435       if (NextExportInst->getOpcode() == R600::EG_ExportSwz ||
436           NextExportInst->getOpcode() == R600::R600_ExportSwz) {
437         unsigned CurrentInstExportType = NextExportInst->getOperand(1)
438             .getImm();
439         if (CurrentInstExportType == InstExportType) {
440           isLastInstructionOfItsType = false;
441           break;
442         }
443       }
444     }
445     bool EOP = isEOP(I);
446     if (!EOP && !isLastInstructionOfItsType)
447       return BB;
448     unsigned CfInst = (MI.getOpcode() == R600::EG_ExportSwz) ? 84 : 40;
449     BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode()))
450         .add(MI.getOperand(0))
451         .add(MI.getOperand(1))
452         .add(MI.getOperand(2))
453         .add(MI.getOperand(3))
454         .add(MI.getOperand(4))
455         .add(MI.getOperand(5))
456         .add(MI.getOperand(6))
457         .addImm(CfInst)
458         .addImm(EOP);
459     break;
460   }
461   case R600::RETURN: {
462     return BB;
463   }
464   }
465 
466   MI.eraseFromParent();
467   return BB;
468 }
469 
470 //===----------------------------------------------------------------------===//
471 // Custom DAG Lowering Operations
472 //===----------------------------------------------------------------------===//
473 
474 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
475   MachineFunction &MF = DAG.getMachineFunction();
476   R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
477   switch (Op.getOpcode()) {
478   default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
479   case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
480   case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
481   case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
482   case ISD::SRA_PARTS:
483   case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
484   case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY);
485   case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW);
486   case ISD::FCOS:
487   case ISD::FSIN: return LowerTrig(Op, DAG);
488   case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
489   case ISD::STORE: return LowerSTORE(Op, DAG);
490   case ISD::LOAD: {
491     SDValue Result = LowerLOAD(Op, DAG);
492     assert((!Result.getNode() ||
493             Result.getNode()->getNumValues() == 2) &&
494            "Load should return a value and a chain");
495     return Result;
496   }
497 
498   case ISD::BRCOND: return LowerBRCOND(Op, DAG);
499   case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
500   case ISD::FrameIndex: return lowerFrameIndex(Op, DAG);
501   case ISD::INTRINSIC_VOID: {
502     SDValue Chain = Op.getOperand(0);
503     unsigned IntrinsicID =
504                          cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
505     switch (IntrinsicID) {
506     case Intrinsic::r600_store_swizzle: {
507       SDLoc DL(Op);
508       const SDValue Args[8] = {
509         Chain,
510         Op.getOperand(2), // Export Value
511         Op.getOperand(3), // ArrayBase
512         Op.getOperand(4), // Type
513         DAG.getConstant(0, DL, MVT::i32), // SWZ_X
514         DAG.getConstant(1, DL, MVT::i32), // SWZ_Y
515         DAG.getConstant(2, DL, MVT::i32), // SWZ_Z
516         DAG.getConstant(3, DL, MVT::i32) // SWZ_W
517       };
518       return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, Op.getValueType(), Args);
519     }
520 
521     // default for switch(IntrinsicID)
522     default: break;
523     }
524     // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
525     break;
526   }
527   case ISD::INTRINSIC_WO_CHAIN: {
528     unsigned IntrinsicID =
529                          cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
530     EVT VT = Op.getValueType();
531     SDLoc DL(Op);
532     switch (IntrinsicID) {
533     case Intrinsic::r600_tex:
534     case Intrinsic::r600_texc: {
535       unsigned TextureOp;
536       switch (IntrinsicID) {
537       case Intrinsic::r600_tex:
538         TextureOp = 0;
539         break;
540       case Intrinsic::r600_texc:
541         TextureOp = 1;
542         break;
543       default:
544         llvm_unreachable("unhandled texture operation");
545       }
546 
547       SDValue TexArgs[19] = {
548         DAG.getConstant(TextureOp, DL, MVT::i32),
549         Op.getOperand(1),
550         DAG.getConstant(0, DL, MVT::i32),
551         DAG.getConstant(1, DL, MVT::i32),
552         DAG.getConstant(2, DL, MVT::i32),
553         DAG.getConstant(3, DL, MVT::i32),
554         Op.getOperand(2),
555         Op.getOperand(3),
556         Op.getOperand(4),
557         DAG.getConstant(0, DL, MVT::i32),
558         DAG.getConstant(1, DL, MVT::i32),
559         DAG.getConstant(2, DL, MVT::i32),
560         DAG.getConstant(3, DL, MVT::i32),
561         Op.getOperand(5),
562         Op.getOperand(6),
563         Op.getOperand(7),
564         Op.getOperand(8),
565         Op.getOperand(9),
566         Op.getOperand(10)
567       };
568       return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
569     }
570     case Intrinsic::r600_dot4: {
571       SDValue Args[8] = {
572       DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
573           DAG.getConstant(0, DL, MVT::i32)),
574       DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
575           DAG.getConstant(0, DL, MVT::i32)),
576       DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
577           DAG.getConstant(1, DL, MVT::i32)),
578       DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
579           DAG.getConstant(1, DL, MVT::i32)),
580       DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
581           DAG.getConstant(2, DL, MVT::i32)),
582       DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
583           DAG.getConstant(2, DL, MVT::i32)),
584       DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
585           DAG.getConstant(3, DL, MVT::i32)),
586       DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
587           DAG.getConstant(3, DL, MVT::i32))
588       };
589       return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args);
590     }
591 
592     case Intrinsic::r600_implicitarg_ptr: {
593       MVT PtrVT = getPointerTy(DAG.getDataLayout(), AMDGPUAS::PARAM_I_ADDRESS);
594       uint32_t ByteOffset = getImplicitParameterOffset(MF, FIRST_IMPLICIT);
595       return DAG.getConstant(ByteOffset, DL, PtrVT);
596     }
597     case Intrinsic::r600_read_ngroups_x:
598       return LowerImplicitParameter(DAG, VT, DL, 0);
599     case Intrinsic::r600_read_ngroups_y:
600       return LowerImplicitParameter(DAG, VT, DL, 1);
601     case Intrinsic::r600_read_ngroups_z:
602       return LowerImplicitParameter(DAG, VT, DL, 2);
603     case Intrinsic::r600_read_global_size_x:
604       return LowerImplicitParameter(DAG, VT, DL, 3);
605     case Intrinsic::r600_read_global_size_y:
606       return LowerImplicitParameter(DAG, VT, DL, 4);
607     case Intrinsic::r600_read_global_size_z:
608       return LowerImplicitParameter(DAG, VT, DL, 5);
609     case Intrinsic::r600_read_local_size_x:
610       return LowerImplicitParameter(DAG, VT, DL, 6);
611     case Intrinsic::r600_read_local_size_y:
612       return LowerImplicitParameter(DAG, VT, DL, 7);
613     case Intrinsic::r600_read_local_size_z:
614       return LowerImplicitParameter(DAG, VT, DL, 8);
615 
616     case Intrinsic::r600_read_tgid_x:
617       return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
618                                      R600::T1_X, VT);
619     case Intrinsic::r600_read_tgid_y:
620       return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
621                                      R600::T1_Y, VT);
622     case Intrinsic::r600_read_tgid_z:
623       return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
624                                      R600::T1_Z, VT);
625     case Intrinsic::r600_read_tidig_x:
626       return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
627                                      R600::T0_X, VT);
628     case Intrinsic::r600_read_tidig_y:
629       return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
630                                      R600::T0_Y, VT);
631     case Intrinsic::r600_read_tidig_z:
632       return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
633                                      R600::T0_Z, VT);
634 
635     case Intrinsic::r600_recipsqrt_ieee:
636       return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
637 
638     case Intrinsic::r600_recipsqrt_clamped:
639       return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1));
640     default:
641       return Op;
642     }
643 
644     // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
645     break;
646   }
647   } // end switch(Op.getOpcode())
648   return SDValue();
649 }
650 
651 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
652                                             SmallVectorImpl<SDValue> &Results,
653                                             SelectionDAG &DAG) const {
654   switch (N->getOpcode()) {
655   default:
656     AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG);
657     return;
658   case ISD::FP_TO_UINT:
659     if (N->getValueType(0) == MVT::i1) {
660       Results.push_back(lowerFP_TO_UINT(N->getOperand(0), DAG));
661       return;
662     }
663     // Since we don't care about out of bounds values we can use FP_TO_SINT for
664     // uints too. The DAGLegalizer code for uint considers some extra cases
665     // which are not necessary here.
666     LLVM_FALLTHROUGH;
667   case ISD::FP_TO_SINT: {
668     if (N->getValueType(0) == MVT::i1) {
669       Results.push_back(lowerFP_TO_SINT(N->getOperand(0), DAG));
670       return;
671     }
672 
673     SDValue Result;
674     if (expandFP_TO_SINT(N, Result, DAG))
675       Results.push_back(Result);
676     return;
677   }
678   case ISD::SDIVREM: {
679     SDValue Op = SDValue(N, 1);
680     SDValue RES = LowerSDIVREM(Op, DAG);
681     Results.push_back(RES);
682     Results.push_back(RES.getValue(1));
683     break;
684   }
685   case ISD::UDIVREM: {
686     SDValue Op = SDValue(N, 0);
687     LowerUDIVREM64(Op, DAG, Results);
688     break;
689   }
690   }
691 }
692 
693 SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG,
694                                                    SDValue Vector) const {
695   SDLoc DL(Vector);
696   EVT VecVT = Vector.getValueType();
697   EVT EltVT = VecVT.getVectorElementType();
698   SmallVector<SDValue, 8> Args;
699 
700   for (unsigned i = 0, e = VecVT.getVectorNumElements(); i != e; ++i) {
701     Args.push_back(DAG.getNode(
702         ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vector,
703         DAG.getConstant(i, DL, getVectorIdxTy(DAG.getDataLayout()))));
704   }
705 
706   return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args);
707 }
708 
709 SDValue R600TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
710                                                     SelectionDAG &DAG) const {
711   SDLoc DL(Op);
712   SDValue Vector = Op.getOperand(0);
713   SDValue Index = Op.getOperand(1);
714 
715   if (isa<ConstantSDNode>(Index) ||
716       Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
717     return Op;
718 
719   Vector = vectorToVerticalVector(DAG, Vector);
720   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(),
721                      Vector, Index);
722 }
723 
724 SDValue R600TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
725                                                    SelectionDAG &DAG) const {
726   SDLoc DL(Op);
727   SDValue Vector = Op.getOperand(0);
728   SDValue Value = Op.getOperand(1);
729   SDValue Index = Op.getOperand(2);
730 
731   if (isa<ConstantSDNode>(Index) ||
732       Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
733     return Op;
734 
735   Vector = vectorToVerticalVector(DAG, Vector);
736   SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(),
737                                Vector, Value, Index);
738   return vectorToVerticalVector(DAG, Insert);
739 }
740 
741 SDValue R600TargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
742                                                SDValue Op,
743                                                SelectionDAG &DAG) const {
744   GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
745   if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
746     return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
747 
748   const DataLayout &DL = DAG.getDataLayout();
749   const GlobalValue *GV = GSD->getGlobal();
750   MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
751 
752   SDValue GA = DAG.getTargetGlobalAddress(GV, SDLoc(GSD), ConstPtrVT);
753   return DAG.getNode(AMDGPUISD::CONST_DATA_PTR, SDLoc(GSD), ConstPtrVT, GA);
754 }
755 
756 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
757   // On hw >= R700, COS/SIN input must be between -1. and 1.
758   // Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
759   EVT VT = Op.getValueType();
760   SDValue Arg = Op.getOperand(0);
761   SDLoc DL(Op);
762 
763   // TODO: Should this propagate fast-math-flags?
764   SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT,
765       DAG.getNode(ISD::FADD, DL, VT,
766         DAG.getNode(ISD::FMUL, DL, VT, Arg,
767           DAG.getConstantFP(0.15915494309, DL, MVT::f32)),
768         DAG.getConstantFP(0.5, DL, MVT::f32)));
769   unsigned TrigNode;
770   switch (Op.getOpcode()) {
771   case ISD::FCOS:
772     TrigNode = AMDGPUISD::COS_HW;
773     break;
774   case ISD::FSIN:
775     TrigNode = AMDGPUISD::SIN_HW;
776     break;
777   default:
778     llvm_unreachable("Wrong trig opcode");
779   }
780   SDValue TrigVal = DAG.getNode(TrigNode, DL, VT,
781       DAG.getNode(ISD::FADD, DL, VT, FractPart,
782         DAG.getConstantFP(-0.5, DL, MVT::f32)));
783   if (Gen >= AMDGPUSubtarget::R700)
784     return TrigVal;
785   // On R600 hw, COS/SIN input must be between -Pi and Pi.
786   return DAG.getNode(ISD::FMUL, DL, VT, TrigVal,
787       DAG.getConstantFP(numbers::pif, DL, MVT::f32));
788 }
789 
790 SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const {
791   SDLoc DL(Op);
792   EVT VT = Op.getValueType();
793 
794   SDValue Lo = Op.getOperand(0);
795   SDValue Hi = Op.getOperand(1);
796   SDValue Shift = Op.getOperand(2);
797   SDValue Zero = DAG.getConstant(0, DL, VT);
798   SDValue One  = DAG.getConstant(1, DL, VT);
799 
800   SDValue Width  = DAG.getConstant(VT.getSizeInBits(), DL, VT);
801   SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT);
802   SDValue BigShift  = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
803   SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
804 
805   // The dance around Width1 is necessary for 0 special case.
806   // Without it the CompShift might be 32, producing incorrect results in
807   // Overflow. So we do the shift in two steps, the alternative is to
808   // add a conditional to filter the special case.
809 
810   SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift);
811   Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One);
812 
813   SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift);
814   HiSmall = DAG.getNode(ISD::OR, DL, VT, HiSmall, Overflow);
815   SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift);
816 
817   SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift);
818   SDValue LoBig = Zero;
819 
820   Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
821   Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
822 
823   return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
824 }
825 
826 SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const {
827   SDLoc DL(Op);
828   EVT VT = Op.getValueType();
829 
830   SDValue Lo = Op.getOperand(0);
831   SDValue Hi = Op.getOperand(1);
832   SDValue Shift = Op.getOperand(2);
833   SDValue Zero = DAG.getConstant(0, DL, VT);
834   SDValue One  = DAG.getConstant(1, DL, VT);
835 
836   const bool SRA = Op.getOpcode() == ISD::SRA_PARTS;
837 
838   SDValue Width  = DAG.getConstant(VT.getSizeInBits(), DL, VT);
839   SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT);
840   SDValue BigShift  = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
841   SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
842 
843   // The dance around Width1 is necessary for 0 special case.
844   // Without it the CompShift might be 32, producing incorrect results in
845   // Overflow. So we do the shift in two steps, the alternative is to
846   // add a conditional to filter the special case.
847 
848   SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift);
849   Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One);
850 
851   SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift);
852   SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift);
853   LoSmall = DAG.getNode(ISD::OR, DL, VT, LoSmall, Overflow);
854 
855   SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift);
856   SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero;
857 
858   Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
859   Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
860 
861   return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
862 }
863 
864 SDValue R600TargetLowering::LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
865                                           unsigned mainop, unsigned ovf) const {
866   SDLoc DL(Op);
867   EVT VT = Op.getValueType();
868 
869   SDValue Lo = Op.getOperand(0);
870   SDValue Hi = Op.getOperand(1);
871 
872   SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi);
873   // Extend sign.
874   OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF,
875                     DAG.getValueType(MVT::i1));
876 
877   SDValue Res = DAG.getNode(mainop, DL, VT, Lo, Hi);
878 
879   return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF);
880 }
881 
882 SDValue R600TargetLowering::lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const {
883   SDLoc DL(Op);
884   return DAG.getNode(
885       ISD::SETCC,
886       DL,
887       MVT::i1,
888       Op, DAG.getConstantFP(1.0f, DL, MVT::f32),
889       DAG.getCondCode(ISD::SETEQ));
890 }
891 
892 SDValue R600TargetLowering::lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const {
893   SDLoc DL(Op);
894   return DAG.getNode(
895       ISD::SETCC,
896       DL,
897       MVT::i1,
898       Op, DAG.getConstantFP(-1.0f, DL, MVT::f32),
899       DAG.getCondCode(ISD::SETEQ));
900 }
901 
902 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
903                                                    const SDLoc &DL,
904                                                    unsigned DwordOffset) const {
905   unsigned ByteOffset = DwordOffset * 4;
906   PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
907                                       AMDGPUAS::PARAM_I_ADDRESS);
908 
909   // We shouldn't be using an offset wider than 16-bits for implicit parameters.
910   assert(isInt<16>(ByteOffset));
911 
912   return DAG.getLoad(VT, DL, DAG.getEntryNode(),
913                      DAG.getConstant(ByteOffset, DL, MVT::i32), // PTR
914                      MachinePointerInfo(ConstantPointerNull::get(PtrType)));
915 }
916 
917 bool R600TargetLowering::isZero(SDValue Op) const {
918   if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
919     return Cst->isNullValue();
920   } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
921     return CstFP->isZero();
922   } else {
923     return false;
924   }
925 }
926 
927 bool R600TargetLowering::isHWTrueValue(SDValue Op) const {
928   if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
929     return CFP->isExactlyValue(1.0);
930   }
931   return isAllOnesConstant(Op);
932 }
933 
934 bool R600TargetLowering::isHWFalseValue(SDValue Op) const {
935   if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
936     return CFP->getValueAPF().isZero();
937   }
938   return isNullConstant(Op);
939 }
940 
941 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
942   SDLoc DL(Op);
943   EVT VT = Op.getValueType();
944 
945   SDValue LHS = Op.getOperand(0);
946   SDValue RHS = Op.getOperand(1);
947   SDValue True = Op.getOperand(2);
948   SDValue False = Op.getOperand(3);
949   SDValue CC = Op.getOperand(4);
950   SDValue Temp;
951 
952   if (VT == MVT::f32) {
953     DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
954     SDValue MinMax = combineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
955     if (MinMax)
956       return MinMax;
957   }
958 
959   // LHS and RHS are guaranteed to be the same value type
960   EVT CompareVT = LHS.getValueType();
961 
962   // Check if we can lower this to a native operation.
963 
964   // Try to lower to a SET* instruction:
965   //
966   // SET* can match the following patterns:
967   //
968   // select_cc f32, f32, -1,  0, cc_supported
969   // select_cc f32, f32, 1.0f, 0.0f, cc_supported
970   // select_cc i32, i32, -1,  0, cc_supported
971   //
972 
973   // Move hardware True/False values to the correct operand.
974   if (isHWTrueValue(False) && isHWFalseValue(True)) {
975     ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
976     ISD::CondCode InverseCC =
977         ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
978     if (isCondCodeLegal(InverseCC, CompareVT.getSimpleVT())) {
979       std::swap(False, True);
980       CC = DAG.getCondCode(InverseCC);
981     } else {
982       ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InverseCC);
983       if (isCondCodeLegal(SwapInvCC, CompareVT.getSimpleVT())) {
984         std::swap(False, True);
985         std::swap(LHS, RHS);
986         CC = DAG.getCondCode(SwapInvCC);
987       }
988     }
989   }
990 
991   if (isHWTrueValue(True) && isHWFalseValue(False) &&
992       (CompareVT == VT || VT == MVT::i32)) {
993     // This can be matched by a SET* instruction.
994     return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
995   }
996 
997   // Try to lower to a CND* instruction:
998   //
999   // CND* can match the following patterns:
1000   //
1001   // select_cc f32, 0.0, f32, f32, cc_supported
1002   // select_cc f32, 0.0, i32, i32, cc_supported
1003   // select_cc i32, 0,   f32, f32, cc_supported
1004   // select_cc i32, 0,   i32, i32, cc_supported
1005   //
1006 
1007   // Try to move the zero value to the RHS
1008   if (isZero(LHS)) {
1009     ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1010     // Try swapping the operands
1011     ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(CCOpcode);
1012     if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
1013       std::swap(LHS, RHS);
1014       CC = DAG.getCondCode(CCSwapped);
1015     } else {
1016       // Try inverting the conditon and then swapping the operands
1017       ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT.isInteger());
1018       CCSwapped = ISD::getSetCCSwappedOperands(CCInv);
1019       if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
1020         std::swap(True, False);
1021         std::swap(LHS, RHS);
1022         CC = DAG.getCondCode(CCSwapped);
1023       }
1024     }
1025   }
1026   if (isZero(RHS)) {
1027     SDValue Cond = LHS;
1028     SDValue Zero = RHS;
1029     ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1030     if (CompareVT != VT) {
1031       // Bitcast True / False to the correct types.  This will end up being
1032       // a nop, but it allows us to define only a single pattern in the
1033       // .TD files for each CND* instruction rather than having to have
1034       // one pattern for integer True/False and one for fp True/False
1035       True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
1036       False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
1037     }
1038 
1039     switch (CCOpcode) {
1040     case ISD::SETONE:
1041     case ISD::SETUNE:
1042     case ISD::SETNE:
1043       CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
1044       Temp = True;
1045       True = False;
1046       False = Temp;
1047       break;
1048     default:
1049       break;
1050     }
1051     SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
1052         Cond, Zero,
1053         True, False,
1054         DAG.getCondCode(CCOpcode));
1055     return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
1056   }
1057 
1058   // If we make it this for it means we have no native instructions to handle
1059   // this SELECT_CC, so we must lower it.
1060   SDValue HWTrue, HWFalse;
1061 
1062   if (CompareVT == MVT::f32) {
1063     HWTrue = DAG.getConstantFP(1.0f, DL, CompareVT);
1064     HWFalse = DAG.getConstantFP(0.0f, DL, CompareVT);
1065   } else if (CompareVT == MVT::i32) {
1066     HWTrue = DAG.getConstant(-1, DL, CompareVT);
1067     HWFalse = DAG.getConstant(0, DL, CompareVT);
1068   }
1069   else {
1070     llvm_unreachable("Unhandled value type in LowerSELECT_CC");
1071   }
1072 
1073   // Lower this unsupported SELECT_CC into a combination of two supported
1074   // SELECT_CC operations.
1075   SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
1076 
1077   return DAG.getNode(ISD::SELECT_CC, DL, VT,
1078       Cond, HWFalse,
1079       True, False,
1080       DAG.getCondCode(ISD::SETNE));
1081 }
1082 
1083 /// LLVM generates byte-addressed pointers.  For indirect addressing, we need to
1084 /// convert these pointers to a register index.  Each register holds
1085 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
1086 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
1087 /// for indirect addressing.
1088 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
1089                                                unsigned StackWidth,
1090                                                SelectionDAG &DAG) const {
1091   unsigned SRLPad;
1092   switch(StackWidth) {
1093   case 1:
1094     SRLPad = 2;
1095     break;
1096   case 2:
1097     SRLPad = 3;
1098     break;
1099   case 4:
1100     SRLPad = 4;
1101     break;
1102   default: llvm_unreachable("Invalid stack width");
1103   }
1104 
1105   SDLoc DL(Ptr);
1106   return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr,
1107                      DAG.getConstant(SRLPad, DL, MVT::i32));
1108 }
1109 
1110 void R600TargetLowering::getStackAddress(unsigned StackWidth,
1111                                          unsigned ElemIdx,
1112                                          unsigned &Channel,
1113                                          unsigned &PtrIncr) const {
1114   switch (StackWidth) {
1115   default:
1116   case 1:
1117     Channel = 0;
1118     if (ElemIdx > 0) {
1119       PtrIncr = 1;
1120     } else {
1121       PtrIncr = 0;
1122     }
1123     break;
1124   case 2:
1125     Channel = ElemIdx % 2;
1126     if (ElemIdx == 2) {
1127       PtrIncr = 1;
1128     } else {
1129       PtrIncr = 0;
1130     }
1131     break;
1132   case 4:
1133     Channel = ElemIdx;
1134     PtrIncr = 0;
1135     break;
1136   }
1137 }
1138 
1139 SDValue R600TargetLowering::lowerPrivateTruncStore(StoreSDNode *Store,
1140                                                    SelectionDAG &DAG) const {
1141   SDLoc DL(Store);
1142   //TODO: Who creates the i8 stores?
1143   assert(Store->isTruncatingStore()
1144          || Store->getValue().getValueType() == MVT::i8);
1145   assert(Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS);
1146 
1147   SDValue Mask;
1148   if (Store->getMemoryVT() == MVT::i8) {
1149     assert(Store->getAlignment() >= 1);
1150     Mask = DAG.getConstant(0xff, DL, MVT::i32);
1151   } else if (Store->getMemoryVT() == MVT::i16) {
1152     assert(Store->getAlignment() >= 2);
1153     Mask = DAG.getConstant(0xffff, DL, MVT::i32);
1154   } else {
1155     llvm_unreachable("Unsupported private trunc store");
1156   }
1157 
1158   SDValue OldChain = Store->getChain();
1159   bool VectorTrunc = (OldChain.getOpcode() == AMDGPUISD::DUMMY_CHAIN);
1160   // Skip dummy
1161   SDValue Chain = VectorTrunc ? OldChain->getOperand(0) : OldChain;
1162   SDValue BasePtr = Store->getBasePtr();
1163   SDValue Offset = Store->getOffset();
1164   EVT MemVT = Store->getMemoryVT();
1165 
1166   SDValue LoadPtr = BasePtr;
1167   if (!Offset.isUndef()) {
1168     LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset);
1169   }
1170 
1171   // Get dword location
1172   // TODO: this should be eliminated by the future SHR ptr, 2
1173   SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr,
1174                             DAG.getConstant(0xfffffffc, DL, MVT::i32));
1175 
1176   // Load dword
1177   // TODO: can we be smarter about machine pointer info?
1178   MachinePointerInfo PtrInfo(UndefValue::get(
1179       Type::getInt32PtrTy(*DAG.getContext(), AMDGPUAS::PRIVATE_ADDRESS)));
1180   SDValue Dst = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo);
1181 
1182   Chain = Dst.getValue(1);
1183 
1184   // Get offset in dword
1185   SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr,
1186                                 DAG.getConstant(0x3, DL, MVT::i32));
1187 
1188   // Convert byte offset to bit shift
1189   SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1190                                  DAG.getConstant(3, DL, MVT::i32));
1191 
1192   // TODO: Contrary to the name of the functiom,
1193   // it also handles sub i32 non-truncating stores (like i1)
1194   SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1195                                   Store->getValue());
1196 
1197   // Mask the value to the right type
1198   SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1199 
1200   // Shift the value in place
1201   SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1202                                      MaskedValue, ShiftAmt);
1203 
1204   // Shift the mask in place
1205   SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt);
1206 
1207   // Invert the mask. NOTE: if we had native ROL instructions we could
1208   // use inverted mask
1209   DstMask = DAG.getNOT(DL, DstMask, MVT::i32);
1210 
1211   // Cleanup the target bits
1212   Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1213 
1214   // Add the new bits
1215   SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1216 
1217   // Store dword
1218   // TODO: Can we be smarter about MachinePointerInfo?
1219   SDValue NewStore = DAG.getStore(Chain, DL, Value, Ptr, PtrInfo);
1220 
1221   // If we are part of expanded vector, make our neighbors depend on this store
1222   if (VectorTrunc) {
1223     // Make all other vector elements depend on this store
1224     Chain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, NewStore);
1225     DAG.ReplaceAllUsesOfValueWith(OldChain, Chain);
1226   }
1227   return NewStore;
1228 }
1229 
1230 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1231   StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
1232   unsigned AS = StoreNode->getAddressSpace();
1233 
1234   SDValue Chain = StoreNode->getChain();
1235   SDValue Ptr = StoreNode->getBasePtr();
1236   SDValue Value = StoreNode->getValue();
1237 
1238   EVT VT = Value.getValueType();
1239   EVT MemVT = StoreNode->getMemoryVT();
1240   EVT PtrVT = Ptr.getValueType();
1241 
1242   SDLoc DL(Op);
1243 
1244   const bool TruncatingStore = StoreNode->isTruncatingStore();
1245 
1246   // Neither LOCAL nor PRIVATE can do vectors at the moment
1247   if ((AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::PRIVATE_ADDRESS ||
1248        TruncatingStore) &&
1249       VT.isVector()) {
1250     if ((AS == AMDGPUAS::PRIVATE_ADDRESS) && TruncatingStore) {
1251       // Add an extra level of chain to isolate this vector
1252       SDValue NewChain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, Chain);
1253       // TODO: can the chain be replaced without creating a new store?
1254       SDValue NewStore = DAG.getTruncStore(
1255           NewChain, DL, Value, Ptr, StoreNode->getPointerInfo(),
1256           MemVT, StoreNode->getAlignment(),
1257           StoreNode->getMemOperand()->getFlags(), StoreNode->getAAInfo());
1258       StoreNode = cast<StoreSDNode>(NewStore);
1259     }
1260 
1261     return scalarizeVectorStore(StoreNode, DAG);
1262   }
1263 
1264   unsigned Align = StoreNode->getAlignment();
1265   if (Align < MemVT.getStoreSize() &&
1266       !allowsMisalignedMemoryAccesses(
1267           MemVT, AS, Align, StoreNode->getMemOperand()->getFlags(), nullptr)) {
1268     return expandUnalignedStore(StoreNode, DAG);
1269   }
1270 
1271   SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, PtrVT, Ptr,
1272                                   DAG.getConstant(2, DL, PtrVT));
1273 
1274   if (AS == AMDGPUAS::GLOBAL_ADDRESS) {
1275     // It is beneficial to create MSKOR here instead of combiner to avoid
1276     // artificial dependencies introduced by RMW
1277     if (TruncatingStore) {
1278       assert(VT.bitsLE(MVT::i32));
1279       SDValue MaskConstant;
1280       if (MemVT == MVT::i8) {
1281         MaskConstant = DAG.getConstant(0xFF, DL, MVT::i32);
1282       } else {
1283         assert(MemVT == MVT::i16);
1284         assert(StoreNode->getAlignment() >= 2);
1285         MaskConstant = DAG.getConstant(0xFFFF, DL, MVT::i32);
1286       }
1287 
1288       SDValue ByteIndex = DAG.getNode(ISD::AND, DL, PtrVT, Ptr,
1289                                       DAG.getConstant(0x00000003, DL, PtrVT));
1290       SDValue BitShift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
1291                                      DAG.getConstant(3, DL, VT));
1292 
1293       // Put the mask in correct place
1294       SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, BitShift);
1295 
1296       // Put the value bits in correct place
1297       SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant);
1298       SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, BitShift);
1299 
1300       // XXX: If we add a 64-bit ZW register class, then we could use a 2 x i32
1301       // vector instead.
1302       SDValue Src[4] = {
1303         ShiftedValue,
1304         DAG.getConstant(0, DL, MVT::i32),
1305         DAG.getConstant(0, DL, MVT::i32),
1306         Mask
1307       };
1308       SDValue Input = DAG.getBuildVector(MVT::v4i32, DL, Src);
1309       SDValue Args[3] = { Chain, Input, DWordAddr };
1310       return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL,
1311                                      Op->getVTList(), Args, MemVT,
1312                                      StoreNode->getMemOperand());
1313     } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR && VT.bitsGE(MVT::i32)) {
1314       // Convert pointer from byte address to dword address.
1315       Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr);
1316 
1317       if (StoreNode->isIndexed()) {
1318         llvm_unreachable("Indexed stores not supported yet");
1319       } else {
1320         Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1321       }
1322       return Chain;
1323     }
1324   }
1325 
1326   // GLOBAL_ADDRESS has been handled above, LOCAL_ADDRESS allows all sizes
1327   if (AS != AMDGPUAS::PRIVATE_ADDRESS)
1328     return SDValue();
1329 
1330   if (MemVT.bitsLT(MVT::i32))
1331     return lowerPrivateTruncStore(StoreNode, DAG);
1332 
1333   // Standard i32+ store, tag it with DWORDADDR to note that the address
1334   // has been shifted
1335   if (Ptr.getOpcode() != AMDGPUISD::DWORDADDR) {
1336     Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr);
1337     return DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1338   }
1339 
1340   // Tagged i32+ stores will be matched by patterns
1341   return SDValue();
1342 }
1343 
1344 // return (512 + (kc_bank << 12)
1345 static int
1346 ConstantAddressBlock(unsigned AddressSpace) {
1347   switch (AddressSpace) {
1348   case AMDGPUAS::CONSTANT_BUFFER_0:
1349     return 512;
1350   case AMDGPUAS::CONSTANT_BUFFER_1:
1351     return 512 + 4096;
1352   case AMDGPUAS::CONSTANT_BUFFER_2:
1353     return 512 + 4096 * 2;
1354   case AMDGPUAS::CONSTANT_BUFFER_3:
1355     return 512 + 4096 * 3;
1356   case AMDGPUAS::CONSTANT_BUFFER_4:
1357     return 512 + 4096 * 4;
1358   case AMDGPUAS::CONSTANT_BUFFER_5:
1359     return 512 + 4096 * 5;
1360   case AMDGPUAS::CONSTANT_BUFFER_6:
1361     return 512 + 4096 * 6;
1362   case AMDGPUAS::CONSTANT_BUFFER_7:
1363     return 512 + 4096 * 7;
1364   case AMDGPUAS::CONSTANT_BUFFER_8:
1365     return 512 + 4096 * 8;
1366   case AMDGPUAS::CONSTANT_BUFFER_9:
1367     return 512 + 4096 * 9;
1368   case AMDGPUAS::CONSTANT_BUFFER_10:
1369     return 512 + 4096 * 10;
1370   case AMDGPUAS::CONSTANT_BUFFER_11:
1371     return 512 + 4096 * 11;
1372   case AMDGPUAS::CONSTANT_BUFFER_12:
1373     return 512 + 4096 * 12;
1374   case AMDGPUAS::CONSTANT_BUFFER_13:
1375     return 512 + 4096 * 13;
1376   case AMDGPUAS::CONSTANT_BUFFER_14:
1377     return 512 + 4096 * 14;
1378   case AMDGPUAS::CONSTANT_BUFFER_15:
1379     return 512 + 4096 * 15;
1380   default:
1381     return -1;
1382   }
1383 }
1384 
1385 SDValue R600TargetLowering::lowerPrivateExtLoad(SDValue Op,
1386                                                 SelectionDAG &DAG) const {
1387   SDLoc DL(Op);
1388   LoadSDNode *Load = cast<LoadSDNode>(Op);
1389   ISD::LoadExtType ExtType = Load->getExtensionType();
1390   EVT MemVT = Load->getMemoryVT();
1391   assert(Load->getAlignment() >= MemVT.getStoreSize());
1392 
1393   SDValue BasePtr = Load->getBasePtr();
1394   SDValue Chain = Load->getChain();
1395   SDValue Offset = Load->getOffset();
1396 
1397   SDValue LoadPtr = BasePtr;
1398   if (!Offset.isUndef()) {
1399     LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset);
1400   }
1401 
1402   // Get dword location
1403   // NOTE: this should be eliminated by the future SHR ptr, 2
1404   SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr,
1405                             DAG.getConstant(0xfffffffc, DL, MVT::i32));
1406 
1407   // Load dword
1408   // TODO: can we be smarter about machine pointer info?
1409   MachinePointerInfo PtrInfo(UndefValue::get(
1410       Type::getInt32PtrTy(*DAG.getContext(), AMDGPUAS::PRIVATE_ADDRESS)));
1411   SDValue Read = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo);
1412 
1413   // Get offset within the register.
1414   SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1415                                 LoadPtr, DAG.getConstant(0x3, DL, MVT::i32));
1416 
1417   // Bit offset of target byte (byteIdx * 8).
1418   SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1419                                  DAG.getConstant(3, DL, MVT::i32));
1420 
1421   // Shift to the right.
1422   SDValue Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Read, ShiftAmt);
1423 
1424   // Eliminate the upper bits by setting them to ...
1425   EVT MemEltVT = MemVT.getScalarType();
1426 
1427   if (ExtType == ISD::SEXTLOAD) { // ... ones.
1428     SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1429     Ret = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode);
1430   } else { // ... or zeros.
1431     Ret = DAG.getZeroExtendInReg(Ret, DL, MemEltVT);
1432   }
1433 
1434   SDValue Ops[] = {
1435     Ret,
1436     Read.getValue(1) // This should be our output chain
1437   };
1438 
1439   return DAG.getMergeValues(Ops, DL);
1440 }
1441 
1442 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1443   LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1444   unsigned AS = LoadNode->getAddressSpace();
1445   EVT MemVT = LoadNode->getMemoryVT();
1446   ISD::LoadExtType ExtType = LoadNode->getExtensionType();
1447 
1448   if (AS == AMDGPUAS::PRIVATE_ADDRESS &&
1449       ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(MVT::i32)) {
1450     return lowerPrivateExtLoad(Op, DAG);
1451   }
1452 
1453   SDLoc DL(Op);
1454   EVT VT = Op.getValueType();
1455   SDValue Chain = LoadNode->getChain();
1456   SDValue Ptr = LoadNode->getBasePtr();
1457 
1458   if ((LoadNode->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1459       LoadNode->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1460       VT.isVector()) {
1461       return scalarizeVectorLoad(LoadNode, DAG);
1462   }
1463 
1464   // This is still used for explicit load from addrspace(8)
1465   int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
1466   if (ConstantBlock > -1 &&
1467       ((LoadNode->getExtensionType() == ISD::NON_EXTLOAD) ||
1468        (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) {
1469     SDValue Result;
1470     if (isa<Constant>(LoadNode->getMemOperand()->getValue()) ||
1471         isa<ConstantSDNode>(Ptr)) {
1472       return constBufferLoad(LoadNode, LoadNode->getAddressSpace(), DAG);
1473     } else {
1474       //TODO: Does this even work?
1475       // non-constant ptr can't be folded, keeps it as a v4f32 load
1476       Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1477           DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1478                       DAG.getConstant(4, DL, MVT::i32)),
1479                       DAG.getConstant(LoadNode->getAddressSpace() -
1480                                       AMDGPUAS::CONSTANT_BUFFER_0, DL, MVT::i32)
1481           );
1482     }
1483 
1484     if (!VT.isVector()) {
1485       Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1486                            DAG.getConstant(0, DL, MVT::i32));
1487     }
1488 
1489     SDValue MergedValues[2] = {
1490       Result,
1491       Chain
1492     };
1493     return DAG.getMergeValues(MergedValues, DL);
1494   }
1495 
1496   // For most operations returning SDValue() will result in the node being
1497   // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so we
1498   // need to manually expand loads that may be legal in some address spaces and
1499   // illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported for
1500   // compute shaders, since the data is sign extended when it is uploaded to the
1501   // buffer. However SEXT loads from other address spaces are not supported, so
1502   // we need to expand them here.
1503   if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1504     assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1505     SDValue NewLoad = DAG.getExtLoad(
1506         ISD::EXTLOAD, DL, VT, Chain, Ptr, LoadNode->getPointerInfo(), MemVT,
1507         LoadNode->getAlignment(), LoadNode->getMemOperand()->getFlags());
1508     SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, NewLoad,
1509                               DAG.getValueType(MemVT));
1510 
1511     SDValue MergedValues[2] = { Res, Chain };
1512     return DAG.getMergeValues(MergedValues, DL);
1513   }
1514 
1515   if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1516     return SDValue();
1517   }
1518 
1519   // DWORDADDR ISD marks already shifted address
1520   if (Ptr.getOpcode() != AMDGPUISD::DWORDADDR) {
1521     assert(VT == MVT::i32);
1522     Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(2, DL, MVT::i32));
1523     Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, MVT::i32, Ptr);
1524     return DAG.getLoad(MVT::i32, DL, Chain, Ptr, LoadNode->getMemOperand());
1525   }
1526   return SDValue();
1527 }
1528 
1529 SDValue R600TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1530   SDValue Chain = Op.getOperand(0);
1531   SDValue Cond  = Op.getOperand(1);
1532   SDValue Jump  = Op.getOperand(2);
1533 
1534   return DAG.getNode(AMDGPUISD::BRANCH_COND, SDLoc(Op), Op.getValueType(),
1535                      Chain, Jump, Cond);
1536 }
1537 
1538 SDValue R600TargetLowering::lowerFrameIndex(SDValue Op,
1539                                             SelectionDAG &DAG) const {
1540   MachineFunction &MF = DAG.getMachineFunction();
1541   const R600FrameLowering *TFL = Subtarget->getFrameLowering();
1542 
1543   FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
1544 
1545   unsigned FrameIndex = FIN->getIndex();
1546   unsigned IgnoredFrameReg;
1547   unsigned Offset =
1548     TFL->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
1549   return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), SDLoc(Op),
1550                          Op.getValueType());
1551 }
1552 
1553 CCAssignFn *R600TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1554                                                   bool IsVarArg) const {
1555   switch (CC) {
1556   case CallingConv::AMDGPU_KERNEL:
1557   case CallingConv::SPIR_KERNEL:
1558   case CallingConv::C:
1559   case CallingConv::Fast:
1560   case CallingConv::Cold:
1561     llvm_unreachable("kernels should not be handled here");
1562   case CallingConv::AMDGPU_VS:
1563   case CallingConv::AMDGPU_GS:
1564   case CallingConv::AMDGPU_PS:
1565   case CallingConv::AMDGPU_CS:
1566   case CallingConv::AMDGPU_HS:
1567   case CallingConv::AMDGPU_ES:
1568   case CallingConv::AMDGPU_LS:
1569     return CC_R600;
1570   default:
1571     report_fatal_error("Unsupported calling convention.");
1572   }
1573 }
1574 
1575 /// XXX Only kernel functions are supported, so we can assume for now that
1576 /// every function is a kernel function, but in the future we should use
1577 /// separate calling conventions for kernel and non-kernel functions.
1578 SDValue R600TargetLowering::LowerFormalArguments(
1579     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1580     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
1581     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1582   SmallVector<CCValAssign, 16> ArgLocs;
1583   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1584                  *DAG.getContext());
1585   MachineFunction &MF = DAG.getMachineFunction();
1586   SmallVector<ISD::InputArg, 8> LocalIns;
1587 
1588   if (AMDGPU::isShader(CallConv)) {
1589     CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
1590   } else {
1591     analyzeFormalArgumentsCompute(CCInfo, Ins);
1592   }
1593 
1594   for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1595     CCValAssign &VA = ArgLocs[i];
1596     const ISD::InputArg &In = Ins[i];
1597     EVT VT = In.VT;
1598     EVT MemVT = VA.getLocVT();
1599     if (!VT.isVector() && MemVT.isVector()) {
1600       // Get load source type if scalarized.
1601       MemVT = MemVT.getVectorElementType();
1602     }
1603 
1604     if (AMDGPU::isShader(CallConv)) {
1605       unsigned Reg = MF.addLiveIn(VA.getLocReg(), &R600::R600_Reg128RegClass);
1606       SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT);
1607       InVals.push_back(Register);
1608       continue;
1609     }
1610 
1611     PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1612                                           AMDGPUAS::PARAM_I_ADDRESS);
1613 
1614     // i64 isn't a legal type, so the register type used ends up as i32, which
1615     // isn't expected here. It attempts to create this sextload, but it ends up
1616     // being invalid. Somehow this seems to work with i64 arguments, but breaks
1617     // for <1 x i64>.
1618 
1619     // The first 36 bytes of the input buffer contains information about
1620     // thread group and global sizes.
1621     ISD::LoadExtType Ext = ISD::NON_EXTLOAD;
1622     if (MemVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) {
1623       // FIXME: This should really check the extload type, but the handling of
1624       // extload vector parameters seems to be broken.
1625 
1626       // Ext = In.Flags.isSExt() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
1627       Ext = ISD::SEXTLOAD;
1628     }
1629 
1630     // Compute the offset from the value.
1631     // XXX - I think PartOffset should give you this, but it seems to give the
1632     // size of the register which isn't useful.
1633 
1634     unsigned ValBase = ArgLocs[In.getOrigArgIndex()].getLocMemOffset();
1635     unsigned PartOffset = VA.getLocMemOffset();
1636     unsigned Alignment = MinAlign(VT.getStoreSize(), PartOffset);
1637 
1638     MachinePointerInfo PtrInfo(UndefValue::get(PtrTy), PartOffset - ValBase);
1639     SDValue Arg = DAG.getLoad(
1640         ISD::UNINDEXED, Ext, VT, DL, Chain,
1641         DAG.getConstant(PartOffset, DL, MVT::i32), DAG.getUNDEF(MVT::i32),
1642         PtrInfo,
1643         MemVT, Alignment, MachineMemOperand::MONonTemporal |
1644                                         MachineMemOperand::MODereferenceable |
1645                                         MachineMemOperand::MOInvariant);
1646 
1647     InVals.push_back(Arg);
1648   }
1649   return Chain;
1650 }
1651 
1652 EVT R600TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1653                                            EVT VT) const {
1654    if (!VT.isVector())
1655      return MVT::i32;
1656    return VT.changeVectorElementTypeToInteger();
1657 }
1658 
1659 bool R600TargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,
1660                                           const SelectionDAG &DAG) const {
1661   // Local and Private addresses do not handle vectors. Limit to i32
1662   if ((AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::PRIVATE_ADDRESS)) {
1663     return (MemVT.getSizeInBits() <= 32);
1664   }
1665   return true;
1666 }
1667 
1668 bool R600TargetLowering::allowsMisalignedMemoryAccesses(
1669     EVT VT, unsigned AddrSpace, unsigned Align, MachineMemOperand::Flags Flags,
1670     bool *IsFast) const {
1671   if (IsFast)
1672     *IsFast = false;
1673 
1674   if (!VT.isSimple() || VT == MVT::Other)
1675     return false;
1676 
1677   if (VT.bitsLT(MVT::i32))
1678     return false;
1679 
1680   // TODO: This is a rough estimate.
1681   if (IsFast)
1682     *IsFast = true;
1683 
1684   return VT.bitsGT(MVT::i32) && Align % 4 == 0;
1685 }
1686 
1687 static SDValue CompactSwizzlableVector(
1688   SelectionDAG &DAG, SDValue VectorEntry,
1689   DenseMap<unsigned, unsigned> &RemapSwizzle) {
1690   assert(RemapSwizzle.empty());
1691 
1692   SDLoc DL(VectorEntry);
1693   EVT EltTy = VectorEntry.getValueType().getVectorElementType();
1694 
1695   SDValue NewBldVec[4];
1696   for (unsigned i = 0; i < 4; i++)
1697     NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry,
1698                                DAG.getIntPtrConstant(i, DL));
1699 
1700   for (unsigned i = 0; i < 4; i++) {
1701     if (NewBldVec[i].isUndef())
1702       // We mask write here to teach later passes that the ith element of this
1703       // vector is undef. Thus we can use it to reduce 128 bits reg usage,
1704       // break false dependencies and additionnaly make assembly easier to read.
1705       RemapSwizzle[i] = 7; // SEL_MASK_WRITE
1706     if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) {
1707       if (C->isZero()) {
1708         RemapSwizzle[i] = 4; // SEL_0
1709         NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1710       } else if (C->isExactlyValue(1.0)) {
1711         RemapSwizzle[i] = 5; // SEL_1
1712         NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1713       }
1714     }
1715 
1716     if (NewBldVec[i].isUndef())
1717       continue;
1718 
1719     for (unsigned j = 0; j < i; j++) {
1720       if (NewBldVec[i] == NewBldVec[j]) {
1721         NewBldVec[i] = DAG.getUNDEF(NewBldVec[i].getValueType());
1722         RemapSwizzle[i] = j;
1723         break;
1724       }
1725     }
1726   }
1727 
1728   return DAG.getBuildVector(VectorEntry.getValueType(), SDLoc(VectorEntry),
1729                             NewBldVec);
1730 }
1731 
1732 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1733                                 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1734   assert(RemapSwizzle.empty());
1735 
1736   SDLoc DL(VectorEntry);
1737   EVT EltTy = VectorEntry.getValueType().getVectorElementType();
1738 
1739   SDValue NewBldVec[4];
1740   bool isUnmovable[4] = {false, false, false, false};
1741   for (unsigned i = 0; i < 4; i++)
1742     NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry,
1743                                DAG.getIntPtrConstant(i, DL));
1744 
1745   for (unsigned i = 0; i < 4; i++) {
1746     RemapSwizzle[i] = i;
1747     if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1748       unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1749           ->getZExtValue();
1750       if (i == Idx)
1751         isUnmovable[Idx] = true;
1752     }
1753   }
1754 
1755   for (unsigned i = 0; i < 4; i++) {
1756     if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1757       unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1758           ->getZExtValue();
1759       if (isUnmovable[Idx])
1760         continue;
1761       // Swap i and Idx
1762       std::swap(NewBldVec[Idx], NewBldVec[i]);
1763       std::swap(RemapSwizzle[i], RemapSwizzle[Idx]);
1764       break;
1765     }
1766   }
1767 
1768   return DAG.getBuildVector(VectorEntry.getValueType(), SDLoc(VectorEntry),
1769                             NewBldVec);
1770 }
1771 
1772 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector, SDValue Swz[4],
1773                                             SelectionDAG &DAG,
1774                                             const SDLoc &DL) const {
1775   // Old -> New swizzle values
1776   DenseMap<unsigned, unsigned> SwizzleRemap;
1777 
1778   BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
1779   for (unsigned i = 0; i < 4; i++) {
1780     unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
1781     if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1782       Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
1783   }
1784 
1785   SwizzleRemap.clear();
1786   BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
1787   for (unsigned i = 0; i < 4; i++) {
1788     unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
1789     if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1790       Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
1791   }
1792 
1793   return BuildVector;
1794 }
1795 
1796 SDValue R600TargetLowering::constBufferLoad(LoadSDNode *LoadNode, int Block,
1797                                             SelectionDAG &DAG) const {
1798   SDLoc DL(LoadNode);
1799   EVT VT = LoadNode->getValueType(0);
1800   SDValue Chain = LoadNode->getChain();
1801   SDValue Ptr = LoadNode->getBasePtr();
1802   assert (isa<ConstantSDNode>(Ptr));
1803 
1804   //TODO: Support smaller loads
1805   if (LoadNode->getMemoryVT().getScalarType() != MVT::i32 || !ISD::isNON_EXTLoad(LoadNode))
1806     return SDValue();
1807 
1808   if (LoadNode->getAlignment() < 4)
1809     return SDValue();
1810 
1811   int ConstantBlock = ConstantAddressBlock(Block);
1812 
1813   SDValue Slots[4];
1814   for (unsigned i = 0; i < 4; i++) {
1815     // We want Const position encoded with the following formula :
1816     // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1817     // const_index is Ptr computed by llvm using an alignment of 16.
1818     // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1819     // then div by 4 at the ISel step
1820     SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1821         DAG.getConstant(4 * i + ConstantBlock * 16, DL, MVT::i32));
1822     Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1823   }
1824   EVT NewVT = MVT::v4i32;
1825   unsigned NumElements = 4;
1826   if (VT.isVector()) {
1827     NewVT = VT;
1828     NumElements = VT.getVectorNumElements();
1829   }
1830   SDValue Result = DAG.getBuildVector(NewVT, DL, makeArrayRef(Slots, NumElements));
1831   if (!VT.isVector()) {
1832     Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1833                          DAG.getConstant(0, DL, MVT::i32));
1834   }
1835   SDValue MergedValues[2] = {
1836     Result,
1837     Chain
1838   };
1839   return DAG.getMergeValues(MergedValues, DL);
1840 }
1841 
1842 //===----------------------------------------------------------------------===//
1843 // Custom DAG Optimizations
1844 //===----------------------------------------------------------------------===//
1845 
1846 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1847                                               DAGCombinerInfo &DCI) const {
1848   SelectionDAG &DAG = DCI.DAG;
1849   SDLoc DL(N);
1850 
1851   switch (N->getOpcode()) {
1852   // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1853   case ISD::FP_ROUND: {
1854       SDValue Arg = N->getOperand(0);
1855       if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1856         return DAG.getNode(ISD::UINT_TO_FP, DL, N->getValueType(0),
1857                            Arg.getOperand(0));
1858       }
1859       break;
1860     }
1861 
1862   // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1863   // (i32 select_cc f32, f32, -1, 0 cc)
1864   //
1865   // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1866   // this to one of the SET*_DX10 instructions.
1867   case ISD::FP_TO_SINT: {
1868     SDValue FNeg = N->getOperand(0);
1869     if (FNeg.getOpcode() != ISD::FNEG) {
1870       return SDValue();
1871     }
1872     SDValue SelectCC = FNeg.getOperand(0);
1873     if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1874         SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1875         SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1876         !isHWTrueValue(SelectCC.getOperand(2)) ||
1877         !isHWFalseValue(SelectCC.getOperand(3))) {
1878       return SDValue();
1879     }
1880 
1881     return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0),
1882                            SelectCC.getOperand(0), // LHS
1883                            SelectCC.getOperand(1), // RHS
1884                            DAG.getConstant(-1, DL, MVT::i32), // True
1885                            DAG.getConstant(0, DL, MVT::i32),  // False
1886                            SelectCC.getOperand(4)); // CC
1887   }
1888 
1889   // insert_vector_elt (build_vector elt0, ... , eltN), NewEltIdx, idx
1890   // => build_vector elt0, ... , NewEltIdx, ... , eltN
1891   case ISD::INSERT_VECTOR_ELT: {
1892     SDValue InVec = N->getOperand(0);
1893     SDValue InVal = N->getOperand(1);
1894     SDValue EltNo = N->getOperand(2);
1895 
1896     // If the inserted element is an UNDEF, just use the input vector.
1897     if (InVal.isUndef())
1898       return InVec;
1899 
1900     EVT VT = InVec.getValueType();
1901 
1902     // If we can't generate a legal BUILD_VECTOR, exit
1903     if (!isOperationLegal(ISD::BUILD_VECTOR, VT))
1904       return SDValue();
1905 
1906     // Check that we know which element is being inserted
1907     if (!isa<ConstantSDNode>(EltNo))
1908       return SDValue();
1909     unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
1910 
1911     // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
1912     // be converted to a BUILD_VECTOR).  Fill in the Ops vector with the
1913     // vector elements.
1914     SmallVector<SDValue, 8> Ops;
1915     if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1916       Ops.append(InVec.getNode()->op_begin(),
1917                  InVec.getNode()->op_end());
1918     } else if (InVec.isUndef()) {
1919       unsigned NElts = VT.getVectorNumElements();
1920       Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
1921     } else {
1922       return SDValue();
1923     }
1924 
1925     // Insert the element
1926     if (Elt < Ops.size()) {
1927       // All the operands of BUILD_VECTOR must have the same type;
1928       // we enforce that here.
1929       EVT OpVT = Ops[0].getValueType();
1930       if (InVal.getValueType() != OpVT)
1931         InVal = OpVT.bitsGT(InVal.getValueType()) ?
1932           DAG.getNode(ISD::ANY_EXTEND, DL, OpVT, InVal) :
1933           DAG.getNode(ISD::TRUNCATE, DL, OpVT, InVal);
1934       Ops[Elt] = InVal;
1935     }
1936 
1937     // Return the new vector
1938     return DAG.getBuildVector(VT, DL, Ops);
1939   }
1940 
1941   // Extract_vec (Build_vector) generated by custom lowering
1942   // also needs to be customly combined
1943   case ISD::EXTRACT_VECTOR_ELT: {
1944     SDValue Arg = N->getOperand(0);
1945     if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1946       if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1947         unsigned Element = Const->getZExtValue();
1948         return Arg->getOperand(Element);
1949       }
1950     }
1951     if (Arg.getOpcode() == ISD::BITCAST &&
1952         Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
1953         (Arg.getOperand(0).getValueType().getVectorNumElements() ==
1954          Arg.getValueType().getVectorNumElements())) {
1955       if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1956         unsigned Element = Const->getZExtValue();
1957         return DAG.getNode(ISD::BITCAST, DL, N->getVTList(),
1958                            Arg->getOperand(0).getOperand(Element));
1959       }
1960     }
1961     break;
1962   }
1963 
1964   case ISD::SELECT_CC: {
1965     // Try common optimizations
1966     if (SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI))
1967       return Ret;
1968 
1969     // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1970     //      selectcc x, y, a, b, inv(cc)
1971     //
1972     // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1973     //      selectcc x, y, a, b, cc
1974     SDValue LHS = N->getOperand(0);
1975     if (LHS.getOpcode() != ISD::SELECT_CC) {
1976       return SDValue();
1977     }
1978 
1979     SDValue RHS = N->getOperand(1);
1980     SDValue True = N->getOperand(2);
1981     SDValue False = N->getOperand(3);
1982     ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1983 
1984     if (LHS.getOperand(2).getNode() != True.getNode() ||
1985         LHS.getOperand(3).getNode() != False.getNode() ||
1986         RHS.getNode() != False.getNode()) {
1987       return SDValue();
1988     }
1989 
1990     switch (NCC) {
1991     default: return SDValue();
1992     case ISD::SETNE: return LHS;
1993     case ISD::SETEQ: {
1994       ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1995       LHSCC = ISD::getSetCCInverse(LHSCC,
1996                                   LHS.getOperand(0).getValueType().isInteger());
1997       if (DCI.isBeforeLegalizeOps() ||
1998           isCondCodeLegal(LHSCC, LHS.getOperand(0).getSimpleValueType()))
1999         return DAG.getSelectCC(DL,
2000                                LHS.getOperand(0),
2001                                LHS.getOperand(1),
2002                                LHS.getOperand(2),
2003                                LHS.getOperand(3),
2004                                LHSCC);
2005       break;
2006     }
2007     }
2008     return SDValue();
2009   }
2010 
2011   case AMDGPUISD::R600_EXPORT: {
2012     SDValue Arg = N->getOperand(1);
2013     if (Arg.getOpcode() != ISD::BUILD_VECTOR)
2014       break;
2015 
2016     SDValue NewArgs[8] = {
2017       N->getOperand(0), // Chain
2018       SDValue(),
2019       N->getOperand(2), // ArrayBase
2020       N->getOperand(3), // Type
2021       N->getOperand(4), // SWZ_X
2022       N->getOperand(5), // SWZ_Y
2023       N->getOperand(6), // SWZ_Z
2024       N->getOperand(7) // SWZ_W
2025     };
2026     NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG, DL);
2027     return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, N->getVTList(), NewArgs);
2028   }
2029   case AMDGPUISD::TEXTURE_FETCH: {
2030     SDValue Arg = N->getOperand(1);
2031     if (Arg.getOpcode() != ISD::BUILD_VECTOR)
2032       break;
2033 
2034     SDValue NewArgs[19] = {
2035       N->getOperand(0),
2036       N->getOperand(1),
2037       N->getOperand(2),
2038       N->getOperand(3),
2039       N->getOperand(4),
2040       N->getOperand(5),
2041       N->getOperand(6),
2042       N->getOperand(7),
2043       N->getOperand(8),
2044       N->getOperand(9),
2045       N->getOperand(10),
2046       N->getOperand(11),
2047       N->getOperand(12),
2048       N->getOperand(13),
2049       N->getOperand(14),
2050       N->getOperand(15),
2051       N->getOperand(16),
2052       N->getOperand(17),
2053       N->getOperand(18),
2054     };
2055     NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG, DL);
2056     return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, N->getVTList(), NewArgs);
2057   }
2058 
2059   case ISD::LOAD: {
2060     LoadSDNode *LoadNode = cast<LoadSDNode>(N);
2061     SDValue Ptr = LoadNode->getBasePtr();
2062     if (LoadNode->getAddressSpace() == AMDGPUAS::PARAM_I_ADDRESS &&
2063          isa<ConstantSDNode>(Ptr))
2064       return constBufferLoad(LoadNode, AMDGPUAS::CONSTANT_BUFFER_0, DAG);
2065     break;
2066   }
2067 
2068   default: break;
2069   }
2070 
2071   return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
2072 }
2073 
2074 bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx,
2075                                      SDValue &Src, SDValue &Neg, SDValue &Abs,
2076                                      SDValue &Sel, SDValue &Imm,
2077                                      SelectionDAG &DAG) const {
2078   const R600InstrInfo *TII = Subtarget->getInstrInfo();
2079   if (!Src.isMachineOpcode())
2080     return false;
2081 
2082   switch (Src.getMachineOpcode()) {
2083   case R600::FNEG_R600:
2084     if (!Neg.getNode())
2085       return false;
2086     Src = Src.getOperand(0);
2087     Neg = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32);
2088     return true;
2089   case R600::FABS_R600:
2090     if (!Abs.getNode())
2091       return false;
2092     Src = Src.getOperand(0);
2093     Abs = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32);
2094     return true;
2095   case R600::CONST_COPY: {
2096     unsigned Opcode = ParentNode->getMachineOpcode();
2097     bool HasDst = TII->getOperandIdx(Opcode, R600::OpName::dst) > -1;
2098 
2099     if (!Sel.getNode())
2100       return false;
2101 
2102     SDValue CstOffset = Src.getOperand(0);
2103     if (ParentNode->getValueType(0).isVector())
2104       return false;
2105 
2106     // Gather constants values
2107     int SrcIndices[] = {
2108       TII->getOperandIdx(Opcode, R600::OpName::src0),
2109       TII->getOperandIdx(Opcode, R600::OpName::src1),
2110       TII->getOperandIdx(Opcode, R600::OpName::src2),
2111       TII->getOperandIdx(Opcode, R600::OpName::src0_X),
2112       TII->getOperandIdx(Opcode, R600::OpName::src0_Y),
2113       TII->getOperandIdx(Opcode, R600::OpName::src0_Z),
2114       TII->getOperandIdx(Opcode, R600::OpName::src0_W),
2115       TII->getOperandIdx(Opcode, R600::OpName::src1_X),
2116       TII->getOperandIdx(Opcode, R600::OpName::src1_Y),
2117       TII->getOperandIdx(Opcode, R600::OpName::src1_Z),
2118       TII->getOperandIdx(Opcode, R600::OpName::src1_W)
2119     };
2120     std::vector<unsigned> Consts;
2121     for (int OtherSrcIdx : SrcIndices) {
2122       int OtherSelIdx = TII->getSelIdx(Opcode, OtherSrcIdx);
2123       if (OtherSrcIdx < 0 || OtherSelIdx < 0)
2124         continue;
2125       if (HasDst) {
2126         OtherSrcIdx--;
2127         OtherSelIdx--;
2128       }
2129       if (RegisterSDNode *Reg =
2130           dyn_cast<RegisterSDNode>(ParentNode->getOperand(OtherSrcIdx))) {
2131         if (Reg->getReg() == R600::ALU_CONST) {
2132           ConstantSDNode *Cst
2133             = cast<ConstantSDNode>(ParentNode->getOperand(OtherSelIdx));
2134           Consts.push_back(Cst->getZExtValue());
2135         }
2136       }
2137     }
2138 
2139     ConstantSDNode *Cst = cast<ConstantSDNode>(CstOffset);
2140     Consts.push_back(Cst->getZExtValue());
2141     if (!TII->fitsConstReadLimitations(Consts)) {
2142       return false;
2143     }
2144 
2145     Sel = CstOffset;
2146     Src = DAG.getRegister(R600::ALU_CONST, MVT::f32);
2147     return true;
2148   }
2149   case R600::MOV_IMM_GLOBAL_ADDR:
2150     // Check if the Imm slot is used. Taken from below.
2151     if (cast<ConstantSDNode>(Imm)->getZExtValue())
2152       return false;
2153     Imm = Src.getOperand(0);
2154     Src = DAG.getRegister(R600::ALU_LITERAL_X, MVT::i32);
2155     return true;
2156   case R600::MOV_IMM_I32:
2157   case R600::MOV_IMM_F32: {
2158     unsigned ImmReg = R600::ALU_LITERAL_X;
2159     uint64_t ImmValue = 0;
2160 
2161     if (Src.getMachineOpcode() == R600::MOV_IMM_F32) {
2162       ConstantFPSDNode *FPC = dyn_cast<ConstantFPSDNode>(Src.getOperand(0));
2163       float FloatValue = FPC->getValueAPF().convertToFloat();
2164       if (FloatValue == 0.0) {
2165         ImmReg = R600::ZERO;
2166       } else if (FloatValue == 0.5) {
2167         ImmReg = R600::HALF;
2168       } else if (FloatValue == 1.0) {
2169         ImmReg = R600::ONE;
2170       } else {
2171         ImmValue = FPC->getValueAPF().bitcastToAPInt().getZExtValue();
2172       }
2173     } else {
2174       ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src.getOperand(0));
2175       uint64_t Value = C->getZExtValue();
2176       if (Value == 0) {
2177         ImmReg = R600::ZERO;
2178       } else if (Value == 1) {
2179         ImmReg = R600::ONE_INT;
2180       } else {
2181         ImmValue = Value;
2182       }
2183     }
2184 
2185     // Check that we aren't already using an immediate.
2186     // XXX: It's possible for an instruction to have more than one
2187     // immediate operand, but this is not supported yet.
2188     if (ImmReg == R600::ALU_LITERAL_X) {
2189       if (!Imm.getNode())
2190         return false;
2191       ConstantSDNode *C = dyn_cast<ConstantSDNode>(Imm);
2192       assert(C);
2193       if (C->getZExtValue())
2194         return false;
2195       Imm = DAG.getTargetConstant(ImmValue, SDLoc(ParentNode), MVT::i32);
2196     }
2197     Src = DAG.getRegister(ImmReg, MVT::i32);
2198     return true;
2199   }
2200   default:
2201     return false;
2202   }
2203 }
2204 
2205 /// Fold the instructions after selecting them
2206 SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node,
2207                                             SelectionDAG &DAG) const {
2208   const R600InstrInfo *TII = Subtarget->getInstrInfo();
2209   if (!Node->isMachineOpcode())
2210     return Node;
2211 
2212   unsigned Opcode = Node->getMachineOpcode();
2213   SDValue FakeOp;
2214 
2215   std::vector<SDValue> Ops(Node->op_begin(), Node->op_end());
2216 
2217   if (Opcode == R600::DOT_4) {
2218     int OperandIdx[] = {
2219       TII->getOperandIdx(Opcode, R600::OpName::src0_X),
2220       TII->getOperandIdx(Opcode, R600::OpName::src0_Y),
2221       TII->getOperandIdx(Opcode, R600::OpName::src0_Z),
2222       TII->getOperandIdx(Opcode, R600::OpName::src0_W),
2223       TII->getOperandIdx(Opcode, R600::OpName::src1_X),
2224       TII->getOperandIdx(Opcode, R600::OpName::src1_Y),
2225       TII->getOperandIdx(Opcode, R600::OpName::src1_Z),
2226       TII->getOperandIdx(Opcode, R600::OpName::src1_W)
2227         };
2228     int NegIdx[] = {
2229       TII->getOperandIdx(Opcode, R600::OpName::src0_neg_X),
2230       TII->getOperandIdx(Opcode, R600::OpName::src0_neg_Y),
2231       TII->getOperandIdx(Opcode, R600::OpName::src0_neg_Z),
2232       TII->getOperandIdx(Opcode, R600::OpName::src0_neg_W),
2233       TII->getOperandIdx(Opcode, R600::OpName::src1_neg_X),
2234       TII->getOperandIdx(Opcode, R600::OpName::src1_neg_Y),
2235       TII->getOperandIdx(Opcode, R600::OpName::src1_neg_Z),
2236       TII->getOperandIdx(Opcode, R600::OpName::src1_neg_W)
2237     };
2238     int AbsIdx[] = {
2239       TII->getOperandIdx(Opcode, R600::OpName::src0_abs_X),
2240       TII->getOperandIdx(Opcode, R600::OpName::src0_abs_Y),
2241       TII->getOperandIdx(Opcode, R600::OpName::src0_abs_Z),
2242       TII->getOperandIdx(Opcode, R600::OpName::src0_abs_W),
2243       TII->getOperandIdx(Opcode, R600::OpName::src1_abs_X),
2244       TII->getOperandIdx(Opcode, R600::OpName::src1_abs_Y),
2245       TII->getOperandIdx(Opcode, R600::OpName::src1_abs_Z),
2246       TII->getOperandIdx(Opcode, R600::OpName::src1_abs_W)
2247     };
2248     for (unsigned i = 0; i < 8; i++) {
2249       if (OperandIdx[i] < 0)
2250         return Node;
2251       SDValue &Src = Ops[OperandIdx[i] - 1];
2252       SDValue &Neg = Ops[NegIdx[i] - 1];
2253       SDValue &Abs = Ops[AbsIdx[i] - 1];
2254       bool HasDst = TII->getOperandIdx(Opcode, R600::OpName::dst) > -1;
2255       int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2256       if (HasDst)
2257         SelIdx--;
2258       SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2259       if (FoldOperand(Node, i, Src, Neg, Abs, Sel, FakeOp, DAG))
2260         return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2261     }
2262   } else if (Opcode == R600::REG_SEQUENCE) {
2263     for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) {
2264       SDValue &Src = Ops[i];
2265       if (FoldOperand(Node, i, Src, FakeOp, FakeOp, FakeOp, FakeOp, DAG))
2266         return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2267     }
2268   } else {
2269     if (!TII->hasInstrModifiers(Opcode))
2270       return Node;
2271     int OperandIdx[] = {
2272       TII->getOperandIdx(Opcode, R600::OpName::src0),
2273       TII->getOperandIdx(Opcode, R600::OpName::src1),
2274       TII->getOperandIdx(Opcode, R600::OpName::src2)
2275     };
2276     int NegIdx[] = {
2277       TII->getOperandIdx(Opcode, R600::OpName::src0_neg),
2278       TII->getOperandIdx(Opcode, R600::OpName::src1_neg),
2279       TII->getOperandIdx(Opcode, R600::OpName::src2_neg)
2280     };
2281     int AbsIdx[] = {
2282       TII->getOperandIdx(Opcode, R600::OpName::src0_abs),
2283       TII->getOperandIdx(Opcode, R600::OpName::src1_abs),
2284       -1
2285     };
2286     for (unsigned i = 0; i < 3; i++) {
2287       if (OperandIdx[i] < 0)
2288         return Node;
2289       SDValue &Src = Ops[OperandIdx[i] - 1];
2290       SDValue &Neg = Ops[NegIdx[i] - 1];
2291       SDValue FakeAbs;
2292       SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
2293       bool HasDst = TII->getOperandIdx(Opcode, R600::OpName::dst) > -1;
2294       int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2295       int ImmIdx = TII->getOperandIdx(Opcode, R600::OpName::literal);
2296       if (HasDst) {
2297         SelIdx--;
2298         ImmIdx--;
2299       }
2300       SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2301       SDValue &Imm = Ops[ImmIdx];
2302       if (FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG))
2303         return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2304     }
2305   }
2306 
2307   return Node;
2308 }
2309