1 //===-- R600AsmPrinter.cpp - R600 Assembly printer ------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 ///
11 /// The R600AsmPrinter is used to print both assembly string and also binary
12 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
13 /// an MCObjectStreamer it outputs binary code.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "R600AsmPrinter.h"
18 #include "AMDGPUSubtarget.h"
19 #include "R600Defines.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "llvm/BinaryFormat/ELF.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCSectionELF.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/Target/TargetLoweringObjectFile.h"
26 
27 using namespace llvm;
28 
29 AsmPrinter *
30 llvm::createR600AsmPrinterPass(TargetMachine &TM,
31                                std::unique_ptr<MCStreamer> &&Streamer) {
32   return new R600AsmPrinter(TM, std::move(Streamer));
33 }
34 
35 R600AsmPrinter::R600AsmPrinter(TargetMachine &TM,
36                                std::unique_ptr<MCStreamer> Streamer)
37   : AsmPrinter(TM, std::move(Streamer)) { }
38 
39 StringRef R600AsmPrinter::getPassName() const {
40   return "R600 Assembly Printer";
41 }
42 
43 void R600AsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
44   unsigned MaxGPR = 0;
45   bool killPixel = false;
46   const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>();
47   const R600RegisterInfo *RI = STM.getRegisterInfo();
48   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
49 
50   for (const MachineBasicBlock &MBB : MF) {
51     for (const MachineInstr &MI : MBB) {
52       if (MI.getOpcode() == R600::KILLGT)
53         killPixel = true;
54       unsigned numOperands = MI.getNumOperands();
55       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
56         const MachineOperand &MO = MI.getOperand(op_idx);
57         if (!MO.isReg())
58           continue;
59         unsigned HWReg = RI->getHWRegIndex(MO.getReg());
60 
61         // Register with value > 127 aren't GPR
62         if (HWReg > 127)
63           continue;
64         MaxGPR = std::max(MaxGPR, HWReg);
65       }
66     }
67   }
68 
69   unsigned RsrcReg;
70   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
71     // Evergreen / Northern Islands
72     switch (MF.getFunction().getCallingConv()) {
73     default: LLVM_FALLTHROUGH;
74     case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
75     case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
76     case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
77     case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
78     }
79   } else {
80     // R600 / R700
81     switch (MF.getFunction().getCallingConv()) {
82     default: LLVM_FALLTHROUGH;
83     case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH;
84     case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH;
85     case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
86     case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
87     }
88   }
89 
90   OutStreamer->emitInt32(RsrcReg);
91   OutStreamer->emitIntValue(S_NUM_GPRS(MaxGPR + 1) |
92                            S_STACK_SIZE(MFI->CFStackSize), 4);
93   OutStreamer->emitInt32(R_02880C_DB_SHADER_CONTROL);
94   OutStreamer->emitInt32(S_02880C_KILL_ENABLE(killPixel));
95 
96   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
97     OutStreamer->emitInt32(R_0288E8_SQ_LDS_ALLOC);
98     OutStreamer->emitIntValue(alignTo(MFI->getLDSSize(), 4) >> 2, 4);
99   }
100 }
101 
102 bool R600AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
103 
104 
105   // Functions needs to be cacheline (256B) aligned.
106   MF.ensureAlignment(Align(256));
107 
108   SetupMachineFunction(MF);
109 
110   MCContext &Context = getObjFileLowering().getContext();
111   MCSectionELF *ConfigSection =
112       Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
113   OutStreamer->SwitchSection(ConfigSection);
114 
115   EmitProgramInfoR600(MF);
116 
117   emitFunctionBody();
118 
119   if (isVerbose()) {
120     MCSectionELF *CommentSection =
121         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
122     OutStreamer->SwitchSection(CommentSection);
123 
124     R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
125     OutStreamer->emitRawComment(
126       Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->CFStackSize)));
127   }
128 
129   return false;
130 }
131 
132