1//===-- MIMGInstructions.td - MIMG Instruction Definitions ----------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// MIMG-specific encoding families to distinguish between semantically 10// equivalent machine instructions with different encoding. 11// 12// - MIMGEncGfx6: encoding introduced with gfx6 (obsoleted for atomics in gfx8) 13// - MIMGEncGfx8: encoding introduced with gfx8 for atomics 14// - MIMGEncGfx90a: encoding for gfx90a for atomics 15// - MIMGEncGfx10Default: gfx10 default (non-NSA) encoding 16// - MIMGEncGfx10NSA: gfx10 NSA encoding 17class MIMGEncoding; 18 19def MIMGEncGfx6 : MIMGEncoding; 20def MIMGEncGfx8 : MIMGEncoding; 21def MIMGEncGfx90a : MIMGEncoding; 22def MIMGEncGfx10Default : MIMGEncoding; 23def MIMGEncGfx10NSA : MIMGEncoding; 24 25def MIMGEncoding : GenericEnum { 26 let FilterClass = "MIMGEncoding"; 27} 28 29// Represent an ISA-level opcode, independent of the encoding and the 30// vdata/vaddr size. 31class MIMGBaseOpcode : PredicateControl { 32 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME); 33 bit Store = 0; 34 bit Atomic = 0; 35 bit AtomicX2 = 0; // (f)cmpswap 36 bit Sampler = 0; 37 bit Gather4 = 0; 38 bits<8> NumExtraArgs = 0; 39 bit Gradients = 0; 40 bit G16 = 0; 41 bit Coordinates = 1; 42 bit LodOrClampOrMip = 0; 43 bit HasD16 = 0; 44 bit IsAtomicRet = 0; 45} 46 47def MIMGBaseOpcode : GenericEnum { 48 let FilterClass = "MIMGBaseOpcode"; 49} 50 51def MIMGBaseOpcodesTable : GenericTable { 52 let FilterClass = "MIMGBaseOpcode"; 53 let CppTypeName = "MIMGBaseOpcodeInfo"; 54 let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler", 55 "Gather4", "NumExtraArgs", "Gradients", "G16", "Coordinates", 56 "LodOrClampOrMip", "HasD16"]; 57 string TypeOf_BaseOpcode = "MIMGBaseOpcode"; 58 59 let PrimaryKey = ["BaseOpcode"]; 60 let PrimaryKeyName = "getMIMGBaseOpcodeInfo"; 61} 62 63def MIMGDim : GenericEnum { 64 let FilterClass = "AMDGPUDimProps"; 65} 66 67def MIMGDimInfoTable : GenericTable { 68 let FilterClass = "AMDGPUDimProps"; 69 let CppTypeName = "MIMGDimInfo"; 70 let Fields = ["Dim", "NumCoords", "NumGradients", "DA", "Encoding", "AsmSuffix"]; 71 string TypeOf_Dim = "MIMGDim"; 72 73 let PrimaryKey = ["Dim"]; 74 let PrimaryKeyName = "getMIMGDimInfo"; 75} 76 77def getMIMGDimInfoByEncoding : SearchIndex { 78 let Table = MIMGDimInfoTable; 79 let Key = ["Encoding"]; 80} 81 82def getMIMGDimInfoByAsmSuffix : SearchIndex { 83 let Table = MIMGDimInfoTable; 84 let Key = ["AsmSuffix"]; 85} 86 87def MIMG { 88 int NOP = -1; 89} 90 91class mimgopc <int base, int vi = base, int si = base> { 92 field bits<8> BASE = base; // Opcode for all but atomics 93 field bits<8> VI = vi; // VI is only used for atomic instructions 94 field bits<8> SI = si; // SI is only used for atomic instructions 95 bit HAS_BASE = !ne(base, MIMG.NOP); 96 bit HAS_VI = !ne(vi, MIMG.NOP); 97 bit HAS_SI = !ne(si, MIMG.NOP); 98} 99 100class MIMGLZMapping<MIMGBaseOpcode l, MIMGBaseOpcode lz> { 101 MIMGBaseOpcode L = l; 102 MIMGBaseOpcode LZ = lz; 103} 104 105def MIMGLZMappingTable : GenericTable { 106 let FilterClass = "MIMGLZMapping"; 107 let CppTypeName = "MIMGLZMappingInfo"; 108 let Fields = ["L", "LZ"]; 109 string TypeOf_L = "MIMGBaseOpcode"; 110 string TypeOf_LZ = "MIMGBaseOpcode"; 111 112 let PrimaryKey = ["L"]; 113 let PrimaryKeyName = "getMIMGLZMappingInfo"; 114} 115 116class MIMGMIPMapping<MIMGBaseOpcode mip, MIMGBaseOpcode nonmip> { 117 MIMGBaseOpcode MIP = mip; 118 MIMGBaseOpcode NONMIP = nonmip; 119} 120 121def MIMGMIPMappingTable : GenericTable { 122 let FilterClass = "MIMGMIPMapping"; 123 let CppTypeName = "MIMGMIPMappingInfo"; 124 let Fields = ["MIP", "NONMIP"]; 125 string TypeOf_MIP = "MIMGBaseOpcode"; 126 string TypeOf_NONMIP = "MIMGBaseOpcode"; 127 128 let PrimaryKey = ["MIP"]; 129 let PrimaryKeyName = "getMIMGMIPMappingInfo"; 130} 131 132class MIMGG16Mapping<MIMGBaseOpcode g, MIMGBaseOpcode g16> { 133 MIMGBaseOpcode G = g; 134 MIMGBaseOpcode G16 = g16; 135} 136 137def MIMGG16MappingTable : GenericTable { 138 let FilterClass = "MIMGG16Mapping"; 139 let CppTypeName = "MIMGG16MappingInfo"; 140 let Fields = ["G", "G16"]; 141 string TypeOf_G = "MIMGBaseOpcode"; 142 string TypeOf_G16 = "MIMGBaseOpcode"; 143 144 let PrimaryKey = ["G"]; 145 let PrimaryKeyName = "getMIMGG16MappingInfo"; 146} 147 148class MIMG_Base <dag outs, string dns = ""> 149 : InstSI <outs, (ins), "", []> { 150 151 let VM_CNT = 1; 152 let EXP_CNT = 1; 153 let MIMG = 1; 154 let Uses = [EXEC]; 155 let mayLoad = 1; 156 let mayStore = 0; 157 let SchedRW = [WriteVMEM]; 158 let UseNamedOperandTable = 1; 159 let hasSideEffects = 0; // XXX ???? 160 161 let DecoderNamespace = dns; 162 let isAsmParserOnly = !eq(dns, ""); 163} 164 165class MIMG <dag outs, string dns = ""> 166 : MIMG_Base <outs, dns> { 167 168 let hasPostISelHook = 1; 169 let AsmMatchConverter = "cvtMIMG"; 170 171 Instruction Opcode = !cast<Instruction>(NAME); 172 MIMGBaseOpcode BaseOpcode; 173 MIMGEncoding MIMGEncoding; 174 bits<8> VDataDwords; 175 bits<8> VAddrDwords; 176} 177 178def MIMGInfoTable : GenericTable { 179 let FilterClass = "MIMG"; 180 let CppTypeName = "MIMGInfo"; 181 let Fields = ["Opcode", "BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"]; 182 string TypeOf_BaseOpcode = "MIMGBaseOpcode"; 183 string TypeOf_MIMGEncoding = "MIMGEncoding"; 184 185 let PrimaryKey = ["BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"]; 186 let PrimaryKeyName = "getMIMGOpcodeHelper"; 187} 188 189def getMIMGInfo : SearchIndex { 190 let Table = MIMGInfoTable; 191 let Key = ["Opcode"]; 192} 193 194// This class used to use !foldl to memoize the AddrAsmNames list. 195// It turned out that that was much slower than using !filter. 196class MIMGNSAHelper<int num_addrs> { 197 list<string> AddrAsmNames = 198 !foreach(i, !filter(i, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11], 199 !lt(i, num_addrs)), "vaddr" # i); 200 dag AddrIns = !dag(ins, !foreach(arg, AddrAsmNames, VGPR_32), AddrAsmNames); 201 string AddrAsm = "[$" # !interleave(AddrAsmNames, ", $") # "]"; 202 203 int NSA = !if(!le(num_addrs, 1), ?, 204 !if(!le(num_addrs, 5), 1, 205 !if(!le(num_addrs, 9), 2, 206 !if(!le(num_addrs, 13), 3, ?)))); 207} 208 209// Base class of all pre-gfx10 MIMG instructions. 210class MIMG_gfx6789<bits<8> op, dag outs, string dns = ""> 211 : MIMG<outs, dns>, MIMGe_gfx6789<op> { 212 let SubtargetPredicate = isGFX6GFX7GFX8GFX9NotGFX90A; 213 let AssemblerPredicate = isGFX6GFX7GFX8GFX9NotGFX90A; 214 215 let MIMGEncoding = MIMGEncGfx6; 216 217 let d16 = !if(BaseOpcode.HasD16, ?, 0); 218} 219 220class MIMG_gfx90a<bits<8> op, dag outs, string dns = ""> 221 : MIMG<outs, dns>, MIMGe_gfx90a<op> { 222 let SubtargetPredicate = isGFX90APlus; 223 let AssemblerPredicate = isGFX90APlus; 224 225 let MIMGEncoding = MIMGEncGfx90a; 226 227 let d16 = !if(BaseOpcode.HasD16, ?, 0); 228} 229 230// Base class of all non-NSA gfx10 MIMG instructions. 231class MIMG_gfx10<int op, dag outs, string dns = ""> 232 : MIMG<outs, dns>, MIMGe_gfx10<op> { 233 let SubtargetPredicate = isGFX10Plus; 234 let AssemblerPredicate = isGFX10Plus; 235 236 let MIMGEncoding = MIMGEncGfx10Default; 237 238 let d16 = !if(BaseOpcode.HasD16, ?, 0); 239 let nsa = 0; 240} 241 242// Base class for all NSA MIMG instructions. 243// Note that 1-dword addresses always use non-NSA variants. 244class MIMG_nsa_gfx10<int op, dag outs, int num_addrs, string dns=""> 245 : MIMG<outs, dns>, MIMGe_gfx10<op> { 246 let SubtargetPredicate = isGFX10Plus; 247 let AssemblerPredicate = isGFX10Plus; 248 249 let MIMGEncoding = MIMGEncGfx10NSA; 250 251 MIMGNSAHelper nsah = MIMGNSAHelper<num_addrs>; 252 dag AddrIns = nsah.AddrIns; 253 string AddrAsm = nsah.AddrAsm; 254 255 let d16 = !if(BaseOpcode.HasD16, ?, 0); 256 let nsa = nsah.NSA; 257} 258 259class MIMG_NoSampler_Helper <mimgopc op, string asm, 260 RegisterClass dst_rc, 261 RegisterClass addr_rc, 262 string dns=""> 263 : MIMG_gfx6789 <op.BASE, (outs dst_rc:$vdata), dns> { 264 let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc, 265 DMask:$dmask, UNorm:$unorm, SCCB_0:$sccb, GLC:$glc, SLC:$slc, 266 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 267 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 268 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$sccb$glc$slc$r128$tfe$lwe$da" 269 #!if(BaseOpcode.HasD16, "$d16", ""); 270} 271 272class MIMG_NoSampler_Helper_gfx90a <mimgopc op, string asm, 273 RegisterClass dst_rc, 274 RegisterClass addr_rc, 275 string dns=""> 276 : MIMG_gfx90a <op.BASE, (outs getLdStRegisterOperand<dst_rc>.ret:$vdata), dns> { 277 let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc, 278 DMask:$dmask, UNorm:$unorm, SCCB_0:$sccb, GLC:$glc, SLC:$slc, 279 R128A16:$r128, LWE:$lwe, DA:$da), 280 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 281 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$sccb$glc$slc$r128$lwe$da" 282 #!if(BaseOpcode.HasD16, "$d16", ""); 283} 284 285class MIMG_NoSampler_gfx10<mimgopc op, string opcode, 286 RegisterClass DataRC, RegisterClass AddrRC, 287 string dns=""> 288 : MIMG_gfx10<op.BASE, (outs DataRC:$vdata), dns> { 289 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask, 290 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, 291 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 292 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 293 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe" 294 #!if(BaseOpcode.HasD16, "$d16", ""); 295} 296 297class MIMG_NoSampler_nsa_gfx10<mimgopc op, string opcode, 298 RegisterClass DataRC, int num_addrs, 299 string dns=""> 300 : MIMG_nsa_gfx10<op.BASE, (outs DataRC:$vdata), num_addrs, dns> { 301 let InOperandList = !con(AddrIns, 302 (ins SReg_256:$srsrc, DMask:$dmask, 303 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, 304 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 305 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 306 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe" 307 #!if(BaseOpcode.HasD16, "$d16", ""); 308} 309 310multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm, 311 RegisterClass dst_rc, 312 bit enableDisasm, 313 bit ExtendedImageInst = 1> { 314 let ssamp = 0 in { 315 let VAddrDwords = 1 in { 316 if op.HAS_BASE then { 317 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32, 318 !if(enableDisasm, "AMDGPU", "")>; 319 foreach _ = BoolToList<!eq(ExtendedImageInst, 0)>.ret in 320 def _V1_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPR_32, 321 !if(enableDisasm, "GFX90A", "")>; 322 def _V1_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPR_32, 323 !if(enableDisasm, "AMDGPU", "")>; 324 } 325 } 326 327 let VAddrDwords = 2 in { 328 if op.HAS_BASE then { 329 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>; 330 foreach _ = BoolToList<!eq(ExtendedImageInst, 0)>.ret in 331 def _V2_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_64>; 332 def _V2_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_64>; 333 def _V2_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 2>; 334 } 335 } 336 337 let VAddrDwords = 3 in { 338 if op.HAS_BASE then { 339 def _V3 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_96>; 340 foreach _ = BoolToList<!eq(ExtendedImageInst, 0)>.ret in 341 def _V3_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_96>; 342 def _V3_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_96>; 343 def _V3_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 3>; 344 } 345 } 346 347 let VAddrDwords = 4 in { 348 if op.HAS_BASE then { 349 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>; 350 foreach _ = BoolToList<!eq(ExtendedImageInst, 0)>.ret in 351 def _V4_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_128>; 352 def _V4_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_128>; 353 def _V4_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 4, 354 !if(enableDisasm, "AMDGPU", "")>; 355 } 356 } 357 } 358} 359 360multiclass MIMG_NoSampler <mimgopc op, string asm, bit has_d16, bit mip = 0, 361 bit isResInfo = 0, 362 bit msaa = 0> { 363 def "" : MIMGBaseOpcode { 364 let Coordinates = !not(isResInfo); 365 let LodOrClampOrMip = mip; 366 let HasD16 = has_d16; 367 } 368 369 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), 370 mayLoad = !not(isResInfo) in { 371 let VDataDwords = 1 in 372 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1, msaa>; 373 let VDataDwords = 2 in 374 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 0, msaa>; 375 let VDataDwords = 3 in 376 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 0, msaa>; 377 let VDataDwords = 4 in 378 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 0, msaa>; 379 let VDataDwords = 5 in 380 defm _V5 : MIMG_NoSampler_Src_Helper <op, asm, VReg_160, 0, msaa>; 381 } 382} 383 384class MIMG_Store_Helper <mimgopc op, string asm, 385 RegisterClass data_rc, 386 RegisterClass addr_rc, 387 string dns = ""> 388 : MIMG_gfx6789<op.BASE, (outs), dns> { 389 let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, 390 DMask:$dmask, UNorm:$unorm, SCCB_0:$sccb, GLC:$glc, SLC:$slc, 391 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 392 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 393 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$sccb$glc$slc$r128$tfe$lwe$da" 394 #!if(BaseOpcode.HasD16, "$d16", ""); 395} 396 397class MIMG_Store_Helper_gfx90a <mimgopc op, string asm, 398 RegisterClass data_rc, 399 RegisterClass addr_rc, 400 string dns = ""> 401 : MIMG_gfx90a<op.BASE, (outs), dns> { 402 let InOperandList = !con((ins getLdStRegisterOperand<data_rc>.ret:$vdata, 403 addr_rc:$vaddr, SReg_256:$srsrc, 404 DMask:$dmask, UNorm:$unorm, SCCB_0:$sccb, GLC:$glc, SLC:$slc, 405 R128A16:$r128, LWE:$lwe, DA:$da), 406 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 407 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$sccb$glc$slc$r128$lwe$da" 408 #!if(BaseOpcode.HasD16, "$d16", ""); 409} 410 411class MIMG_Store_gfx10<mimgopc op, string opcode, 412 RegisterClass DataRC, RegisterClass AddrRC, 413 string dns=""> 414 : MIMG_gfx10<op.BASE, (outs), dns> { 415 let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc, 416 DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc, 417 GLC:$glc, SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 418 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 419 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe" 420 #!if(BaseOpcode.HasD16, "$d16", ""); 421} 422 423class MIMG_Store_nsa_gfx10<mimgopc op, string opcode, 424 RegisterClass DataRC, int num_addrs, 425 string dns=""> 426 : MIMG_nsa_gfx10<op.BASE, (outs), num_addrs, dns> { 427 let InOperandList = !con((ins DataRC:$vdata), 428 AddrIns, 429 (ins SReg_256:$srsrc, DMask:$dmask, 430 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, 431 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 432 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 433 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe" 434 #!if(BaseOpcode.HasD16, "$d16", ""); 435} 436 437multiclass MIMG_Store_Addr_Helper <mimgopc op, string asm, 438 RegisterClass data_rc, 439 bit enableDisasm> { 440 let mayLoad = 0, mayStore = 1, hasSideEffects = 0, hasPostISelHook = 0, 441 DisableWQM = 1, ssamp = 0 in { 442 let VAddrDwords = 1 in { 443 if op.HAS_BASE then { 444 def _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32, 445 !if(enableDisasm, "AMDGPU", "")>; 446 def _V1_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VGPR_32, 447 !if(enableDisasm, "GFX90A", "")>; 448 def _V1_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VGPR_32, 449 !if(enableDisasm, "AMDGPU", "")>; 450 } 451 } 452 let VAddrDwords = 2 in { 453 if op.HAS_BASE then { 454 def _V2 : MIMG_Store_Helper <op, asm, data_rc, VReg_64>; 455 def _V2_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_64>; 456 def _V2_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_64>; 457 def _V2_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 2>; 458 } 459 } 460 let VAddrDwords = 3 in { 461 if op.HAS_BASE then { 462 def _V3 : MIMG_Store_Helper <op, asm, data_rc, VReg_96>; 463 def _V3_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_96>; 464 def _V3_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_96>; 465 def _V3_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 3>; 466 } 467 } 468 let VAddrDwords = 4 in { 469 if op.HAS_BASE then { 470 def _V4 : MIMG_Store_Helper <op, asm, data_rc, VReg_128>; 471 def _V4_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_128>; 472 def _V4_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_128>; 473 def _V4_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 4, 474 !if(enableDisasm, "AMDGPU", "")>; 475 } 476 } 477 } 478} 479 480multiclass MIMG_Store <mimgopc op, string asm, bit has_d16, bit mip = 0> { 481 def "" : MIMGBaseOpcode { 482 let Store = 1; 483 let LodOrClampOrMip = mip; 484 let HasD16 = has_d16; 485 } 486 487 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in { 488 let VDataDwords = 1 in 489 defm _V1 : MIMG_Store_Addr_Helper <op, asm, VGPR_32, 1>; 490 let VDataDwords = 2 in 491 defm _V2 : MIMG_Store_Addr_Helper <op, asm, VReg_64, 0>; 492 let VDataDwords = 3 in 493 defm _V3 : MIMG_Store_Addr_Helper <op, asm, VReg_96, 0>; 494 let VDataDwords = 4 in 495 defm _V4 : MIMG_Store_Addr_Helper <op, asm, VReg_128, 0>; 496 let VDataDwords = 5 in 497 defm _V5 : MIMG_Store_Addr_Helper <op, asm, VReg_160, 0>; 498 } 499} 500 501class MIMG_Atomic_gfx6789_base <bits<8> op, string asm, RegisterClass data_rc, 502 RegisterClass addr_rc, string dns=""> 503 : MIMG_gfx6789 <op, (outs data_rc:$vdst), dns> { 504 let Constraints = "$vdst = $vdata"; 505 let AsmMatchConverter = "cvtMIMGAtomic"; 506 507 let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, 508 DMask:$dmask, UNorm:$unorm, SCCB_0:$sccb, GLC:$glc, SLC:$slc, 509 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da); 510 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$sccb$glc$slc$r128$tfe$lwe$da"; 511} 512 513class MIMG_Atomic_gfx90a_base <bits<8> op, string asm, RegisterClass data_rc, 514 RegisterClass addr_rc, string dns=""> 515 : MIMG_gfx90a <op, (outs getLdStRegisterOperand<data_rc>.ret:$vdst), dns> { 516 let Constraints = "$vdst = $vdata"; 517 let AsmMatchConverter = "cvtMIMGAtomic"; 518 519 let InOperandList = (ins getLdStRegisterOperand<data_rc>.ret:$vdata, 520 addr_rc:$vaddr, SReg_256:$srsrc, 521 DMask:$dmask, UNorm:$unorm, SCCB_0:$sccb, GLC:$glc, SLC:$slc, 522 R128A16:$r128, LWE:$lwe, DA:$da); 523 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$sccb$glc$slc$r128$lwe$da"; 524} 525 526class MIMG_Atomic_si<mimgopc op, string asm, RegisterClass data_rc, 527 RegisterClass addr_rc, bit enableDasm = 0> 528 : MIMG_Atomic_gfx6789_base<op.SI, asm, data_rc, addr_rc, 529 !if(enableDasm, "GFX6GFX7", "")> { 530 let AssemblerPredicate = isGFX6GFX7; 531} 532 533class MIMG_Atomic_vi<mimgopc op, string asm, RegisterClass data_rc, 534 RegisterClass addr_rc, bit enableDasm = 0> 535 : MIMG_Atomic_gfx6789_base<op.VI, asm, data_rc, addr_rc, !if(enableDasm, "GFX8", "")> { 536 let AssemblerPredicate = isGFX8GFX9NotGFX90A; 537 let MIMGEncoding = MIMGEncGfx8; 538} 539 540class MIMG_Atomic_gfx90a<mimgopc op, string asm, RegisterClass data_rc, 541 RegisterClass addr_rc, bit enableDasm = 0> 542 : MIMG_Atomic_gfx90a_base<op.VI, asm, data_rc, addr_rc, !if(enableDasm, "GFX90A", "")> { 543 let AssemblerPredicate = isGFX90APlus; 544 let MIMGEncoding = MIMGEncGfx90a; 545} 546 547class MIMG_Atomic_gfx10<mimgopc op, string opcode, 548 RegisterClass DataRC, RegisterClass AddrRC, 549 bit enableDisasm = 0> 550 : MIMG_gfx10<!cast<int>(op.BASE), (outs DataRC:$vdst), 551 !if(enableDisasm, "AMDGPU", "")> { 552 let Constraints = "$vdst = $vdata"; 553 let AsmMatchConverter = "cvtMIMGAtomic"; 554 555 let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc, 556 DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc, 557 GLC:$glc, SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe); 558 let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe"; 559} 560 561class MIMG_Atomic_nsa_gfx10<mimgopc op, string opcode, 562 RegisterClass DataRC, int num_addrs, 563 bit enableDisasm = 0> 564 : MIMG_nsa_gfx10<!cast<int>(op.BASE), (outs DataRC:$vdst), num_addrs, 565 !if(enableDisasm, "AMDGPU", "")> { 566 let Constraints = "$vdst = $vdata"; 567 let AsmMatchConverter = "cvtMIMGAtomic"; 568 569 let InOperandList = !con((ins DataRC:$vdata), 570 AddrIns, 571 (ins SReg_256:$srsrc, DMask:$dmask, 572 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, 573 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe)); 574 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe"; 575} 576 577multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm, 578 RegisterClass data_rc, 579 bit enableDasm = 0, 580 bit isFP = 0> { 581 let hasSideEffects = 1, // FIXME: remove this 582 mayLoad = 1, mayStore = 1, hasPostISelHook = 0, DisableWQM = 1, 583 ssamp = 0, FPAtomic = isFP in { 584 let VAddrDwords = 1 in { 585 if op.HAS_SI then { 586 def _V1_si : MIMG_Atomic_si <op, asm, data_rc, VGPR_32, enableDasm>; 587 } 588 if op.HAS_VI then { 589 def _V1_vi : MIMG_Atomic_vi <op, asm, data_rc, VGPR_32, enableDasm>; 590 def _V1_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VGPR_32, enableDasm>; 591 } 592 if op.HAS_BASE then { 593 def _V1_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VGPR_32, enableDasm>; 594 } 595 } 596 let VAddrDwords = 2 in { 597 if op.HAS_SI then { 598 def _V2_si : MIMG_Atomic_si <op, asm, data_rc, VReg_64, 0>; 599 } 600 if op.HAS_VI then { 601 def _V2_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_64, 0>; 602 def _V2_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_64, 0>; 603 } 604 if op.HAS_BASE then { 605 def _V2_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_64, 0>; 606 def _V2_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 2, 0>; 607 } 608 } 609 let VAddrDwords = 3 in { 610 if op.HAS_SI then { 611 def _V3_si : MIMG_Atomic_si <op, asm, data_rc, VReg_96, 0>; 612 } 613 if op.HAS_VI then { 614 def _V3_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_96, 0>; 615 def _V3_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_96, 0>; 616 } 617 if op.HAS_BASE then { 618 def _V3_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_96, 0>; 619 def _V3_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 3, 0>; 620 } 621 } 622 let VAddrDwords = 4 in { 623 if op.HAS_SI then { 624 def _V4_si : MIMG_Atomic_si <op, asm, data_rc, VReg_128, 0>; 625 } 626 if op.HAS_VI then { 627 def _V4_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_128, 0>; 628 def _V4_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_128, 0>; 629 } 630 if op.HAS_BASE then { 631 def _V4_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_128, 0>; 632 def _V4_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 4, enableDasm>; 633 } 634 } 635 } 636} 637 638multiclass MIMG_Atomic <mimgopc op, string asm, bit isCmpSwap = 0, bit isFP = 0> { // 64-bit atomics 639 let IsAtomicRet = 1 in { 640 def "" : MIMGBaseOpcode { 641 let Atomic = 1; 642 let AtomicX2 = isCmpSwap; 643 } 644 645 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in { 646 // _V* variants have different dst size, but the size is encoded implicitly, 647 // using dmask and tfe. Only 32-bit variant is registered with disassembler. 648 // Other variants are reconstructed by disassembler using dmask and tfe. 649 let VDataDwords = !if(isCmpSwap, 2, 1) in 650 defm _V1 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_64, VGPR_32), 1, isFP>; 651 let VDataDwords = !if(isCmpSwap, 4, 2) in 652 defm _V2 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_128, VReg_64), 0, isFP>; 653 } 654 } // End IsAtomicRet = 1 655} 656 657class MIMG_Sampler_Helper <mimgopc op, string asm, RegisterClass dst_rc, 658 RegisterClass src_rc, string dns=""> 659 : MIMG_gfx6789 <op.BASE, (outs dst_rc:$vdata), dns> { 660 let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp, 661 DMask:$dmask, UNorm:$unorm, SCCB_0:$sccb, GLC:$glc, SLC:$slc, 662 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 663 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 664 let AsmString = asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$sccb$glc$slc$r128$tfe$lwe$da" 665 #!if(BaseOpcode.HasD16, "$d16", ""); 666} 667 668class MIMG_Sampler_gfx90a<mimgopc op, string asm, RegisterClass dst_rc, 669 RegisterClass src_rc, string dns=""> 670 : MIMG_gfx90a<op.BASE, (outs getLdStRegisterOperand<dst_rc>.ret:$vdata), dns> { 671 let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp, 672 DMask:$dmask, UNorm:$unorm, SCCB_0:$sccb, GLC:$glc, SLC:$slc, 673 R128A16:$r128, LWE:$lwe, DA:$da), 674 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 675 let AsmString = asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$sccb$glc$slc$r128$lwe$da" 676 #!if(BaseOpcode.HasD16, "$d16", ""); 677} 678 679class MIMG_Sampler_gfx10<mimgopc op, string opcode, 680 RegisterClass DataRC, RegisterClass AddrRC, 681 string dns=""> 682 : MIMG_gfx10<op.BASE, (outs DataRC:$vdata), dns> { 683 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, SReg_128:$ssamp, 684 DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc, 685 GLC:$glc, SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 686 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 687 let AsmString = opcode#" $vdata, $vaddr0, $srsrc, $ssamp$dmask$dim$unorm" 688 #"$dlc$glc$slc$r128$a16$tfe$lwe" 689 #!if(BaseOpcode.HasD16, "$d16", ""); 690} 691 692class MIMG_Sampler_nsa_gfx10<mimgopc op, string opcode, 693 RegisterClass DataRC, int num_addrs, 694 string dns=""> 695 : MIMG_nsa_gfx10<op.BASE, (outs DataRC:$vdata), num_addrs, dns> { 696 let InOperandList = !con(AddrIns, 697 (ins SReg_256:$srsrc, SReg_128:$ssamp, DMask:$dmask, 698 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, 699 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 700 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 701 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc, $ssamp$dmask$dim$unorm" 702 #"$dlc$glc$slc$r128$a16$tfe$lwe" 703 #!if(BaseOpcode.HasD16, "$d16", ""); 704} 705 706class MIMGAddrSize<int dw, bit enable_disasm> { 707 int NumWords = dw; 708 709 RegisterClass RegClass = !if(!le(NumWords, 0), ?, 710 !if(!eq(NumWords, 1), VGPR_32, 711 !if(!eq(NumWords, 2), VReg_64, 712 !if(!eq(NumWords, 3), VReg_96, 713 !if(!eq(NumWords, 4), VReg_128, 714 !if(!le(NumWords, 8), VReg_256, 715 !if(!le(NumWords, 16), VReg_512, ?))))))); 716 717 // Whether the instruction variant with this vaddr size should be enabled for 718 // the auto-generated disassembler. 719 bit Disassemble = enable_disasm; 720} 721 722// Return whether x is in lst. 723class isIntInList<int x, list<int> lst> { 724 bit ret = !foldl(0, lst, lhs, y, !or(lhs, !eq(x, y))); 725} 726 727// Return whether a value inside the range [min, max] (endpoints inclusive) 728// is in the given list. 729class isRangeInList<int min, int max, list<int> lst> { 730 bit ret = !foldl(0, lst, lhs, y, !or(lhs, !and(!le(min, y), !le(y, max)))); 731} 732 733class MIMGAddrSizes_tmp<list<MIMGAddrSize> lst, int min> { 734 list<MIMGAddrSize> List = lst; 735 int Min = min; 736} 737 738class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample> { 739 // List of all possible numbers of address words, taking all combinations of 740 // A16 and image dimension into account (note: no MSAA, since this is for 741 // sample/gather ops). 742 list<int> AllNumAddrWords = 743 !foreach(dw, !if(sample.Gradients, 744 !if(!eq(sample.LodOrClamp, ""), 745 [2, 3, 4, 5, 6, 7, 9], 746 [2, 3, 4, 5, 7, 8, 10]), 747 !if(!eq(sample.LodOrClamp, ""), 748 [1, 2, 3], 749 [1, 2, 3, 4])), 750 !add(dw, !size(sample.ExtraAddrArgs))); 751 752 // Generate machine instructions based on possible register classes for the 753 // required numbers of address words. The disassembler defaults to the 754 // smallest register class. 755 list<MIMGAddrSize> MachineInstrs = 756 !foldl(MIMGAddrSizes_tmp<[], 0>, [1, 2, 3, 4, 8, 16], lhs, dw, 757 !if(isRangeInList<lhs.Min, dw, AllNumAddrWords>.ret, 758 MIMGAddrSizes_tmp< 759 !listconcat(lhs.List, [MIMGAddrSize<dw, !empty(lhs.List)>]), 760 !if(!eq(dw, 3), 3, !add(dw, 1))>, // we still need _V4 for codegen w/ 3 dwords 761 lhs)).List; 762 763 // For NSA, generate machine instructions for all possible numbers of words 764 // except 1 (which is already covered by the non-NSA case). 765 // The disassembler defaults to the largest number of arguments among the 766 // variants with the same number of NSA words, and custom code then derives 767 // the exact variant based on the sample variant and the image dimension. 768 list<MIMGAddrSize> NSAInstrs = 769 !foldl([]<MIMGAddrSize>, [[12, 11, 10], [9, 8, 7, 6], [5, 4, 3, 2]], prev, nsa_group, 770 !listconcat(prev, 771 !foldl([]<MIMGAddrSize>, nsa_group, lhs, dw, 772 !if(isIntInList<dw, AllNumAddrWords>.ret, 773 !listconcat(lhs, [MIMGAddrSize<dw, !empty(lhs)>]), 774 lhs)))); 775} 776 777multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm, 778 AMDGPUSampleVariant sample, RegisterClass dst_rc, 779 bit enableDisasm = 0, 780 bit ExtendedImageInst = 1> { 781 foreach addr = MIMG_Sampler_AddrSizes<sample>.MachineInstrs in { 782 let VAddrDwords = addr.NumWords in { 783 if op.HAS_BASE then { 784 def _V # addr.NumWords 785 : MIMG_Sampler_Helper <op, asm, dst_rc, addr.RegClass, 786 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 787 foreach _ = BoolToList<!eq(ExtendedImageInst, 0)>.ret in 788 def _V # addr.NumWords # _gfx90a 789 : MIMG_Sampler_gfx90a <op, asm, dst_rc, addr.RegClass, 790 !if(!and(enableDisasm, addr.Disassemble), "GFX90A", "")>; 791 def _V # addr.NumWords # _gfx10 792 : MIMG_Sampler_gfx10 <op, asm, dst_rc, addr.RegClass, 793 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 794 } 795 } 796 } 797 798 foreach addr = MIMG_Sampler_AddrSizes<sample>.NSAInstrs in { 799 let VAddrDwords = addr.NumWords in { 800 if op.HAS_BASE then { 801 def _V # addr.NumWords # _nsa_gfx10 802 : MIMG_Sampler_nsa_gfx10<op, asm, dst_rc, addr.NumWords, 803 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 804 } 805 } 806 } 807} 808 809class MIMG_Sampler_BaseOpcode<AMDGPUSampleVariant sample> 810 : MIMGBaseOpcode { 811 let Sampler = 1; 812 let NumExtraArgs = !size(sample.ExtraAddrArgs); 813 let Gradients = sample.Gradients; 814 let LodOrClampOrMip = !ne(sample.LodOrClamp, ""); 815} 816 817multiclass MIMG_Sampler <mimgopc op, AMDGPUSampleVariant sample, bit wqm = 0, 818 bit isG16 = 0, bit isGetLod = 0, 819 string asm = "image_sample"#sample.LowerCaseMod#!if(isG16, "_g16", ""), 820 bit ExtendedImageInst = !ne(sample.LowerCaseMod, "")> { 821 def "" : MIMG_Sampler_BaseOpcode<sample> { 822 let HasD16 = !not(isGetLod); 823 let G16 = isG16; 824 } 825 826 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm, 827 mayLoad = !not(isGetLod) in { 828 let VDataDwords = 1 in 829 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, sample, VGPR_32, 1, ExtendedImageInst>; 830 let VDataDwords = 2 in 831 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64, 0, ExtendedImageInst>; 832 let VDataDwords = 3 in 833 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_96, 0, ExtendedImageInst>; 834 let VDataDwords = 4 in 835 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 0, ExtendedImageInst>; 836 let VDataDwords = 5 in 837 defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160, 0, ExtendedImageInst>; 838 } 839} 840 841multiclass MIMG_Sampler_WQM <mimgopc op, AMDGPUSampleVariant sample> 842 : MIMG_Sampler<op, sample, 1>; 843 844multiclass MIMG_Gather <mimgopc op, AMDGPUSampleVariant sample, bit wqm = 0, 845 string asm = "image_gather4"#sample.LowerCaseMod> { 846 def "" : MIMG_Sampler_BaseOpcode<sample> { 847 let HasD16 = 1; 848 let Gather4 = 1; 849 } 850 851 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm, 852 Gather4 = 1, hasPostISelHook = 0 in { 853 let VDataDwords = 2 in 854 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64>; /* for packed D16 only */ 855 let VDataDwords = 4 in 856 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 1>; 857 let VDataDwords = 5 in 858 defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160>; 859 } 860} 861 862multiclass MIMG_Gather_WQM <mimgopc op, AMDGPUSampleVariant sample> 863 : MIMG_Gather<op, sample, 1>; 864 865class MIMG_IntersectRay_gfx10<mimgopc op, string opcode, RegisterClass AddrRC, bit A16> 866 : MIMG_gfx10<op.BASE, (outs VReg_128:$vdata), "AMDGPU"> { 867 868 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_128:$srsrc), 869 !if(A16, (ins GFX10A16:$a16), (ins))); 870 let AsmString = opcode#" $vdata, $vaddr0, $srsrc"#!if(A16, "$a16", ""); 871 872 let nsa = 0; 873} 874 875class MIMG_IntersectRay_nsa_gfx10<mimgopc op, string opcode, int num_addrs, bit A16> 876 : MIMG_nsa_gfx10<op.BASE, (outs VReg_128:$vdata), num_addrs, "AMDGPU"> { 877 let InOperandList = !con(nsah.AddrIns, 878 (ins SReg_128:$srsrc), 879 !if(A16, (ins GFX10A16:$a16), (ins))); 880 let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc"#!if(A16, "$a16", ""); 881} 882 883multiclass MIMG_IntersectRay<mimgopc op, string opcode, int num_addrs, bit A16> { 884 def "" : MIMGBaseOpcode; 885 let SubtargetPredicate = HasGFX10_BEncoding, 886 AssemblerPredicate = HasGFX10_BEncoding, 887 AsmMatchConverter = !if(A16, "cvtIntersectRay", ""), 888 dmask = 0xf, 889 unorm = 1, 890 d16 = 0, 891 glc = 0, 892 slc = 0, 893 dlc = 0, 894 tfe = 0, 895 lwe = 0, 896 r128 = 1, 897 ssamp = 0, 898 dim = {0, 0, 0}, 899 a16 = A16, 900 d16 = 0, 901 BaseOpcode = !cast<MIMGBaseOpcode>(NAME), 902 VDataDwords = 4 in { 903 // TODO: MIMGAddrSize will choose VReg_512 which is a 16 register tuple, 904 // when we only need 9, 11 or 12 depending on A16 field and ptr size. 905 def "_sa" : MIMG_IntersectRay_gfx10<op, opcode, MIMGAddrSize<num_addrs, 0>.RegClass, A16> { 906 let VAddrDwords = !srl(MIMGAddrSize<num_addrs, 0>.RegClass.Size, 5); 907 } 908 def _nsa : MIMG_IntersectRay_nsa_gfx10<op, opcode, num_addrs, A16> { 909 let VAddrDwords = num_addrs; 910 } 911 } 912} 913 914//===----------------------------------------------------------------------===// 915// MIMG Instructions 916//===----------------------------------------------------------------------===// 917defm IMAGE_LOAD : MIMG_NoSampler <mimgopc<0x00>, "image_load", 1>; 918defm IMAGE_LOAD_MIP : MIMG_NoSampler <mimgopc<0x01>, "image_load_mip", 1, 1>; 919defm IMAGE_LOAD_PCK : MIMG_NoSampler <mimgopc<0x02>, "image_load_pck", 0>; 920defm IMAGE_LOAD_PCK_SGN : MIMG_NoSampler <mimgopc<0x03>, "image_load_pck_sgn", 0>; 921defm IMAGE_LOAD_MIP_PCK : MIMG_NoSampler <mimgopc<0x04>, "image_load_mip_pck", 0, 1>; 922defm IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoSampler <mimgopc<0x05>, "image_load_mip_pck_sgn", 0, 1>; 923defm IMAGE_STORE : MIMG_Store <mimgopc<0x08>, "image_store", 1>; 924defm IMAGE_STORE_MIP : MIMG_Store <mimgopc<0x09>, "image_store_mip", 1, 1>; 925defm IMAGE_STORE_PCK : MIMG_Store <mimgopc<0x0a>, "image_store_pck", 0>; 926defm IMAGE_STORE_MIP_PCK : MIMG_Store <mimgopc<0x0b>, "image_store_mip_pck", 0, 1>; 927 928defm IMAGE_GET_RESINFO : MIMG_NoSampler <mimgopc<0x0e>, "image_get_resinfo", 0, 1, 1>; 929 930defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimgopc<0x0f, 0x10, 0x0f>, "image_atomic_swap">; 931defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimgopc<0x10, 0x11, 0x10>, "image_atomic_cmpswap", 1>; 932defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimgopc<0x11, 0x12, 0x11>, "image_atomic_add">; 933defm IMAGE_ATOMIC_SUB : MIMG_Atomic <mimgopc<0x12, 0x13, 0x12>, "image_atomic_sub">; 934defm IMAGE_ATOMIC_RSUB : MIMG_Atomic <mimgopc<MIMG.NOP, MIMG.NOP, 0x13>, "image_atomic_rsub">; 935defm IMAGE_ATOMIC_SMIN : MIMG_Atomic <mimgopc<0x14>, "image_atomic_smin">; 936defm IMAGE_ATOMIC_UMIN : MIMG_Atomic <mimgopc<0x15>, "image_atomic_umin">; 937defm IMAGE_ATOMIC_SMAX : MIMG_Atomic <mimgopc<0x16>, "image_atomic_smax">; 938defm IMAGE_ATOMIC_UMAX : MIMG_Atomic <mimgopc<0x17>, "image_atomic_umax">; 939defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimgopc<0x18>, "image_atomic_and">; 940defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimgopc<0x19>, "image_atomic_or">; 941defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimgopc<0x1a>, "image_atomic_xor">; 942defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimgopc<0x1b>, "image_atomic_inc">; 943defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimgopc<0x1c>, "image_atomic_dec">; 944defm IMAGE_ATOMIC_FCMPSWAP : MIMG_Atomic <mimgopc<0x1d, MIMG.NOP>, "image_atomic_fcmpswap", 0, 1>; 945defm IMAGE_ATOMIC_FMIN : MIMG_Atomic <mimgopc<0x1e, MIMG.NOP>, "image_atomic_fmin", 0, 1>; 946defm IMAGE_ATOMIC_FMAX : MIMG_Atomic <mimgopc<0x1f, MIMG.NOP>, "image_atomic_fmax", 0, 1>; 947 948defm IMAGE_SAMPLE : MIMG_Sampler_WQM <mimgopc<0x20>, AMDGPUSample>; 949let OtherPredicates = [HasExtendedImageInsts] in { 950defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <mimgopc<0x21>, AMDGPUSample_cl>; 951defm IMAGE_SAMPLE_D : MIMG_Sampler <mimgopc<0x22>, AMDGPUSample_d>; 952defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <mimgopc<0x23>, AMDGPUSample_d_cl>; 953defm IMAGE_SAMPLE_D_G16 : MIMG_Sampler <mimgopc<0xa2>, AMDGPUSample_d, 0, 1>; 954defm IMAGE_SAMPLE_D_CL_G16 : MIMG_Sampler <mimgopc<0xa3>, AMDGPUSample_d_cl, 0, 1>; 955defm IMAGE_SAMPLE_L : MIMG_Sampler <mimgopc<0x24>, AMDGPUSample_l>; 956defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <mimgopc<0x25>, AMDGPUSample_b>; 957defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <mimgopc<0x26>, AMDGPUSample_b_cl>; 958defm IMAGE_SAMPLE_LZ : MIMG_Sampler <mimgopc<0x27>, AMDGPUSample_lz>; 959defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <mimgopc<0x28>, AMDGPUSample_c>; 960defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <mimgopc<0x29>, AMDGPUSample_c_cl>; 961defm IMAGE_SAMPLE_C_D : MIMG_Sampler <mimgopc<0x2a>, AMDGPUSample_c_d>; 962defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <mimgopc<0x2b>, AMDGPUSample_c_d_cl>; 963defm IMAGE_SAMPLE_C_D_G16 : MIMG_Sampler <mimgopc<0xaa>, AMDGPUSample_c_d, 0, 1>; 964defm IMAGE_SAMPLE_C_D_CL_G16 : MIMG_Sampler <mimgopc<0xab>, AMDGPUSample_c_d_cl, 0, 1>; 965defm IMAGE_SAMPLE_C_L : MIMG_Sampler <mimgopc<0x2c>, AMDGPUSample_c_l>; 966defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <mimgopc<0x2d>, AMDGPUSample_c_b>; 967defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <mimgopc<0x2e>, AMDGPUSample_c_b_cl>; 968defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <mimgopc<0x2f>, AMDGPUSample_c_lz>; 969defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <mimgopc<0x30>, AMDGPUSample_o>; 970defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <mimgopc<0x31>, AMDGPUSample_cl_o>; 971defm IMAGE_SAMPLE_D_O : MIMG_Sampler <mimgopc<0x32>, AMDGPUSample_d_o>; 972defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <mimgopc<0x33>, AMDGPUSample_d_cl_o>; 973defm IMAGE_SAMPLE_D_O_G16 : MIMG_Sampler <mimgopc<0xb2>, AMDGPUSample_d_o, 0, 1>; 974defm IMAGE_SAMPLE_D_CL_O_G16 : MIMG_Sampler <mimgopc<0xb3>, AMDGPUSample_d_cl_o, 0, 1>; 975defm IMAGE_SAMPLE_L_O : MIMG_Sampler <mimgopc<0x34>, AMDGPUSample_l_o>; 976defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <mimgopc<0x35>, AMDGPUSample_b_o>; 977defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <mimgopc<0x36>, AMDGPUSample_b_cl_o>; 978defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <mimgopc<0x37>, AMDGPUSample_lz_o>; 979defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <mimgopc<0x38>, AMDGPUSample_c_o>; 980defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <mimgopc<0x39>, AMDGPUSample_c_cl_o>; 981defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <mimgopc<0x3a>, AMDGPUSample_c_d_o>; 982defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <mimgopc<0x3b>, AMDGPUSample_c_d_cl_o>; 983defm IMAGE_SAMPLE_C_D_O_G16 : MIMG_Sampler <mimgopc<0xba>, AMDGPUSample_c_d_o, 0, 1>; 984defm IMAGE_SAMPLE_C_D_CL_O_G16 : MIMG_Sampler <mimgopc<0xbb>, AMDGPUSample_c_d_cl_o, 0, 1>; 985defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <mimgopc<0x3c>, AMDGPUSample_c_l_o>; 986defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <mimgopc<0x3e>, AMDGPUSample_c_b_cl_o>; 987defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <mimgopc<0x3d>, AMDGPUSample_c_b_o>; 988defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <mimgopc<0x3f>, AMDGPUSample_c_lz_o>; 989defm IMAGE_GATHER4 : MIMG_Gather_WQM <mimgopc<0x40>, AMDGPUSample>; 990defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <mimgopc<0x41>, AMDGPUSample_cl>; 991defm IMAGE_GATHER4_L : MIMG_Gather <mimgopc<0x44>, AMDGPUSample_l>; 992defm IMAGE_GATHER4_B : MIMG_Gather_WQM <mimgopc<0x45>, AMDGPUSample_b>; 993defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <mimgopc<0x46>, AMDGPUSample_b_cl>; 994defm IMAGE_GATHER4_LZ : MIMG_Gather <mimgopc<0x47>, AMDGPUSample_lz>; 995defm IMAGE_GATHER4_C : MIMG_Gather_WQM <mimgopc<0x48>, AMDGPUSample_c>; 996defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <mimgopc<0x49>, AMDGPUSample_c_cl>; 997defm IMAGE_GATHER4_C_L : MIMG_Gather <mimgopc<0x4c>, AMDGPUSample_c_l>; 998defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <mimgopc<0x4d>, AMDGPUSample_c_b>; 999defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <mimgopc<0x4e>, AMDGPUSample_c_b_cl>; 1000defm IMAGE_GATHER4_C_LZ : MIMG_Gather <mimgopc<0x4f>, AMDGPUSample_c_lz>; 1001defm IMAGE_GATHER4_O : MIMG_Gather_WQM <mimgopc<0x50>, AMDGPUSample_o>; 1002defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <mimgopc<0x51>, AMDGPUSample_cl_o>; 1003defm IMAGE_GATHER4_L_O : MIMG_Gather <mimgopc<0x54>, AMDGPUSample_l_o>; 1004defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <mimgopc<0x55>, AMDGPUSample_b_o>; 1005defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <mimgopc<0x56>, AMDGPUSample_b_cl_o>; 1006defm IMAGE_GATHER4_LZ_O : MIMG_Gather <mimgopc<0x57>, AMDGPUSample_lz_o>; 1007defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <mimgopc<0x58>, AMDGPUSample_c_o>; 1008defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <mimgopc<0x59>, AMDGPUSample_c_cl_o>; 1009defm IMAGE_GATHER4_C_L_O : MIMG_Gather <mimgopc<0x5c>, AMDGPUSample_c_l_o>; 1010defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <mimgopc<0x5d>, AMDGPUSample_c_b_o>; 1011defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <mimgopc<0x5e>, AMDGPUSample_c_b_cl_o>; 1012defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <mimgopc<0x5f>, AMDGPUSample_c_lz_o>; 1013//defm IMAGE_GATHER4H : MIMG_Gather_WQM <mimgopc<0x61>, ?>; 1014 1015defm IMAGE_GET_LOD : MIMG_Sampler <mimgopc<0x60>, AMDGPUSample, 1, 0, 1, "image_get_lod">; 1016 1017defm IMAGE_SAMPLE_CD : MIMG_Sampler <mimgopc<0x68>, AMDGPUSample_cd>; 1018defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <mimgopc<0x69>, AMDGPUSample_cd_cl>; 1019defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <mimgopc<0x6a>, AMDGPUSample_c_cd>; 1020defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <mimgopc<0x6b>, AMDGPUSample_c_cd_cl>; 1021defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <mimgopc<0x6c>, AMDGPUSample_cd_o>; 1022defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <mimgopc<0x6d>, AMDGPUSample_cd_cl_o>; 1023defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <mimgopc<0x6e>, AMDGPUSample_c_cd_o>; 1024defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <mimgopc<0x6f>, AMDGPUSample_c_cd_cl_o>; 1025defm IMAGE_SAMPLE_CD_G16 : MIMG_Sampler <mimgopc<0xe8>, AMDGPUSample_cd, 0, 1>; 1026defm IMAGE_SAMPLE_CD_CL_G16 : MIMG_Sampler <mimgopc<0xe9>, AMDGPUSample_cd_cl, 0, 1>; 1027defm IMAGE_SAMPLE_C_CD_G16 : MIMG_Sampler <mimgopc<0xea>, AMDGPUSample_c_cd, 0, 1>; 1028defm IMAGE_SAMPLE_C_CD_CL_G16 : MIMG_Sampler <mimgopc<0xeb>, AMDGPUSample_c_cd_cl, 0, 1>; 1029defm IMAGE_SAMPLE_CD_O_G16 : MIMG_Sampler <mimgopc<0xec>, AMDGPUSample_cd_o, 0, 1>; 1030defm IMAGE_SAMPLE_CD_CL_O_G16 : MIMG_Sampler <mimgopc<0xed>, AMDGPUSample_cd_cl_o, 0, 1>; 1031defm IMAGE_SAMPLE_C_CD_O_G16 : MIMG_Sampler <mimgopc<0xee>, AMDGPUSample_c_cd_o, 0, 1>; 1032defm IMAGE_SAMPLE_C_CD_CL_O_G16 : MIMG_Sampler <mimgopc<0xef>, AMDGPUSample_c_cd_cl_o, 0, 1>; 1033} // End OtherPredicates = [HasExtendedImageInsts] 1034//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>; 1035//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>; 1036 1037let SubtargetPredicate = HasGFX10_BEncoding in 1038defm IMAGE_MSAA_LOAD : MIMG_NoSampler <mimgopc<0x80>, "image_msaa_load", 1, 0, 0, 1>; 1039 1040defm IMAGE_BVH_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<0xe6>, "image_bvh_intersect_ray", 11, 0>; 1041defm IMAGE_BVH_INTERSECT_RAY_a16 : MIMG_IntersectRay<mimgopc<0xe6>, "image_bvh_intersect_ray", 8, 1>; 1042defm IMAGE_BVH64_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<0xe7>, "image_bvh64_intersect_ray", 12, 0>; 1043defm IMAGE_BVH64_INTERSECT_RAY_a16 : MIMG_IntersectRay<mimgopc<0xe7>, "image_bvh64_intersect_ray", 9, 1>; 1044 1045/********** ========================================= **********/ 1046/********** Table of dimension-aware image intrinsics **********/ 1047/********** ========================================= **********/ 1048 1049class ImageDimIntrinsicInfo<AMDGPUImageDimIntrinsic I> { 1050 Intrinsic Intr = I; 1051 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(!strconcat("IMAGE_", I.P.OpMod)); 1052 AMDGPUDimProps Dim = I.P.Dim; 1053 AMDGPUImageDimIntrinsicEval DimEval = AMDGPUImageDimIntrinsicEval<I.P>; 1054 1055 bits<8> NumGradients = DimEval.NumGradientArgs; 1056 bits<8> NumDmask = DimEval.NumDmaskArgs; 1057 bits<8> NumData = DimEval.NumDataArgs; 1058 bits<8> NumVAddrs = DimEval.NumVAddrArgs; 1059 bits<8> NumArgs = !add(DimEval.CachePolicyArgIndex, 1); 1060 1061 bits<8> DMaskIndex = DimEval.DmaskArgIndex; 1062 bits<8> VAddrStart = DimEval.VAddrArgIndex; 1063 bits<8> GradientStart = DimEval.GradientArgIndex; 1064 bits<8> CoordStart = DimEval.CoordArgIndex; 1065 bits<8> LodIndex = DimEval.LodArgIndex; 1066 bits<8> MipIndex = DimEval.MipArgIndex; 1067 bits<8> VAddrEnd = !add(DimEval.VAddrArgIndex, DimEval.NumVAddrArgs); 1068 bits<8> RsrcIndex = DimEval.RsrcArgIndex; 1069 bits<8> SampIndex = DimEval.SampArgIndex; 1070 bits<8> UnormIndex = DimEval.UnormArgIndex; 1071 bits<8> TexFailCtrlIndex = DimEval.TexFailCtrlArgIndex; 1072 bits<8> CachePolicyIndex = DimEval.CachePolicyArgIndex; 1073 1074 bits<8> GradientTyArg = !add(I.P.NumRetAndDataAnyTypes, 1075 !foldl(0, I.P.ExtraAddrArgs, cnt, arg, !add(cnt, arg.Type.isAny))); 1076 bits<8> CoordTyArg = !add(GradientTyArg, !if(I.P.Gradients, 1, 0)); 1077} 1078 1079def ImageDimIntrinsicTable : GenericTable { 1080 let FilterClass = "ImageDimIntrinsicInfo"; 1081 let Fields = ["Intr", "BaseOpcode", "Dim", "NumGradients", "NumDmask", "NumData", "NumVAddrs", "NumArgs", 1082 "DMaskIndex", "VAddrStart", "GradientStart", "CoordStart", "LodIndex", "MipIndex", "VAddrEnd", 1083 "RsrcIndex", "SampIndex", "UnormIndex", "TexFailCtrlIndex", "CachePolicyIndex", 1084 "GradientTyArg", "CoordTyArg"]; 1085 string TypeOf_BaseOpcode = "MIMGBaseOpcode"; 1086 string TypeOf_Dim = "MIMGDim"; 1087 1088 let PrimaryKey = ["Intr"]; 1089 let PrimaryKeyName = "getImageDimIntrinsicInfo"; 1090 let PrimaryKeyEarlyOut = 1; 1091} 1092 1093def getImageDimInstrinsicByBaseOpcode : SearchIndex { 1094 let Table = ImageDimIntrinsicTable; 1095 let Key = ["BaseOpcode", "Dim"]; 1096} 1097 1098foreach intr = !listconcat(AMDGPUImageDimIntrinsics, 1099 AMDGPUImageDimAtomicIntrinsics) in { 1100 def : ImageDimIntrinsicInfo<intr>; 1101} 1102 1103// L to LZ Optimization Mapping 1104def : MIMGLZMapping<IMAGE_SAMPLE_L, IMAGE_SAMPLE_LZ>; 1105def : MIMGLZMapping<IMAGE_SAMPLE_C_L, IMAGE_SAMPLE_C_LZ>; 1106def : MIMGLZMapping<IMAGE_SAMPLE_L_O, IMAGE_SAMPLE_LZ_O>; 1107def : MIMGLZMapping<IMAGE_SAMPLE_C_L_O, IMAGE_SAMPLE_C_LZ_O>; 1108def : MIMGLZMapping<IMAGE_GATHER4_L, IMAGE_GATHER4_LZ>; 1109def : MIMGLZMapping<IMAGE_GATHER4_C_L, IMAGE_GATHER4_C_LZ>; 1110def : MIMGLZMapping<IMAGE_GATHER4_L_O, IMAGE_GATHER4_LZ_O>; 1111def : MIMGLZMapping<IMAGE_GATHER4_C_L_O, IMAGE_GATHER4_C_LZ_O>; 1112 1113// MIP to NONMIP Optimization Mapping 1114def : MIMGMIPMapping<IMAGE_LOAD_MIP, IMAGE_LOAD>; 1115def : MIMGMIPMapping<IMAGE_STORE_MIP, IMAGE_STORE>; 1116 1117// G to G16 Optimization Mapping 1118def : MIMGG16Mapping<IMAGE_SAMPLE_D, IMAGE_SAMPLE_D_G16>; 1119def : MIMGG16Mapping<IMAGE_SAMPLE_D_CL, IMAGE_SAMPLE_D_CL_G16>; 1120def : MIMGG16Mapping<IMAGE_SAMPLE_C_D, IMAGE_SAMPLE_C_D_G16>; 1121def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_CL, IMAGE_SAMPLE_C_D_CL_G16>; 1122def : MIMGG16Mapping<IMAGE_SAMPLE_D_O, IMAGE_SAMPLE_D_O_G16>; 1123def : MIMGG16Mapping<IMAGE_SAMPLE_D_CL_O, IMAGE_SAMPLE_D_CL_O_G16>; 1124def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_O, IMAGE_SAMPLE_C_D_O_G16>; 1125def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_CL_O, IMAGE_SAMPLE_C_D_CL_O_G16>; 1126def : MIMGG16Mapping<IMAGE_SAMPLE_CD, IMAGE_SAMPLE_CD_G16>; 1127def : MIMGG16Mapping<IMAGE_SAMPLE_CD_CL, IMAGE_SAMPLE_CD_CL_G16>; 1128def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD, IMAGE_SAMPLE_C_CD_G16>; 1129def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_CL, IMAGE_SAMPLE_C_CD_CL_G16>; 1130def : MIMGG16Mapping<IMAGE_SAMPLE_CD_O, IMAGE_SAMPLE_CD_O_G16>; 1131def : MIMGG16Mapping<IMAGE_SAMPLE_CD_CL_O, IMAGE_SAMPLE_CD_CL_O_G16>; 1132def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_O, IMAGE_SAMPLE_C_CD_O_G16>; 1133def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_CL_O, IMAGE_SAMPLE_C_CD_CL_O_G16>; 1134