1//===-- MIMGInstructions.td - MIMG Instruction Defintions -----------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// MIMG-specific encoding families to distinguish between semantically 10// equivalent machine instructions with different encoding. 11// 12// - MIMGEncGfx6: encoding introduced with gfx6 (obsoleted for atomics in gfx8) 13// - MIMGEncGfx8: encoding introduced with gfx8 for atomics 14class MIMGEncoding; 15 16def MIMGEncGfx6 : MIMGEncoding; 17def MIMGEncGfx8 : MIMGEncoding; 18 19def MIMGEncoding : GenericEnum { 20 let FilterClass = "MIMGEncoding"; 21} 22 23// Represent an ISA-level opcode, independent of the encoding and the 24// vdata/vaddr size. 25class MIMGBaseOpcode { 26 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME); 27 bit Store = 0; 28 bit Atomic = 0; 29 bit AtomicX2 = 0; // (f)cmpswap 30 bit Sampler = 0; 31 bit Gather4 = 0; 32 bits<8> NumExtraArgs = 0; 33 bit Gradients = 0; 34 bit Coordinates = 1; 35 bit LodOrClampOrMip = 0; 36 bit HasD16 = 0; 37} 38 39def MIMGBaseOpcode : GenericEnum { 40 let FilterClass = "MIMGBaseOpcode"; 41} 42 43def MIMGBaseOpcodesTable : GenericTable { 44 let FilterClass = "MIMGBaseOpcode"; 45 let CppTypeName = "MIMGBaseOpcodeInfo"; 46 let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler", "Gather4", 47 "NumExtraArgs", "Gradients", "Coordinates", "LodOrClampOrMip", 48 "HasD16"]; 49 GenericEnum TypeOf_BaseOpcode = MIMGBaseOpcode; 50 51 let PrimaryKey = ["BaseOpcode"]; 52 let PrimaryKeyName = "getMIMGBaseOpcodeInfo"; 53} 54 55def MIMGDim : GenericEnum { 56 let FilterClass = "AMDGPUDimProps"; 57} 58 59def MIMGDimInfoTable : GenericTable { 60 let FilterClass = "AMDGPUDimProps"; 61 let CppTypeName = "MIMGDimInfo"; 62 let Fields = ["Dim", "NumCoords", "NumGradients", "DA"]; 63 GenericEnum TypeOf_Dim = MIMGDim; 64 65 let PrimaryKey = ["Dim"]; 66 let PrimaryKeyName = "getMIMGDimInfo"; 67} 68 69class MIMGLZMapping<MIMGBaseOpcode l, MIMGBaseOpcode lz> { 70 MIMGBaseOpcode L = l; 71 MIMGBaseOpcode LZ = lz; 72} 73 74def MIMGLZMappingTable : GenericTable { 75 let FilterClass = "MIMGLZMapping"; 76 let CppTypeName = "MIMGLZMappingInfo"; 77 let Fields = ["L", "LZ"]; 78 GenericEnum TypeOf_L = MIMGBaseOpcode; 79 GenericEnum TypeOf_LZ = MIMGBaseOpcode; 80 81 let PrimaryKey = ["L"]; 82 let PrimaryKeyName = "getMIMGLZMappingInfo"; 83} 84 85class mimg <bits<7> si, bits<7> vi = si> { 86 field bits<7> SI = si; 87 field bits<7> VI = vi; 88} 89 90class MIMG <dag outs, string dns = ""> 91 : InstSI <outs, (ins), "", []> { 92 93 let VM_CNT = 1; 94 let EXP_CNT = 1; 95 let MIMG = 1; 96 let Uses = [EXEC]; 97 let mayLoad = 1; 98 let mayStore = 0; 99 let hasPostISelHook = 1; 100 let SchedRW = [WriteVMEM]; 101 let UseNamedOperandTable = 1; 102 let hasSideEffects = 0; // XXX ???? 103 104 let DecoderNamespace = dns; 105 let isAsmParserOnly = !if(!eq(dns,""), 1, 0); 106 let AsmMatchConverter = "cvtMIMG"; 107 let usesCustomInserter = 1; 108 109 Instruction Opcode = !cast<Instruction>(NAME); 110 MIMGBaseOpcode BaseOpcode; 111 MIMGEncoding MIMGEncoding = MIMGEncGfx6; 112 bits<8> VDataDwords; 113 bits<8> VAddrDwords; 114} 115 116def MIMGInfoTable : GenericTable { 117 let FilterClass = "MIMG"; 118 let CppTypeName = "MIMGInfo"; 119 let Fields = ["Opcode", "BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"]; 120 GenericEnum TypeOf_BaseOpcode = MIMGBaseOpcode; 121 GenericEnum TypeOf_MIMGEncoding = MIMGEncoding; 122 123 let PrimaryKey = ["BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"]; 124 let PrimaryKeyName = "getMIMGOpcodeHelper"; 125} 126 127def getMIMGInfo : SearchIndex { 128 let Table = MIMGInfoTable; 129 let Key = ["Opcode"]; 130} 131 132class MIMG_NoSampler_Helper <bits<7> op, string asm, 133 RegisterClass dst_rc, 134 RegisterClass addr_rc, 135 string dns=""> 136 : MIMG <(outs dst_rc:$vdata), dns>, 137 MIMGe<op> { 138 let ssamp = 0; 139 let d16 = !if(BaseOpcode.HasD16, ?, 0); 140 141 let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc, 142 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, 143 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 144 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 145 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" 146 #!if(BaseOpcode.HasD16, "$d16", ""); 147} 148 149multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm, 150 RegisterClass dst_rc, 151 bit enableDisasm> { 152 let VAddrDwords = 1 in 153 def NAME # _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32, 154 !if(enableDisasm, "AMDGPU", "")>; 155 let VAddrDwords = 2 in 156 def NAME # _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>; 157 let VAddrDwords = 3 in 158 def NAME # _V3 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_96>; 159 let VAddrDwords = 4 in 160 def NAME # _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>; 161} 162 163multiclass MIMG_NoSampler <bits<7> op, string asm, bit has_d16, bit mip = 0, 164 bit isResInfo = 0> { 165 def "" : MIMGBaseOpcode { 166 let Coordinates = !if(isResInfo, 0, 1); 167 let LodOrClampOrMip = mip; 168 let HasD16 = has_d16; 169 } 170 171 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), 172 mayLoad = !if(isResInfo, 0, 1) in { 173 let VDataDwords = 1 in 174 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>; 175 let VDataDwords = 2 in 176 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 0>; 177 let VDataDwords = 3 in 178 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 0>; 179 let VDataDwords = 4 in 180 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 0>; 181 let VDataDwords = 5 in 182 defm _V5 : MIMG_NoSampler_Src_Helper <op, asm, VReg_160, 0>; 183 } 184} 185 186class MIMG_Store_Helper <bits<7> op, string asm, 187 RegisterClass data_rc, 188 RegisterClass addr_rc, 189 string dns = ""> 190 : MIMG <(outs), dns>, 191 MIMGe<op> { 192 let ssamp = 0; 193 let d16 = !if(BaseOpcode.HasD16, ?, 0); 194 195 let mayLoad = 0; 196 let mayStore = 1; 197 let hasSideEffects = 0; 198 let hasPostISelHook = 0; 199 let DisableWQM = 1; 200 201 let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, 202 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, 203 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 204 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 205 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" 206 #!if(BaseOpcode.HasD16, "$d16", ""); 207} 208 209multiclass MIMG_Store_Addr_Helper <bits<7> op, string asm, 210 RegisterClass data_rc, 211 bit enableDisasm> { 212 let VAddrDwords = 1 in 213 def NAME # _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32, 214 !if(enableDisasm, "AMDGPU", "")>; 215 let VAddrDwords = 2 in 216 def NAME # _V2 : MIMG_Store_Helper <op, asm, data_rc, VReg_64>; 217 let VAddrDwords = 3 in 218 def NAME # _V3 : MIMG_Store_Helper <op, asm, data_rc, VReg_96>; 219 let VAddrDwords = 4 in 220 def NAME # _V4 : MIMG_Store_Helper <op, asm, data_rc, VReg_128>; 221} 222 223multiclass MIMG_Store <bits<7> op, string asm, bit has_d16, bit mip = 0> { 224 def "" : MIMGBaseOpcode { 225 let Store = 1; 226 let LodOrClampOrMip = mip; 227 let HasD16 = has_d16; 228 } 229 230 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in { 231 let VDataDwords = 1 in 232 defm _V1 : MIMG_Store_Addr_Helper <op, asm, VGPR_32, 1>; 233 let VDataDwords = 2 in 234 defm _V2 : MIMG_Store_Addr_Helper <op, asm, VReg_64, 0>; 235 let VDataDwords = 3 in 236 defm _V3 : MIMG_Store_Addr_Helper <op, asm, VReg_96, 0>; 237 let VDataDwords = 4 in 238 defm _V4 : MIMG_Store_Addr_Helper <op, asm, VReg_128, 0>; 239 } 240} 241 242class MIMG_Atomic_Helper <string asm, RegisterClass data_rc, 243 RegisterClass addr_rc, string dns="", 244 bit enableDasm = 0> 245 : MIMG <(outs data_rc:$vdst), !if(enableDasm, dns, "")> { 246 let mayLoad = 1; 247 let mayStore = 1; 248 let hasSideEffects = 1; // FIXME: Remove this 249 let hasPostISelHook = 0; 250 let DisableWQM = 1; 251 let Constraints = "$vdst = $vdata"; 252 let AsmMatchConverter = "cvtMIMGAtomic"; 253 254 let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, 255 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, 256 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da); 257 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"; 258} 259 260multiclass MIMG_Atomic_Helper_m <mimg op, string asm, RegisterClass data_rc, 261 RegisterClass addr_rc, bit enableDasm = 0> { 262 let ssamp = 0, d16 = 0 in { 263 def _si : MIMG_Atomic_Helper<asm, data_rc, addr_rc, "SICI", enableDasm>, 264 SIMCInstr<NAME, SIEncodingFamily.SI>, 265 MIMGe<op.SI> { 266 let AssemblerPredicates = [isSICI]; 267 let DisableDecoder = DisableSIDecoder; 268 } 269 270 def _vi : MIMG_Atomic_Helper<asm, data_rc, addr_rc, "VI", enableDasm>, 271 SIMCInstr<NAME, SIEncodingFamily.VI>, 272 MIMGe<op.VI> { 273 let AssemblerPredicates = [isVI]; 274 let DisableDecoder = DisableVIDecoder; 275 let MIMGEncoding = MIMGEncGfx8; 276 } 277 } 278} 279 280multiclass MIMG_Atomic_Addr_Helper_m <mimg op, string asm, 281 RegisterClass data_rc, 282 bit enableDasm = 0> { 283 // _V* variants have different address size, but the size is not encoded. 284 // So only one variant can be disassembled. V1 looks the safest to decode. 285 let VAddrDwords = 1 in 286 defm _V1 : MIMG_Atomic_Helper_m <op, asm, data_rc, VGPR_32, enableDasm>; 287 let VAddrDwords = 2 in 288 defm _V2 : MIMG_Atomic_Helper_m <op, asm, data_rc, VReg_64>; 289 let VAddrDwords = 3 in 290 defm _V3 : MIMG_Atomic_Helper_m <op, asm, data_rc, VReg_96>; 291 let VAddrDwords = 4 in 292 defm _V4 : MIMG_Atomic_Helper_m <op, asm, data_rc, VReg_128>; 293} 294 295multiclass MIMG_Atomic <mimg op, string asm, bit isCmpSwap = 0> { // 64-bit atomics 296 def "" : MIMGBaseOpcode { 297 let Atomic = 1; 298 let AtomicX2 = isCmpSwap; 299 } 300 301 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in { 302 // _V* variants have different dst size, but the size is encoded implicitly, 303 // using dmask and tfe. Only 32-bit variant is registered with disassembler. 304 // Other variants are reconstructed by disassembler using dmask and tfe. 305 let VDataDwords = !if(isCmpSwap, 2, 1) in 306 defm _V1 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_64, VGPR_32), 1>; 307 let VDataDwords = !if(isCmpSwap, 4, 2) in 308 defm _V2 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_128, VReg_64)>; 309 } 310} 311 312class MIMG_Sampler_Helper <bits<7> op, string asm, RegisterClass dst_rc, 313 RegisterClass src_rc, string dns=""> 314 : MIMG <(outs dst_rc:$vdata), dns>, 315 MIMGe<op> { 316 let d16 = !if(BaseOpcode.HasD16, ?, 0); 317 318 let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp, 319 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, 320 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 321 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 322 let AsmString = asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da" 323 #!if(BaseOpcode.HasD16, "$d16", ""); 324} 325 326class MIMGAddrSize<int dw, bit enable_disasm> { 327 int NumWords = dw; 328 329 RegisterClass RegClass = !if(!le(NumWords, 0), ?, 330 !if(!eq(NumWords, 1), VGPR_32, 331 !if(!eq(NumWords, 2), VReg_64, 332 !if(!eq(NumWords, 3), VReg_96, 333 !if(!eq(NumWords, 4), VReg_128, 334 !if(!le(NumWords, 8), VReg_256, 335 !if(!le(NumWords, 16), VReg_512, ?))))))); 336 337 // Whether the instruction variant with this vaddr size should be enabled for 338 // the auto-generated disassembler. 339 bit Disassemble = enable_disasm; 340} 341 342// Return whether a value inside the range [min, max] (endpoints inclusive) 343// is in the given list. 344class isRangeInList<int min, int max, list<int> lst> { 345 bit ret = !foldl(0, lst, lhs, y, !or(lhs, !and(!le(min, y), !le(y, max)))); 346} 347 348class MIMGAddrSizes_tmp<list<MIMGAddrSize> lst, int min> { 349 list<MIMGAddrSize> List = lst; 350 int Min = min; 351} 352 353class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample> { 354 // List of all possible numbers of address words, taking all combinations of 355 // A16 and image dimension into account (note: no MSAA, since this is for 356 // sample/gather ops). 357 list<int> AllNumAddrWords = 358 !foreach(dw, !if(sample.Gradients, 359 !if(!eq(sample.LodOrClamp, ""), 360 [2, 3, 4, 5, 6, 7, 9], 361 [2, 3, 4, 5, 7, 8, 10]), 362 !if(!eq(sample.LodOrClamp, ""), 363 [1, 2, 3], 364 [1, 2, 3, 4])), 365 !add(dw, !size(sample.ExtraAddrArgs))); 366 367 // Generate machine instructions based on possible register classes for the 368 // required numbers of address words. The disassembler defaults to the 369 // smallest register class. 370 list<MIMGAddrSize> MachineInstrs = 371 !foldl(MIMGAddrSizes_tmp<[], 0>, [1, 2, 3, 4, 8, 16], lhs, dw, 372 !if(isRangeInList<lhs.Min, dw, AllNumAddrWords>.ret, 373 MIMGAddrSizes_tmp< 374 !listconcat(lhs.List, [MIMGAddrSize<dw, !empty(lhs.List)>]), 375 !if(!eq(dw, 3), 3, !add(dw, 1))>, // we still need _V4 for codegen w/ 3 dwords 376 lhs)).List; 377} 378 379multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm, 380 AMDGPUSampleVariant sample, RegisterClass dst_rc, 381 bit enableDisasm = 0> { 382 foreach addr = MIMG_Sampler_AddrSizes<sample>.MachineInstrs in { 383 let VAddrDwords = addr.NumWords in 384 def _V # addr.NumWords 385 : MIMG_Sampler_Helper <op, asm, dst_rc, addr.RegClass, 386 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 387 } 388} 389 390class MIMG_Sampler_BaseOpcode<AMDGPUSampleVariant sample> 391 : MIMGBaseOpcode { 392 let Sampler = 1; 393 let NumExtraArgs = !size(sample.ExtraAddrArgs); 394 let Gradients = sample.Gradients; 395 let LodOrClampOrMip = !ne(sample.LodOrClamp, ""); 396} 397 398multiclass MIMG_Sampler <bits<7> op, AMDGPUSampleVariant sample, bit wqm = 0, 399 bit isGetLod = 0, 400 string asm = "image_sample"#sample.LowerCaseMod> { 401 def "" : MIMG_Sampler_BaseOpcode<sample> { 402 let HasD16 = !if(isGetLod, 0, 1); 403 } 404 405 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm, 406 mayLoad = !if(isGetLod, 0, 1) in { 407 let VDataDwords = 1 in 408 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, sample, VGPR_32, 1>; 409 let VDataDwords = 2 in 410 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64>; 411 let VDataDwords = 3 in 412 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_96>; 413 let VDataDwords = 4 in 414 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128>; 415 let VDataDwords = 5 in 416 defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160>; 417 } 418} 419 420multiclass MIMG_Sampler_WQM <bits<7> op, AMDGPUSampleVariant sample> 421 : MIMG_Sampler<op, sample, 1>; 422 423multiclass MIMG_Gather <bits<7> op, AMDGPUSampleVariant sample, bit wqm = 0, 424 string asm = "image_gather4"#sample.LowerCaseMod> { 425 def "" : MIMG_Sampler_BaseOpcode<sample> { 426 let HasD16 = 1; 427 let Gather4 = 1; 428 } 429 430 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm, 431 Gather4 = 1, hasPostISelHook = 0 in { 432 let VDataDwords = 2 in 433 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64>; /* for packed D16 only */ 434 let VDataDwords = 4 in 435 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 1>; 436 let VDataDwords = 5 in 437 defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160>; 438 } 439} 440 441multiclass MIMG_Gather_WQM <bits<7> op, AMDGPUSampleVariant sample> 442 : MIMG_Gather<op, sample, 1>; 443 444//===----------------------------------------------------------------------===// 445// MIMG Instructions 446//===----------------------------------------------------------------------===// 447defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load", 1>; 448defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip", 1, 1>; 449defm IMAGE_LOAD_PCK : MIMG_NoSampler <0x00000002, "image_load_pck", 0>; 450defm IMAGE_LOAD_PCK_SGN : MIMG_NoSampler <0x00000003, "image_load_pck_sgn", 0>; 451defm IMAGE_LOAD_MIP_PCK : MIMG_NoSampler <0x00000004, "image_load_mip_pck", 0, 1>; 452defm IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoSampler <0x00000005, "image_load_mip_pck_sgn", 0, 1>; 453defm IMAGE_STORE : MIMG_Store <0x00000008, "image_store", 1>; 454defm IMAGE_STORE_MIP : MIMG_Store <0x00000009, "image_store_mip", 1, 1>; 455defm IMAGE_STORE_PCK : MIMG_Store <0x0000000a, "image_store_pck", 0>; 456defm IMAGE_STORE_MIP_PCK : MIMG_Store <0x0000000b, "image_store_mip_pck", 0, 1>; 457 458defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo", 0, 1, 1>; 459 460defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimg<0x0f, 0x10>, "image_atomic_swap">; 461defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimg<0x10, 0x11>, "image_atomic_cmpswap", 1>; 462defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimg<0x11, 0x12>, "image_atomic_add">; 463defm IMAGE_ATOMIC_SUB : MIMG_Atomic <mimg<0x12, 0x13>, "image_atomic_sub">; 464//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>; -- not on VI 465defm IMAGE_ATOMIC_SMIN : MIMG_Atomic <mimg<0x14>, "image_atomic_smin">; 466defm IMAGE_ATOMIC_UMIN : MIMG_Atomic <mimg<0x15>, "image_atomic_umin">; 467defm IMAGE_ATOMIC_SMAX : MIMG_Atomic <mimg<0x16>, "image_atomic_smax">; 468defm IMAGE_ATOMIC_UMAX : MIMG_Atomic <mimg<0x17>, "image_atomic_umax">; 469defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimg<0x18>, "image_atomic_and">; 470defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimg<0x19>, "image_atomic_or">; 471defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimg<0x1a>, "image_atomic_xor">; 472defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimg<0x1b>, "image_atomic_inc">; 473defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimg<0x1c>, "image_atomic_dec">; 474//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d, 1>; -- not on VI 475//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>; -- not on VI 476//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>; -- not on VI 477defm IMAGE_SAMPLE : MIMG_Sampler_WQM <0x00000020, AMDGPUSample>; 478defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <0x00000021, AMDGPUSample_cl>; 479defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, AMDGPUSample_d>; 480defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, AMDGPUSample_d_cl>; 481defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, AMDGPUSample_l>; 482defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <0x00000025, AMDGPUSample_b>; 483defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <0x00000026, AMDGPUSample_b_cl>; 484defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, AMDGPUSample_lz>; 485defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <0x00000028, AMDGPUSample_c>; 486defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <0x00000029, AMDGPUSample_c_cl>; 487defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, AMDGPUSample_c_d>; 488defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, AMDGPUSample_c_d_cl>; 489defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, AMDGPUSample_c_l>; 490defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <0x0000002d, AMDGPUSample_c_b>; 491defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <0x0000002e, AMDGPUSample_c_b_cl>; 492defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, AMDGPUSample_c_lz>; 493defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <0x00000030, AMDGPUSample_o>; 494defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <0x00000031, AMDGPUSample_cl_o>; 495defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, AMDGPUSample_d_o>; 496defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, AMDGPUSample_d_cl_o>; 497defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, AMDGPUSample_l_o>; 498defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <0x00000035, AMDGPUSample_b_o>; 499defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <0x00000036, AMDGPUSample_b_cl_o>; 500defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, AMDGPUSample_lz_o>; 501defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <0x00000038, AMDGPUSample_c_o>; 502defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <0x00000039, AMDGPUSample_c_cl_o>; 503defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, AMDGPUSample_c_d_o>; 504defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, AMDGPUSample_c_d_cl_o>; 505defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, AMDGPUSample_c_l_o>; 506defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <0x0000003e, AMDGPUSample_c_b_cl_o>; 507defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <0x0000003d, AMDGPUSample_c_b_o>; 508defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, AMDGPUSample_c_lz_o>; 509defm IMAGE_GATHER4 : MIMG_Gather_WQM <0x00000040, AMDGPUSample>; 510defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <0x00000041, AMDGPUSample_cl>; 511defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, AMDGPUSample_l>; 512defm IMAGE_GATHER4_B : MIMG_Gather_WQM <0x00000045, AMDGPUSample_b>; 513defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <0x00000046, AMDGPUSample_b_cl>; 514defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, AMDGPUSample_lz>; 515defm IMAGE_GATHER4_C : MIMG_Gather_WQM <0x00000048, AMDGPUSample_c>; 516defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <0x00000049, AMDGPUSample_c_cl>; 517defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, AMDGPUSample_c_l>; 518defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <0x0000004d, AMDGPUSample_c_b>; 519defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <0x0000004e, AMDGPUSample_c_b_cl>; 520defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, AMDGPUSample_c_lz>; 521defm IMAGE_GATHER4_O : MIMG_Gather_WQM <0x00000050, AMDGPUSample_o>; 522defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <0x00000051, AMDGPUSample_cl_o>; 523defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, AMDGPUSample_l_o>; 524defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <0x00000055, AMDGPUSample_b_o>; 525defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, AMDGPUSample_b_cl_o>; 526defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, AMDGPUSample_lz_o>; 527defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <0x00000058, AMDGPUSample_c_o>; 528defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <0x00000059, AMDGPUSample_c_cl_o>; 529defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, AMDGPUSample_c_l_o>; 530defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <0x0000005d, AMDGPUSample_c_b_o>; 531defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <0x0000005e, AMDGPUSample_c_b_cl_o>; 532defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, AMDGPUSample_c_lz_o>; 533 534defm IMAGE_GET_LOD : MIMG_Sampler <0x00000060, AMDGPUSample, 1, 1, "image_get_lod">; 535 536defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, AMDGPUSample_cd>; 537defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, AMDGPUSample_cd_cl>; 538defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, AMDGPUSample_c_cd>; 539defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, AMDGPUSample_c_cd_cl>; 540defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, AMDGPUSample_cd_o>; 541defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, AMDGPUSample_cd_cl_o>; 542defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, AMDGPUSample_c_cd_o>; 543defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, AMDGPUSample_c_cd_cl_o>; 544//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>; 545//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>; 546 547/********** ========================================= **********/ 548/********** Table of dimension-aware image intrinsics **********/ 549/********** ========================================= **********/ 550 551class ImageDimIntrinsicInfo<AMDGPUImageDimIntrinsic I> { 552 Intrinsic Intr = I; 553 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(!strconcat("IMAGE_", I.P.OpMod)); 554 AMDGPUDimProps Dim = I.P.Dim; 555} 556 557def ImageDimIntrinsicTable : GenericTable { 558 let FilterClass = "ImageDimIntrinsicInfo"; 559 let Fields = ["Intr", "BaseOpcode", "Dim"]; 560 GenericEnum TypeOf_BaseOpcode = MIMGBaseOpcode; 561 GenericEnum TypeOf_Dim = MIMGDim; 562 563 let PrimaryKey = ["Intr"]; 564 let PrimaryKeyName = "getImageDimIntrinsicInfo"; 565 let PrimaryKeyEarlyOut = 1; 566} 567 568foreach intr = !listconcat(AMDGPUImageDimIntrinsics, 569 AMDGPUImageDimAtomicIntrinsics) in { 570 def : ImageDimIntrinsicInfo<intr>; 571} 572 573// L to LZ Optimization Mapping 574def : MIMGLZMapping<IMAGE_SAMPLE_L, IMAGE_SAMPLE_LZ>; 575def : MIMGLZMapping<IMAGE_SAMPLE_C_L, IMAGE_SAMPLE_C_LZ>; 576def : MIMGLZMapping<IMAGE_SAMPLE_L_O, IMAGE_SAMPLE_LZ_O>; 577def : MIMGLZMapping<IMAGE_SAMPLE_C_L_O, IMAGE_SAMPLE_C_LZ_O>; 578def : MIMGLZMapping<IMAGE_GATHER4_L, IMAGE_GATHER4_LZ>; 579def : MIMGLZMapping<IMAGE_GATHER4_C_L, IMAGE_GATHER4_C_LZ>; 580def : MIMGLZMapping<IMAGE_GATHER4_L_O, IMAGE_GATHER4_LZ_O>; 581def : MIMGLZMapping<IMAGE_GATHER4_C_L_O, IMAGE_GATHER4_C_LZ_O>; 582