1//===-- MIMGInstructions.td - MIMG Instruction Definitions ----------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// MIMG-specific encoding families to distinguish between semantically 10// equivalent machine instructions with different encoding. 11// 12// - MIMGEncGfx6: encoding introduced with gfx6 (obsoleted for atomics in gfx8) 13// - MIMGEncGfx8: encoding introduced with gfx8 for atomics 14// - MIMGEncGfx90a: encoding for gfx90a for atomics 15// - MIMGEncGfx10Default: gfx10 default (non-NSA) encoding 16// - MIMGEncGfx10NSA: gfx10 NSA encoding 17class MIMGEncoding; 18 19def MIMGEncGfx6 : MIMGEncoding; 20def MIMGEncGfx8 : MIMGEncoding; 21def MIMGEncGfx90a : MIMGEncoding; 22def MIMGEncGfx10Default : MIMGEncoding; 23def MIMGEncGfx10NSA : MIMGEncoding; 24 25def MIMGEncoding : GenericEnum { 26 let FilterClass = "MIMGEncoding"; 27} 28 29// Represent an ISA-level opcode, independent of the encoding and the 30// vdata/vaddr size. 31class MIMGBaseOpcode : PredicateControl { 32 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME); 33 bit Store = 0; 34 bit Atomic = 0; 35 bit AtomicX2 = 0; // (f)cmpswap 36 bit Sampler = 0; 37 bit Gather4 = 0; 38 bits<8> NumExtraArgs = 0; 39 bit Gradients = 0; 40 bit G16 = 0; 41 bit Coordinates = 1; 42 bit LodOrClampOrMip = 0; 43 bit HasD16 = 0; 44 bit IsAtomicRet = 0; 45 bit MSAA = 0; 46} 47 48def MIMGBaseOpcode : GenericEnum { 49 let FilterClass = "MIMGBaseOpcode"; 50} 51 52def MIMGBaseOpcodesTable : GenericTable { 53 let FilterClass = "MIMGBaseOpcode"; 54 let CppTypeName = "MIMGBaseOpcodeInfo"; 55 let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler", 56 "Gather4", "NumExtraArgs", "Gradients", "G16", "Coordinates", 57 "LodOrClampOrMip", "HasD16", "MSAA"]; 58 string TypeOf_BaseOpcode = "MIMGBaseOpcode"; 59 60 let PrimaryKey = ["BaseOpcode"]; 61 let PrimaryKeyName = "getMIMGBaseOpcodeInfo"; 62} 63 64def MIMGDim : GenericEnum { 65 let FilterClass = "AMDGPUDimProps"; 66} 67 68def MIMGDimInfoTable : GenericTable { 69 let FilterClass = "AMDGPUDimProps"; 70 let CppTypeName = "MIMGDimInfo"; 71 let Fields = ["Dim", "NumCoords", "NumGradients", "MSAA", "DA", "Encoding", "AsmSuffix"]; 72 string TypeOf_Dim = "MIMGDim"; 73 74 let PrimaryKey = ["Dim"]; 75 let PrimaryKeyName = "getMIMGDimInfo"; 76} 77 78def getMIMGDimInfoByEncoding : SearchIndex { 79 let Table = MIMGDimInfoTable; 80 let Key = ["Encoding"]; 81} 82 83def getMIMGDimInfoByAsmSuffix : SearchIndex { 84 let Table = MIMGDimInfoTable; 85 let Key = ["AsmSuffix"]; 86} 87 88def MIMG { 89 int NOP = -1; 90} 91 92class mimgopc <int base, int vi = base, int si = base> { 93 field bits<8> BASE = base; // Opcode for all but atomics 94 field bits<8> VI = vi; // VI is only used for atomic instructions 95 field bits<8> SI = si; // SI is only used for atomic instructions 96 bit HAS_BASE = !ne(base, MIMG.NOP); 97 bit HAS_VI = !ne(vi, MIMG.NOP); 98 bit HAS_SI = !ne(si, MIMG.NOP); 99} 100 101class MIMGLZMapping<MIMGBaseOpcode l, MIMGBaseOpcode lz> { 102 MIMGBaseOpcode L = l; 103 MIMGBaseOpcode LZ = lz; 104} 105 106def MIMGLZMappingTable : GenericTable { 107 let FilterClass = "MIMGLZMapping"; 108 let CppTypeName = "MIMGLZMappingInfo"; 109 let Fields = ["L", "LZ"]; 110 string TypeOf_L = "MIMGBaseOpcode"; 111 string TypeOf_LZ = "MIMGBaseOpcode"; 112 113 let PrimaryKey = ["L"]; 114 let PrimaryKeyName = "getMIMGLZMappingInfo"; 115} 116 117class MIMGMIPMapping<MIMGBaseOpcode mip, MIMGBaseOpcode nonmip> { 118 MIMGBaseOpcode MIP = mip; 119 MIMGBaseOpcode NONMIP = nonmip; 120} 121 122def MIMGMIPMappingTable : GenericTable { 123 let FilterClass = "MIMGMIPMapping"; 124 let CppTypeName = "MIMGMIPMappingInfo"; 125 let Fields = ["MIP", "NONMIP"]; 126 string TypeOf_MIP = "MIMGBaseOpcode"; 127 string TypeOf_NONMIP = "MIMGBaseOpcode"; 128 129 let PrimaryKey = ["MIP"]; 130 let PrimaryKeyName = "getMIMGMIPMappingInfo"; 131} 132 133class MIMGG16Mapping<MIMGBaseOpcode g, MIMGBaseOpcode g16> { 134 MIMGBaseOpcode G = g; 135 MIMGBaseOpcode G16 = g16; 136} 137 138def MIMGG16MappingTable : GenericTable { 139 let FilterClass = "MIMGG16Mapping"; 140 let CppTypeName = "MIMGG16MappingInfo"; 141 let Fields = ["G", "G16"]; 142 string TypeOf_G = "MIMGBaseOpcode"; 143 string TypeOf_G16 = "MIMGBaseOpcode"; 144 145 let PrimaryKey = ["G"]; 146 let PrimaryKeyName = "getMIMGG16MappingInfo"; 147} 148 149class MIMG_Base <dag outs, string dns = ""> 150 : InstSI <outs, (ins), "", []> { 151 152 let VM_CNT = 1; 153 let EXP_CNT = 1; 154 let MIMG = 1; 155 let Uses = [EXEC]; 156 let mayLoad = 1; 157 let mayStore = 0; 158 let SchedRW = [WriteVMEM]; 159 let UseNamedOperandTable = 1; 160 let hasSideEffects = 0; // XXX ???? 161 162 let DecoderNamespace = dns; 163 let isAsmParserOnly = !eq(dns, ""); 164} 165 166class MIMG <dag outs, string dns = ""> 167 : MIMG_Base <outs, dns> { 168 169 let hasPostISelHook = 1; 170 let AsmMatchConverter = "cvtMIMG"; 171 172 Instruction Opcode = !cast<Instruction>(NAME); 173 MIMGBaseOpcode BaseOpcode; 174 MIMGEncoding MIMGEncoding; 175 bits<8> VDataDwords; 176 bits<8> VAddrDwords; 177} 178 179def MIMGInfoTable : GenericTable { 180 let FilterClass = "MIMG"; 181 let CppTypeName = "MIMGInfo"; 182 let Fields = ["Opcode", "BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"]; 183 string TypeOf_BaseOpcode = "MIMGBaseOpcode"; 184 string TypeOf_MIMGEncoding = "MIMGEncoding"; 185 186 let PrimaryKey = ["BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"]; 187 let PrimaryKeyName = "getMIMGOpcodeHelper"; 188} 189 190def getMIMGInfo : SearchIndex { 191 let Table = MIMGInfoTable; 192 let Key = ["Opcode"]; 193} 194 195// This class used to use !foldl to memoize the AddrAsmNames list. 196// It turned out that that was much slower than using !filter. 197class MIMGNSAHelper<int num_addrs> { 198 list<string> AddrAsmNames = 199 !foreach(i, !filter(i, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11], 200 !lt(i, num_addrs)), "vaddr" # i); 201 dag AddrIns = !dag(ins, !foreach(arg, AddrAsmNames, VGPR_32), AddrAsmNames); 202 string AddrAsm = "[$" # !interleave(AddrAsmNames, ", $") # "]"; 203 204 int NSA = !if(!le(num_addrs, 1), ?, 205 !if(!le(num_addrs, 5), 1, 206 !if(!le(num_addrs, 9), 2, 207 !if(!le(num_addrs, 13), 3, ?)))); 208} 209 210// Base class of all pre-gfx10 MIMG instructions. 211class MIMG_gfx6789<bits<8> op, dag outs, string dns = ""> 212 : MIMG<outs, dns>, MIMGe_gfx6789<op> { 213 let SubtargetPredicate = isGFX6GFX7GFX8GFX9NotGFX90A; 214 let AssemblerPredicate = isGFX6GFX7GFX8GFX9NotGFX90A; 215 216 let MIMGEncoding = MIMGEncGfx6; 217 218 let d16 = !if(BaseOpcode.HasD16, ?, 0); 219} 220 221class MIMG_gfx90a<bits<8> op, dag outs, string dns = ""> 222 : MIMG<outs, dns>, MIMGe_gfx90a<op> { 223 let SubtargetPredicate = isGFX90APlus; 224 let AssemblerPredicate = isGFX90APlus; 225 226 let MIMGEncoding = MIMGEncGfx90a; 227 228 let d16 = !if(BaseOpcode.HasD16, ?, 0); 229} 230 231// Base class of all non-NSA gfx10 MIMG instructions. 232class MIMG_gfx10<int op, dag outs, string dns = ""> 233 : MIMG<outs, dns>, MIMGe_gfx10<op> { 234 let SubtargetPredicate = isGFX10Plus; 235 let AssemblerPredicate = isGFX10Plus; 236 237 let MIMGEncoding = MIMGEncGfx10Default; 238 239 let d16 = !if(BaseOpcode.HasD16, ?, 0); 240 let nsa = 0; 241} 242 243// Base class for all NSA MIMG instructions. 244// Note that 1-dword addresses always use non-NSA variants. 245class MIMG_nsa_gfx10<int op, dag outs, int num_addrs, string dns=""> 246 : MIMG<outs, dns>, MIMGe_gfx10<op> { 247 let SubtargetPredicate = isGFX10Plus; 248 let AssemblerPredicate = isGFX10Plus; 249 250 let MIMGEncoding = MIMGEncGfx10NSA; 251 252 MIMGNSAHelper nsah = MIMGNSAHelper<num_addrs>; 253 dag AddrIns = nsah.AddrIns; 254 string AddrAsm = nsah.AddrAsm; 255 256 let d16 = !if(BaseOpcode.HasD16, ?, 0); 257 let nsa = nsah.NSA; 258} 259 260class MIMG_NoSampler_Helper <mimgopc op, string asm, 261 RegisterClass dst_rc, 262 RegisterClass addr_rc, 263 string dns=""> 264 : MIMG_gfx6789 <op.BASE, (outs dst_rc:$vdata), dns> { 265 let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc, 266 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 267 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 268 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 269 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da" 270 #!if(BaseOpcode.HasD16, "$d16", ""); 271} 272 273class MIMG_NoSampler_Helper_gfx90a <mimgopc op, string asm, 274 RegisterClass dst_rc, 275 RegisterClass addr_rc, 276 string dns=""> 277 : MIMG_gfx90a <op.BASE, (outs getLdStRegisterOperand<dst_rc>.ret:$vdata), dns> { 278 let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc, 279 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 280 R128A16:$r128, LWE:$lwe, DA:$da), 281 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 282 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da" 283 #!if(BaseOpcode.HasD16, "$d16", ""); 284} 285 286class MIMG_NoSampler_gfx10<mimgopc op, string opcode, 287 RegisterClass DataRC, RegisterClass AddrRC, 288 string dns=""> 289 : MIMG_gfx10<op.BASE, (outs DataRC:$vdata), dns> { 290 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask, 291 Dim:$dim, UNorm:$unorm, CPol:$cpol, 292 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 293 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 294 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" 295 #!if(BaseOpcode.HasD16, "$d16", ""); 296} 297 298class MIMG_NoSampler_nsa_gfx10<mimgopc op, string opcode, 299 RegisterClass DataRC, int num_addrs, 300 string dns=""> 301 : MIMG_nsa_gfx10<op.BASE, (outs DataRC:$vdata), num_addrs, dns> { 302 let InOperandList = !con(AddrIns, 303 (ins SReg_256:$srsrc, DMask:$dmask, 304 Dim:$dim, UNorm:$unorm, CPol:$cpol, 305 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 306 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 307 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" 308 #!if(BaseOpcode.HasD16, "$d16", ""); 309} 310 311multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm, 312 RegisterClass dst_rc, 313 bit enableDisasm, 314 bit ExtendedImageInst = 1> { 315 let ssamp = 0 in { 316 let VAddrDwords = 1 in { 317 if op.HAS_BASE then { 318 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32, 319 !if(enableDisasm, "AMDGPU", "")>; 320 foreach _ = BoolToList<!eq(ExtendedImageInst, 0)>.ret in 321 def _V1_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPR_32, 322 !if(enableDisasm, "GFX90A", "")>; 323 def _V1_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPR_32, 324 !if(enableDisasm, "AMDGPU", "")>; 325 } 326 } 327 328 let VAddrDwords = 2 in { 329 if op.HAS_BASE then { 330 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>; 331 foreach _ = BoolToList<!eq(ExtendedImageInst, 0)>.ret in 332 def _V2_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_64>; 333 def _V2_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_64>; 334 def _V2_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 2>; 335 } 336 } 337 338 let VAddrDwords = 3 in { 339 if op.HAS_BASE then { 340 def _V3 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_96>; 341 foreach _ = BoolToList<!eq(ExtendedImageInst, 0)>.ret in 342 def _V3_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_96>; 343 def _V3_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_96>; 344 def _V3_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 3>; 345 } 346 } 347 348 let VAddrDwords = 4 in { 349 if op.HAS_BASE then { 350 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>; 351 foreach _ = BoolToList<!eq(ExtendedImageInst, 0)>.ret in 352 def _V4_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_128>; 353 def _V4_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_128>; 354 def _V4_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 4, 355 !if(enableDisasm, "AMDGPU", "")>; 356 } 357 } 358 } 359} 360 361multiclass MIMG_NoSampler <mimgopc op, string asm, bit has_d16, bit mip = 0, 362 bit isResInfo = 0, 363 bit msaa = 0> { 364 def "" : MIMGBaseOpcode { 365 let Coordinates = !not(isResInfo); 366 let LodOrClampOrMip = mip; 367 let HasD16 = has_d16; 368 let MSAA = msaa; 369 } 370 371 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), 372 mayLoad = !not(isResInfo) in { 373 let VDataDwords = 1 in 374 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1, msaa>; 375 let VDataDwords = 2 in 376 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 0, msaa>; 377 let VDataDwords = 3 in 378 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 0, msaa>; 379 let VDataDwords = 4 in 380 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 0, msaa>; 381 let VDataDwords = 5 in 382 defm _V5 : MIMG_NoSampler_Src_Helper <op, asm, VReg_160, 0, msaa>; 383 } 384} 385 386class MIMG_Store_Helper <mimgopc op, string asm, 387 RegisterClass data_rc, 388 RegisterClass addr_rc, 389 string dns = ""> 390 : MIMG_gfx6789<op.BASE, (outs), dns> { 391 let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, 392 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 393 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 394 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 395 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da" 396 #!if(BaseOpcode.HasD16, "$d16", ""); 397} 398 399class MIMG_Store_Helper_gfx90a <mimgopc op, string asm, 400 RegisterClass data_rc, 401 RegisterClass addr_rc, 402 string dns = ""> 403 : MIMG_gfx90a<op.BASE, (outs), dns> { 404 let InOperandList = !con((ins getLdStRegisterOperand<data_rc>.ret:$vdata, 405 addr_rc:$vaddr, SReg_256:$srsrc, 406 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 407 R128A16:$r128, LWE:$lwe, DA:$da), 408 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 409 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da" 410 #!if(BaseOpcode.HasD16, "$d16", ""); 411} 412 413class MIMG_Store_gfx10<mimgopc op, string opcode, 414 RegisterClass DataRC, RegisterClass AddrRC, 415 string dns=""> 416 : MIMG_gfx10<op.BASE, (outs), dns> { 417 let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc, 418 DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol, 419 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 420 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 421 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" 422 #!if(BaseOpcode.HasD16, "$d16", ""); 423} 424 425class MIMG_Store_nsa_gfx10<mimgopc op, string opcode, 426 RegisterClass DataRC, int num_addrs, 427 string dns=""> 428 : MIMG_nsa_gfx10<op.BASE, (outs), num_addrs, dns> { 429 let InOperandList = !con((ins DataRC:$vdata), 430 AddrIns, 431 (ins SReg_256:$srsrc, DMask:$dmask, 432 Dim:$dim, UNorm:$unorm, CPol:$cpol, 433 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 434 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 435 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" 436 #!if(BaseOpcode.HasD16, "$d16", ""); 437} 438 439multiclass MIMG_Store_Addr_Helper <mimgopc op, string asm, 440 RegisterClass data_rc, 441 bit enableDisasm> { 442 let mayLoad = 0, mayStore = 1, hasSideEffects = 0, hasPostISelHook = 0, 443 DisableWQM = 1, ssamp = 0 in { 444 let VAddrDwords = 1 in { 445 if op.HAS_BASE then { 446 def _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32, 447 !if(enableDisasm, "AMDGPU", "")>; 448 def _V1_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VGPR_32, 449 !if(enableDisasm, "GFX90A", "")>; 450 def _V1_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VGPR_32, 451 !if(enableDisasm, "AMDGPU", "")>; 452 } 453 } 454 let VAddrDwords = 2 in { 455 if op.HAS_BASE then { 456 def _V2 : MIMG_Store_Helper <op, asm, data_rc, VReg_64>; 457 def _V2_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_64>; 458 def _V2_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_64>; 459 def _V2_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 2>; 460 } 461 } 462 let VAddrDwords = 3 in { 463 if op.HAS_BASE then { 464 def _V3 : MIMG_Store_Helper <op, asm, data_rc, VReg_96>; 465 def _V3_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_96>; 466 def _V3_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_96>; 467 def _V3_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 3>; 468 } 469 } 470 let VAddrDwords = 4 in { 471 if op.HAS_BASE then { 472 def _V4 : MIMG_Store_Helper <op, asm, data_rc, VReg_128>; 473 def _V4_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_128>; 474 def _V4_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_128>; 475 def _V4_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 4, 476 !if(enableDisasm, "AMDGPU", "")>; 477 } 478 } 479 } 480} 481 482multiclass MIMG_Store <mimgopc op, string asm, bit has_d16, bit mip = 0> { 483 def "" : MIMGBaseOpcode { 484 let Store = 1; 485 let LodOrClampOrMip = mip; 486 let HasD16 = has_d16; 487 } 488 489 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in { 490 let VDataDwords = 1 in 491 defm _V1 : MIMG_Store_Addr_Helper <op, asm, VGPR_32, 1>; 492 let VDataDwords = 2 in 493 defm _V2 : MIMG_Store_Addr_Helper <op, asm, VReg_64, 0>; 494 let VDataDwords = 3 in 495 defm _V3 : MIMG_Store_Addr_Helper <op, asm, VReg_96, 0>; 496 let VDataDwords = 4 in 497 defm _V4 : MIMG_Store_Addr_Helper <op, asm, VReg_128, 0>; 498 let VDataDwords = 5 in 499 defm _V5 : MIMG_Store_Addr_Helper <op, asm, VReg_160, 0>; 500 } 501} 502 503class MIMG_Atomic_gfx6789_base <bits<8> op, string asm, RegisterClass data_rc, 504 RegisterClass addr_rc, string dns=""> 505 : MIMG_gfx6789 <op, (outs data_rc:$vdst), dns> { 506 let Constraints = "$vdst = $vdata"; 507 let AsmMatchConverter = "cvtMIMGAtomic"; 508 509 let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, 510 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 511 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da); 512 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da"; 513} 514 515class MIMG_Atomic_gfx90a_base <bits<8> op, string asm, RegisterClass data_rc, 516 RegisterClass addr_rc, string dns=""> 517 : MIMG_gfx90a <op, (outs getLdStRegisterOperand<data_rc>.ret:$vdst), dns> { 518 let Constraints = "$vdst = $vdata"; 519 let AsmMatchConverter = "cvtMIMGAtomic"; 520 521 let InOperandList = (ins getLdStRegisterOperand<data_rc>.ret:$vdata, 522 addr_rc:$vaddr, SReg_256:$srsrc, 523 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 524 R128A16:$r128, LWE:$lwe, DA:$da); 525 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da"; 526} 527 528class MIMG_Atomic_si<mimgopc op, string asm, RegisterClass data_rc, 529 RegisterClass addr_rc, bit enableDasm = 0> 530 : MIMG_Atomic_gfx6789_base<op.SI, asm, data_rc, addr_rc, 531 !if(enableDasm, "GFX6GFX7", "")> { 532 let AssemblerPredicate = isGFX6GFX7; 533} 534 535class MIMG_Atomic_vi<mimgopc op, string asm, RegisterClass data_rc, 536 RegisterClass addr_rc, bit enableDasm = 0> 537 : MIMG_Atomic_gfx6789_base<op.VI, asm, data_rc, addr_rc, !if(enableDasm, "GFX8", "")> { 538 let AssemblerPredicate = isGFX8GFX9NotGFX90A; 539 let MIMGEncoding = MIMGEncGfx8; 540} 541 542class MIMG_Atomic_gfx90a<mimgopc op, string asm, RegisterClass data_rc, 543 RegisterClass addr_rc, bit enableDasm = 0> 544 : MIMG_Atomic_gfx90a_base<op.VI, asm, data_rc, addr_rc, !if(enableDasm, "GFX90A", "")> { 545 let AssemblerPredicate = isGFX90APlus; 546 let MIMGEncoding = MIMGEncGfx90a; 547} 548 549class MIMG_Atomic_gfx10<mimgopc op, string opcode, 550 RegisterClass DataRC, RegisterClass AddrRC, 551 bit enableDisasm = 0> 552 : MIMG_gfx10<!cast<int>(op.BASE), (outs DataRC:$vdst), 553 !if(enableDisasm, "AMDGPU", "")> { 554 let Constraints = "$vdst = $vdata"; 555 let AsmMatchConverter = "cvtMIMGAtomic"; 556 557 let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc, 558 DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol, 559 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe); 560 let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"; 561} 562 563class MIMG_Atomic_nsa_gfx10<mimgopc op, string opcode, 564 RegisterClass DataRC, int num_addrs, 565 bit enableDisasm = 0> 566 : MIMG_nsa_gfx10<!cast<int>(op.BASE), (outs DataRC:$vdst), num_addrs, 567 !if(enableDisasm, "AMDGPU", "")> { 568 let Constraints = "$vdst = $vdata"; 569 let AsmMatchConverter = "cvtMIMGAtomic"; 570 571 let InOperandList = !con((ins DataRC:$vdata), 572 AddrIns, 573 (ins SReg_256:$srsrc, DMask:$dmask, 574 Dim:$dim, UNorm:$unorm, CPol:$cpol, 575 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe)); 576 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"; 577} 578 579multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm, 580 RegisterClass data_rc, 581 bit enableDasm = 0, 582 bit isFP = 0> { 583 let hasSideEffects = 1, // FIXME: remove this 584 mayLoad = 1, mayStore = 1, hasPostISelHook = 0, DisableWQM = 1, 585 ssamp = 0, FPAtomic = isFP in { 586 let VAddrDwords = 1 in { 587 if op.HAS_SI then { 588 def _V1_si : MIMG_Atomic_si <op, asm, data_rc, VGPR_32, enableDasm>; 589 } 590 if op.HAS_VI then { 591 def _V1_vi : MIMG_Atomic_vi <op, asm, data_rc, VGPR_32, enableDasm>; 592 def _V1_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VGPR_32, enableDasm>; 593 } 594 if op.HAS_BASE then { 595 def _V1_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VGPR_32, enableDasm>; 596 } 597 } 598 let VAddrDwords = 2 in { 599 if op.HAS_SI then { 600 def _V2_si : MIMG_Atomic_si <op, asm, data_rc, VReg_64, 0>; 601 } 602 if op.HAS_VI then { 603 def _V2_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_64, 0>; 604 def _V2_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_64, 0>; 605 } 606 if op.HAS_BASE then { 607 def _V2_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_64, 0>; 608 def _V2_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 2, 0>; 609 } 610 } 611 let VAddrDwords = 3 in { 612 if op.HAS_SI then { 613 def _V3_si : MIMG_Atomic_si <op, asm, data_rc, VReg_96, 0>; 614 } 615 if op.HAS_VI then { 616 def _V3_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_96, 0>; 617 def _V3_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_96, 0>; 618 } 619 if op.HAS_BASE then { 620 def _V3_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_96, 0>; 621 def _V3_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 3, 0>; 622 } 623 } 624 let VAddrDwords = 4 in { 625 if op.HAS_SI then { 626 def _V4_si : MIMG_Atomic_si <op, asm, data_rc, VReg_128, 0>; 627 } 628 if op.HAS_VI then { 629 def _V4_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_128, 0>; 630 def _V4_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_128, 0>; 631 } 632 if op.HAS_BASE then { 633 def _V4_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_128, 0>; 634 def _V4_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 4, enableDasm>; 635 } 636 } 637 } 638} 639 640multiclass MIMG_Atomic <mimgopc op, string asm, bit isCmpSwap = 0, bit isFP = 0> { // 64-bit atomics 641 let IsAtomicRet = 1 in { 642 def "" : MIMGBaseOpcode { 643 let Atomic = 1; 644 let AtomicX2 = isCmpSwap; 645 } 646 647 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in { 648 // _V* variants have different dst size, but the size is encoded implicitly, 649 // using dmask and tfe. Only 32-bit variant is registered with disassembler. 650 // Other variants are reconstructed by disassembler using dmask and tfe. 651 let VDataDwords = !if(isCmpSwap, 2, 1) in 652 defm _V1 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_64, VGPR_32), 1, isFP>; 653 let VDataDwords = !if(isCmpSwap, 4, 2) in 654 defm _V2 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_128, VReg_64), 0, isFP>; 655 } 656 } // End IsAtomicRet = 1 657} 658 659class MIMG_Sampler_Helper <mimgopc op, string asm, RegisterClass dst_rc, 660 RegisterClass src_rc, string dns=""> 661 : MIMG_gfx6789 <op.BASE, (outs dst_rc:$vdata), dns> { 662 let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp, 663 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 664 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 665 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 666 let AsmString = asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$cpol$r128$tfe$lwe$da" 667 #!if(BaseOpcode.HasD16, "$d16", ""); 668} 669 670class MIMG_Sampler_gfx90a<mimgopc op, string asm, RegisterClass dst_rc, 671 RegisterClass src_rc, string dns=""> 672 : MIMG_gfx90a<op.BASE, (outs getLdStRegisterOperand<dst_rc>.ret:$vdata), dns> { 673 let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp, 674 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 675 R128A16:$r128, LWE:$lwe, DA:$da), 676 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 677 let AsmString = asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$cpol$r128$lwe$da" 678 #!if(BaseOpcode.HasD16, "$d16", ""); 679} 680 681class MIMG_Sampler_gfx10<mimgopc op, string opcode, 682 RegisterClass DataRC, RegisterClass AddrRC, 683 string dns=""> 684 : MIMG_gfx10<op.BASE, (outs DataRC:$vdata), dns> { 685 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, SReg_128:$ssamp, 686 DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol, 687 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 688 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 689 let AsmString = opcode#" $vdata, $vaddr0, $srsrc, $ssamp$dmask$dim$unorm" 690 #"$cpol$r128$a16$tfe$lwe" 691 #!if(BaseOpcode.HasD16, "$d16", ""); 692} 693 694class MIMG_Sampler_nsa_gfx10<mimgopc op, string opcode, 695 RegisterClass DataRC, int num_addrs, 696 string dns=""> 697 : MIMG_nsa_gfx10<op.BASE, (outs DataRC:$vdata), num_addrs, dns> { 698 let InOperandList = !con(AddrIns, 699 (ins SReg_256:$srsrc, SReg_128:$ssamp, DMask:$dmask, 700 Dim:$dim, UNorm:$unorm, CPol:$cpol, 701 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 702 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 703 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc, $ssamp$dmask$dim$unorm" 704 #"$cpol$r128$a16$tfe$lwe" 705 #!if(BaseOpcode.HasD16, "$d16", ""); 706} 707 708class MIMGAddrSize<int dw, bit enable_disasm> { 709 int NumWords = dw; 710 711 RegisterClass RegClass = !if(!le(NumWords, 0), ?, 712 !if(!eq(NumWords, 1), VGPR_32, 713 !if(!eq(NumWords, 2), VReg_64, 714 !if(!eq(NumWords, 3), VReg_96, 715 !if(!eq(NumWords, 4), VReg_128, 716 !if(!le(NumWords, 8), VReg_256, 717 !if(!le(NumWords, 16), VReg_512, ?))))))); 718 719 // Whether the instruction variant with this vaddr size should be enabled for 720 // the auto-generated disassembler. 721 bit Disassemble = enable_disasm; 722} 723 724// Return whether x is in lst. 725class isIntInList<int x, list<int> lst> { 726 bit ret = !foldl(0, lst, lhs, y, !or(lhs, !eq(x, y))); 727} 728 729// Return whether a value inside the range [min, max] (endpoints inclusive) 730// is in the given list. 731class isRangeInList<int min, int max, list<int> lst> { 732 bit ret = !foldl(0, lst, lhs, y, !or(lhs, !and(!le(min, y), !le(y, max)))); 733} 734 735class MIMGAddrSizes_tmp<list<MIMGAddrSize> lst, int min> { 736 list<MIMGAddrSize> List = lst; 737 int Min = min; 738} 739 740class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample> { 741 // List of all possible numbers of address words, taking all combinations of 742 // A16 and image dimension into account (note: no MSAA, since this is for 743 // sample/gather ops). 744 list<int> AllNumAddrWords = 745 !foreach(dw, !if(sample.Gradients, 746 !if(!eq(sample.LodOrClamp, ""), 747 [2, 3, 4, 5, 6, 7, 9], 748 [2, 3, 4, 5, 7, 8, 10]), 749 !if(!eq(sample.LodOrClamp, ""), 750 [1, 2, 3], 751 [1, 2, 3, 4])), 752 !add(dw, !size(sample.ExtraAddrArgs))); 753 754 // Generate machine instructions based on possible register classes for the 755 // required numbers of address words. The disassembler defaults to the 756 // smallest register class. 757 list<MIMGAddrSize> MachineInstrs = 758 !foldl(MIMGAddrSizes_tmp<[], 0>, [1, 2, 3, 4, 8, 16], lhs, dw, 759 !if(isRangeInList<lhs.Min, dw, AllNumAddrWords>.ret, 760 MIMGAddrSizes_tmp< 761 !listconcat(lhs.List, [MIMGAddrSize<dw, !empty(lhs.List)>]), 762 !if(!eq(dw, 3), 3, !add(dw, 1))>, // we still need _V4 for codegen w/ 3 dwords 763 lhs)).List; 764 765 // For NSA, generate machine instructions for all possible numbers of words 766 // except 1 (which is already covered by the non-NSA case). 767 // The disassembler defaults to the largest number of arguments among the 768 // variants with the same number of NSA words, and custom code then derives 769 // the exact variant based on the sample variant and the image dimension. 770 list<MIMGAddrSize> NSAInstrs = 771 !foldl([]<MIMGAddrSize>, [[12, 11, 10], [9, 8, 7, 6], [5, 4, 3, 2]], prev, nsa_group, 772 !listconcat(prev, 773 !foldl([]<MIMGAddrSize>, nsa_group, lhs, dw, 774 !if(isIntInList<dw, AllNumAddrWords>.ret, 775 !listconcat(lhs, [MIMGAddrSize<dw, !empty(lhs)>]), 776 lhs)))); 777} 778 779multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm, 780 AMDGPUSampleVariant sample, RegisterClass dst_rc, 781 bit enableDisasm = 0, 782 bit ExtendedImageInst = 1> { 783 foreach addr = MIMG_Sampler_AddrSizes<sample>.MachineInstrs in { 784 let VAddrDwords = addr.NumWords in { 785 if op.HAS_BASE then { 786 def _V # addr.NumWords 787 : MIMG_Sampler_Helper <op, asm, dst_rc, addr.RegClass, 788 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 789 foreach _ = BoolToList<!eq(ExtendedImageInst, 0)>.ret in 790 def _V # addr.NumWords # _gfx90a 791 : MIMG_Sampler_gfx90a <op, asm, dst_rc, addr.RegClass, 792 !if(!and(enableDisasm, addr.Disassemble), "GFX90A", "")>; 793 def _V # addr.NumWords # _gfx10 794 : MIMG_Sampler_gfx10 <op, asm, dst_rc, addr.RegClass, 795 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 796 } 797 } 798 } 799 800 foreach addr = MIMG_Sampler_AddrSizes<sample>.NSAInstrs in { 801 let VAddrDwords = addr.NumWords in { 802 if op.HAS_BASE then { 803 def _V # addr.NumWords # _nsa_gfx10 804 : MIMG_Sampler_nsa_gfx10<op, asm, dst_rc, addr.NumWords, 805 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 806 } 807 } 808 } 809} 810 811class MIMG_Sampler_BaseOpcode<AMDGPUSampleVariant sample> 812 : MIMGBaseOpcode { 813 let Sampler = 1; 814 let NumExtraArgs = !size(sample.ExtraAddrArgs); 815 let Gradients = sample.Gradients; 816 let LodOrClampOrMip = !ne(sample.LodOrClamp, ""); 817} 818 819multiclass MIMG_Sampler <mimgopc op, AMDGPUSampleVariant sample, bit wqm = 0, 820 bit isG16 = 0, bit isGetLod = 0, 821 string asm = "image_sample"#sample.LowerCaseMod#!if(isG16, "_g16", ""), 822 bit ExtendedImageInst = !ne(sample.LowerCaseMod, "")> { 823 def "" : MIMG_Sampler_BaseOpcode<sample> { 824 let HasD16 = !not(isGetLod); 825 let G16 = isG16; 826 } 827 828 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm, 829 mayLoad = !not(isGetLod) in { 830 let VDataDwords = 1 in 831 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, sample, VGPR_32, 1, ExtendedImageInst>; 832 let VDataDwords = 2 in 833 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64, 0, ExtendedImageInst>; 834 let VDataDwords = 3 in 835 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_96, 0, ExtendedImageInst>; 836 let VDataDwords = 4 in 837 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 0, ExtendedImageInst>; 838 let VDataDwords = 5 in 839 defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160, 0, ExtendedImageInst>; 840 } 841} 842 843multiclass MIMG_Sampler_WQM <mimgopc op, AMDGPUSampleVariant sample> 844 : MIMG_Sampler<op, sample, 1>; 845 846multiclass MIMG_Gather <mimgopc op, AMDGPUSampleVariant sample, bit wqm = 0, 847 string asm = "image_gather4"#sample.LowerCaseMod> { 848 def "" : MIMG_Sampler_BaseOpcode<sample> { 849 let HasD16 = 1; 850 let Gather4 = 1; 851 } 852 853 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm, 854 Gather4 = 1, hasPostISelHook = 0 in { 855 let VDataDwords = 2 in 856 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64>; /* for packed D16 only */ 857 let VDataDwords = 4 in 858 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 1>; 859 let VDataDwords = 5 in 860 defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160>; 861 } 862} 863 864multiclass MIMG_Gather_WQM <mimgopc op, AMDGPUSampleVariant sample> 865 : MIMG_Gather<op, sample, 1>; 866 867class MIMG_IntersectRay_gfx10<mimgopc op, string opcode, RegisterClass AddrRC, bit A16> 868 : MIMG_gfx10<op.BASE, (outs VReg_128:$vdata), "AMDGPU"> { 869 870 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_128:$srsrc), 871 !if(A16, (ins GFX10A16:$a16), (ins))); 872 let AsmString = opcode#" $vdata, $vaddr0, $srsrc"#!if(A16, "$a16", ""); 873 874 let nsa = 0; 875} 876 877class MIMG_IntersectRay_nsa_gfx10<mimgopc op, string opcode, int num_addrs, bit A16> 878 : MIMG_nsa_gfx10<op.BASE, (outs VReg_128:$vdata), num_addrs, "AMDGPU"> { 879 let InOperandList = !con(nsah.AddrIns, 880 (ins SReg_128:$srsrc), 881 !if(A16, (ins GFX10A16:$a16), (ins))); 882 let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc"#!if(A16, "$a16", ""); 883} 884 885multiclass MIMG_IntersectRay<mimgopc op, string opcode, int num_addrs, bit A16> { 886 def "" : MIMGBaseOpcode; 887 let SubtargetPredicate = HasGFX10_BEncoding, 888 AssemblerPredicate = HasGFX10_BEncoding, 889 AsmMatchConverter = !if(A16, "cvtIntersectRay", ""), 890 dmask = 0xf, 891 unorm = 1, 892 d16 = 0, 893 cpol = 0, 894 tfe = 0, 895 lwe = 0, 896 r128 = 1, 897 ssamp = 0, 898 dim = {0, 0, 0}, 899 a16 = A16, 900 d16 = 0, 901 BaseOpcode = !cast<MIMGBaseOpcode>(NAME), 902 VDataDwords = 4 in { 903 // TODO: MIMGAddrSize will choose VReg_512 which is a 16 register tuple, 904 // when we only need 9, 11 or 12 depending on A16 field and ptr size. 905 def "_sa" : MIMG_IntersectRay_gfx10<op, opcode, MIMGAddrSize<num_addrs, 0>.RegClass, A16> { 906 let VAddrDwords = !srl(MIMGAddrSize<num_addrs, 0>.RegClass.Size, 5); 907 } 908 def _nsa : MIMG_IntersectRay_nsa_gfx10<op, opcode, num_addrs, A16> { 909 let VAddrDwords = num_addrs; 910 } 911 } 912} 913 914//===----------------------------------------------------------------------===// 915// MIMG Instructions 916//===----------------------------------------------------------------------===// 917defm IMAGE_LOAD : MIMG_NoSampler <mimgopc<0x00>, "image_load", 1>; 918defm IMAGE_LOAD_MIP : MIMG_NoSampler <mimgopc<0x01>, "image_load_mip", 1, 1>; 919defm IMAGE_LOAD_PCK : MIMG_NoSampler <mimgopc<0x02>, "image_load_pck", 0>; 920defm IMAGE_LOAD_PCK_SGN : MIMG_NoSampler <mimgopc<0x03>, "image_load_pck_sgn", 0>; 921defm IMAGE_LOAD_MIP_PCK : MIMG_NoSampler <mimgopc<0x04>, "image_load_mip_pck", 0, 1>; 922defm IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoSampler <mimgopc<0x05>, "image_load_mip_pck_sgn", 0, 1>; 923defm IMAGE_STORE : MIMG_Store <mimgopc<0x08>, "image_store", 1>; 924defm IMAGE_STORE_MIP : MIMG_Store <mimgopc<0x09>, "image_store_mip", 1, 1>; 925defm IMAGE_STORE_PCK : MIMG_Store <mimgopc<0x0a>, "image_store_pck", 0>; 926defm IMAGE_STORE_MIP_PCK : MIMG_Store <mimgopc<0x0b>, "image_store_mip_pck", 0, 1>; 927 928defm IMAGE_GET_RESINFO : MIMG_NoSampler <mimgopc<0x0e>, "image_get_resinfo", 0, 1, 1>; 929 930defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimgopc<0x0f, 0x10, 0x0f>, "image_atomic_swap">; 931defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimgopc<0x10, 0x11, 0x10>, "image_atomic_cmpswap", 1>; 932defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimgopc<0x11, 0x12, 0x11>, "image_atomic_add">; 933defm IMAGE_ATOMIC_SUB : MIMG_Atomic <mimgopc<0x12, 0x13, 0x12>, "image_atomic_sub">; 934defm IMAGE_ATOMIC_RSUB : MIMG_Atomic <mimgopc<MIMG.NOP, MIMG.NOP, 0x13>, "image_atomic_rsub">; 935defm IMAGE_ATOMIC_SMIN : MIMG_Atomic <mimgopc<0x14>, "image_atomic_smin">; 936defm IMAGE_ATOMIC_UMIN : MIMG_Atomic <mimgopc<0x15>, "image_atomic_umin">; 937defm IMAGE_ATOMIC_SMAX : MIMG_Atomic <mimgopc<0x16>, "image_atomic_smax">; 938defm IMAGE_ATOMIC_UMAX : MIMG_Atomic <mimgopc<0x17>, "image_atomic_umax">; 939defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimgopc<0x18>, "image_atomic_and">; 940defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimgopc<0x19>, "image_atomic_or">; 941defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimgopc<0x1a>, "image_atomic_xor">; 942defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimgopc<0x1b>, "image_atomic_inc">; 943defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimgopc<0x1c>, "image_atomic_dec">; 944defm IMAGE_ATOMIC_FCMPSWAP : MIMG_Atomic <mimgopc<0x1d, MIMG.NOP>, "image_atomic_fcmpswap", 0, 1>; 945defm IMAGE_ATOMIC_FMIN : MIMG_Atomic <mimgopc<0x1e, MIMG.NOP>, "image_atomic_fmin", 0, 1>; 946defm IMAGE_ATOMIC_FMAX : MIMG_Atomic <mimgopc<0x1f, MIMG.NOP>, "image_atomic_fmax", 0, 1>; 947 948defm IMAGE_SAMPLE : MIMG_Sampler_WQM <mimgopc<0x20>, AMDGPUSample>; 949let OtherPredicates = [HasExtendedImageInsts] in { 950defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <mimgopc<0x21>, AMDGPUSample_cl>; 951defm IMAGE_SAMPLE_D : MIMG_Sampler <mimgopc<0x22>, AMDGPUSample_d>; 952defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <mimgopc<0x23>, AMDGPUSample_d_cl>; 953defm IMAGE_SAMPLE_D_G16 : MIMG_Sampler <mimgopc<0xa2>, AMDGPUSample_d, 0, 1>; 954defm IMAGE_SAMPLE_D_CL_G16 : MIMG_Sampler <mimgopc<0xa3>, AMDGPUSample_d_cl, 0, 1>; 955defm IMAGE_SAMPLE_L : MIMG_Sampler <mimgopc<0x24>, AMDGPUSample_l>; 956defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <mimgopc<0x25>, AMDGPUSample_b>; 957defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <mimgopc<0x26>, AMDGPUSample_b_cl>; 958defm IMAGE_SAMPLE_LZ : MIMG_Sampler <mimgopc<0x27>, AMDGPUSample_lz>; 959defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <mimgopc<0x28>, AMDGPUSample_c>; 960defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <mimgopc<0x29>, AMDGPUSample_c_cl>; 961defm IMAGE_SAMPLE_C_D : MIMG_Sampler <mimgopc<0x2a>, AMDGPUSample_c_d>; 962defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <mimgopc<0x2b>, AMDGPUSample_c_d_cl>; 963defm IMAGE_SAMPLE_C_D_G16 : MIMG_Sampler <mimgopc<0xaa>, AMDGPUSample_c_d, 0, 1>; 964defm IMAGE_SAMPLE_C_D_CL_G16 : MIMG_Sampler <mimgopc<0xab>, AMDGPUSample_c_d_cl, 0, 1>; 965defm IMAGE_SAMPLE_C_L : MIMG_Sampler <mimgopc<0x2c>, AMDGPUSample_c_l>; 966defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <mimgopc<0x2d>, AMDGPUSample_c_b>; 967defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <mimgopc<0x2e>, AMDGPUSample_c_b_cl>; 968defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <mimgopc<0x2f>, AMDGPUSample_c_lz>; 969defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <mimgopc<0x30>, AMDGPUSample_o>; 970defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <mimgopc<0x31>, AMDGPUSample_cl_o>; 971defm IMAGE_SAMPLE_D_O : MIMG_Sampler <mimgopc<0x32>, AMDGPUSample_d_o>; 972defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <mimgopc<0x33>, AMDGPUSample_d_cl_o>; 973defm IMAGE_SAMPLE_D_O_G16 : MIMG_Sampler <mimgopc<0xb2>, AMDGPUSample_d_o, 0, 1>; 974defm IMAGE_SAMPLE_D_CL_O_G16 : MIMG_Sampler <mimgopc<0xb3>, AMDGPUSample_d_cl_o, 0, 1>; 975defm IMAGE_SAMPLE_L_O : MIMG_Sampler <mimgopc<0x34>, AMDGPUSample_l_o>; 976defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <mimgopc<0x35>, AMDGPUSample_b_o>; 977defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <mimgopc<0x36>, AMDGPUSample_b_cl_o>; 978defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <mimgopc<0x37>, AMDGPUSample_lz_o>; 979defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <mimgopc<0x38>, AMDGPUSample_c_o>; 980defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <mimgopc<0x39>, AMDGPUSample_c_cl_o>; 981defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <mimgopc<0x3a>, AMDGPUSample_c_d_o>; 982defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <mimgopc<0x3b>, AMDGPUSample_c_d_cl_o>; 983defm IMAGE_SAMPLE_C_D_O_G16 : MIMG_Sampler <mimgopc<0xba>, AMDGPUSample_c_d_o, 0, 1>; 984defm IMAGE_SAMPLE_C_D_CL_O_G16 : MIMG_Sampler <mimgopc<0xbb>, AMDGPUSample_c_d_cl_o, 0, 1>; 985defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <mimgopc<0x3c>, AMDGPUSample_c_l_o>; 986defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <mimgopc<0x3e>, AMDGPUSample_c_b_cl_o>; 987defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <mimgopc<0x3d>, AMDGPUSample_c_b_o>; 988defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <mimgopc<0x3f>, AMDGPUSample_c_lz_o>; 989defm IMAGE_GATHER4 : MIMG_Gather_WQM <mimgopc<0x40>, AMDGPUSample>; 990defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <mimgopc<0x41>, AMDGPUSample_cl>; 991defm IMAGE_GATHER4_L : MIMG_Gather <mimgopc<0x44>, AMDGPUSample_l>; 992defm IMAGE_GATHER4_B : MIMG_Gather_WQM <mimgopc<0x45>, AMDGPUSample_b>; 993defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <mimgopc<0x46>, AMDGPUSample_b_cl>; 994defm IMAGE_GATHER4_LZ : MIMG_Gather <mimgopc<0x47>, AMDGPUSample_lz>; 995defm IMAGE_GATHER4_C : MIMG_Gather_WQM <mimgopc<0x48>, AMDGPUSample_c>; 996defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <mimgopc<0x49>, AMDGPUSample_c_cl>; 997defm IMAGE_GATHER4_C_L : MIMG_Gather <mimgopc<0x4c>, AMDGPUSample_c_l>; 998defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <mimgopc<0x4d>, AMDGPUSample_c_b>; 999defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <mimgopc<0x4e>, AMDGPUSample_c_b_cl>; 1000defm IMAGE_GATHER4_C_LZ : MIMG_Gather <mimgopc<0x4f>, AMDGPUSample_c_lz>; 1001defm IMAGE_GATHER4_O : MIMG_Gather_WQM <mimgopc<0x50>, AMDGPUSample_o>; 1002defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <mimgopc<0x51>, AMDGPUSample_cl_o>; 1003defm IMAGE_GATHER4_L_O : MIMG_Gather <mimgopc<0x54>, AMDGPUSample_l_o>; 1004defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <mimgopc<0x55>, AMDGPUSample_b_o>; 1005defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <mimgopc<0x56>, AMDGPUSample_b_cl_o>; 1006defm IMAGE_GATHER4_LZ_O : MIMG_Gather <mimgopc<0x57>, AMDGPUSample_lz_o>; 1007defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <mimgopc<0x58>, AMDGPUSample_c_o>; 1008defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <mimgopc<0x59>, AMDGPUSample_c_cl_o>; 1009defm IMAGE_GATHER4_C_L_O : MIMG_Gather <mimgopc<0x5c>, AMDGPUSample_c_l_o>; 1010defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <mimgopc<0x5d>, AMDGPUSample_c_b_o>; 1011defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <mimgopc<0x5e>, AMDGPUSample_c_b_cl_o>; 1012defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <mimgopc<0x5f>, AMDGPUSample_c_lz_o>; 1013//defm IMAGE_GATHER4H : MIMG_Gather_WQM <mimgopc<0x61>, ?>; 1014 1015defm IMAGE_GET_LOD : MIMG_Sampler <mimgopc<0x60>, AMDGPUSample, 1, 0, 1, "image_get_lod">; 1016 1017defm IMAGE_SAMPLE_CD : MIMG_Sampler <mimgopc<0x68>, AMDGPUSample_cd>; 1018defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <mimgopc<0x69>, AMDGPUSample_cd_cl>; 1019defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <mimgopc<0x6a>, AMDGPUSample_c_cd>; 1020defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <mimgopc<0x6b>, AMDGPUSample_c_cd_cl>; 1021defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <mimgopc<0x6c>, AMDGPUSample_cd_o>; 1022defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <mimgopc<0x6d>, AMDGPUSample_cd_cl_o>; 1023defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <mimgopc<0x6e>, AMDGPUSample_c_cd_o>; 1024defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <mimgopc<0x6f>, AMDGPUSample_c_cd_cl_o>; 1025defm IMAGE_SAMPLE_CD_G16 : MIMG_Sampler <mimgopc<0xe8>, AMDGPUSample_cd, 0, 1>; 1026defm IMAGE_SAMPLE_CD_CL_G16 : MIMG_Sampler <mimgopc<0xe9>, AMDGPUSample_cd_cl, 0, 1>; 1027defm IMAGE_SAMPLE_C_CD_G16 : MIMG_Sampler <mimgopc<0xea>, AMDGPUSample_c_cd, 0, 1>; 1028defm IMAGE_SAMPLE_C_CD_CL_G16 : MIMG_Sampler <mimgopc<0xeb>, AMDGPUSample_c_cd_cl, 0, 1>; 1029defm IMAGE_SAMPLE_CD_O_G16 : MIMG_Sampler <mimgopc<0xec>, AMDGPUSample_cd_o, 0, 1>; 1030defm IMAGE_SAMPLE_CD_CL_O_G16 : MIMG_Sampler <mimgopc<0xed>, AMDGPUSample_cd_cl_o, 0, 1>; 1031defm IMAGE_SAMPLE_C_CD_O_G16 : MIMG_Sampler <mimgopc<0xee>, AMDGPUSample_c_cd_o, 0, 1>; 1032defm IMAGE_SAMPLE_C_CD_CL_O_G16 : MIMG_Sampler <mimgopc<0xef>, AMDGPUSample_c_cd_cl_o, 0, 1>; 1033} // End OtherPredicates = [HasExtendedImageInsts] 1034//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>; 1035//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>; 1036 1037let SubtargetPredicate = HasGFX10_BEncoding in 1038defm IMAGE_MSAA_LOAD_X : MIMG_NoSampler <mimgopc<0x80>, "image_msaa_load", 1, 0, 0, 1>; 1039 1040defm IMAGE_BVH_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<0xe6>, "image_bvh_intersect_ray", 11, 0>; 1041defm IMAGE_BVH_INTERSECT_RAY_a16 : MIMG_IntersectRay<mimgopc<0xe6>, "image_bvh_intersect_ray", 8, 1>; 1042defm IMAGE_BVH64_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<0xe7>, "image_bvh64_intersect_ray", 12, 0>; 1043defm IMAGE_BVH64_INTERSECT_RAY_a16 : MIMG_IntersectRay<mimgopc<0xe7>, "image_bvh64_intersect_ray", 9, 1>; 1044 1045/********** ========================================= **********/ 1046/********** Table of dimension-aware image intrinsics **********/ 1047/********** ========================================= **********/ 1048 1049class ImageDimIntrinsicInfo<AMDGPUImageDimIntrinsic I> { 1050 Intrinsic Intr = I; 1051 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(!strconcat("IMAGE_", I.P.OpMod)); 1052 AMDGPUDimProps Dim = I.P.Dim; 1053 AMDGPUImageDimIntrinsicEval DimEval = AMDGPUImageDimIntrinsicEval<I.P>; 1054 1055 bits<8> NumGradients = DimEval.NumGradientArgs; 1056 bits<8> NumDmask = DimEval.NumDmaskArgs; 1057 bits<8> NumData = DimEval.NumDataArgs; 1058 bits<8> NumVAddrs = DimEval.NumVAddrArgs; 1059 bits<8> NumArgs = !add(DimEval.CachePolicyArgIndex, 1); 1060 1061 bits<8> DMaskIndex = DimEval.DmaskArgIndex; 1062 bits<8> VAddrStart = DimEval.VAddrArgIndex; 1063 bits<8> GradientStart = DimEval.GradientArgIndex; 1064 bits<8> CoordStart = DimEval.CoordArgIndex; 1065 bits<8> LodIndex = DimEval.LodArgIndex; 1066 bits<8> MipIndex = DimEval.MipArgIndex; 1067 bits<8> VAddrEnd = !add(DimEval.VAddrArgIndex, DimEval.NumVAddrArgs); 1068 bits<8> RsrcIndex = DimEval.RsrcArgIndex; 1069 bits<8> SampIndex = DimEval.SampArgIndex; 1070 bits<8> UnormIndex = DimEval.UnormArgIndex; 1071 bits<8> TexFailCtrlIndex = DimEval.TexFailCtrlArgIndex; 1072 bits<8> CachePolicyIndex = DimEval.CachePolicyArgIndex; 1073 1074 bits<8> GradientTyArg = !add(I.P.NumRetAndDataAnyTypes, 1075 !foldl(0, I.P.ExtraAddrArgs, cnt, arg, !add(cnt, arg.Type.isAny))); 1076 bits<8> CoordTyArg = !add(GradientTyArg, !if(I.P.Gradients, 1, 0)); 1077} 1078 1079def ImageDimIntrinsicTable : GenericTable { 1080 let FilterClass = "ImageDimIntrinsicInfo"; 1081 let Fields = ["Intr", "BaseOpcode", "Dim", "NumGradients", "NumDmask", "NumData", "NumVAddrs", "NumArgs", 1082 "DMaskIndex", "VAddrStart", "GradientStart", "CoordStart", "LodIndex", "MipIndex", "VAddrEnd", 1083 "RsrcIndex", "SampIndex", "UnormIndex", "TexFailCtrlIndex", "CachePolicyIndex", 1084 "GradientTyArg", "CoordTyArg"]; 1085 string TypeOf_BaseOpcode = "MIMGBaseOpcode"; 1086 string TypeOf_Dim = "MIMGDim"; 1087 1088 let PrimaryKey = ["Intr"]; 1089 let PrimaryKeyName = "getImageDimIntrinsicInfo"; 1090 let PrimaryKeyEarlyOut = 1; 1091} 1092 1093def getImageDimInstrinsicByBaseOpcode : SearchIndex { 1094 let Table = ImageDimIntrinsicTable; 1095 let Key = ["BaseOpcode", "Dim"]; 1096} 1097 1098foreach intr = !listconcat(AMDGPUImageDimIntrinsics, 1099 AMDGPUImageDimAtomicIntrinsics) in { 1100 def : ImageDimIntrinsicInfo<intr>; 1101} 1102 1103// L to LZ Optimization Mapping 1104def : MIMGLZMapping<IMAGE_SAMPLE_L, IMAGE_SAMPLE_LZ>; 1105def : MIMGLZMapping<IMAGE_SAMPLE_C_L, IMAGE_SAMPLE_C_LZ>; 1106def : MIMGLZMapping<IMAGE_SAMPLE_L_O, IMAGE_SAMPLE_LZ_O>; 1107def : MIMGLZMapping<IMAGE_SAMPLE_C_L_O, IMAGE_SAMPLE_C_LZ_O>; 1108def : MIMGLZMapping<IMAGE_GATHER4_L, IMAGE_GATHER4_LZ>; 1109def : MIMGLZMapping<IMAGE_GATHER4_C_L, IMAGE_GATHER4_C_LZ>; 1110def : MIMGLZMapping<IMAGE_GATHER4_L_O, IMAGE_GATHER4_LZ_O>; 1111def : MIMGLZMapping<IMAGE_GATHER4_C_L_O, IMAGE_GATHER4_C_LZ_O>; 1112 1113// MIP to NONMIP Optimization Mapping 1114def : MIMGMIPMapping<IMAGE_LOAD_MIP, IMAGE_LOAD>; 1115def : MIMGMIPMapping<IMAGE_STORE_MIP, IMAGE_STORE>; 1116 1117// G to G16 Optimization Mapping 1118def : MIMGG16Mapping<IMAGE_SAMPLE_D, IMAGE_SAMPLE_D_G16>; 1119def : MIMGG16Mapping<IMAGE_SAMPLE_D_CL, IMAGE_SAMPLE_D_CL_G16>; 1120def : MIMGG16Mapping<IMAGE_SAMPLE_C_D, IMAGE_SAMPLE_C_D_G16>; 1121def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_CL, IMAGE_SAMPLE_C_D_CL_G16>; 1122def : MIMGG16Mapping<IMAGE_SAMPLE_D_O, IMAGE_SAMPLE_D_O_G16>; 1123def : MIMGG16Mapping<IMAGE_SAMPLE_D_CL_O, IMAGE_SAMPLE_D_CL_O_G16>; 1124def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_O, IMAGE_SAMPLE_C_D_O_G16>; 1125def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_CL_O, IMAGE_SAMPLE_C_D_CL_O_G16>; 1126def : MIMGG16Mapping<IMAGE_SAMPLE_CD, IMAGE_SAMPLE_CD_G16>; 1127def : MIMGG16Mapping<IMAGE_SAMPLE_CD_CL, IMAGE_SAMPLE_CD_CL_G16>; 1128def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD, IMAGE_SAMPLE_C_CD_G16>; 1129def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_CL, IMAGE_SAMPLE_C_CD_CL_G16>; 1130def : MIMGG16Mapping<IMAGE_SAMPLE_CD_O, IMAGE_SAMPLE_CD_O_G16>; 1131def : MIMGG16Mapping<IMAGE_SAMPLE_CD_CL_O, IMAGE_SAMPLE_CD_CL_O_G16>; 1132def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_O, IMAGE_SAMPLE_C_CD_O_G16>; 1133def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_CL_O, IMAGE_SAMPLE_C_CD_CL_O_G16>; 1134