1//===-- MIMGInstructions.td - MIMG Instruction Definitions ----------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// MIMG-specific encoding families to distinguish between semantically 10// equivalent machine instructions with different encoding. 11// 12// - MIMGEncGfx6: encoding introduced with gfx6 (obsoleted for atomics in gfx8) 13// - MIMGEncGfx8: encoding introduced with gfx8 for atomics 14// - MIMGEncGfx90a: encoding for gfx90a for atomics 15// - MIMGEncGfx10Default: gfx10 default (non-NSA) encoding 16// - MIMGEncGfx10NSA: gfx10 NSA encoding 17class MIMGEncoding; 18 19def MIMGEncGfx6 : MIMGEncoding; 20def MIMGEncGfx8 : MIMGEncoding; 21def MIMGEncGfx90a : MIMGEncoding; 22def MIMGEncGfx10Default : MIMGEncoding; 23def MIMGEncGfx10NSA : MIMGEncoding; 24 25def MIMGEncoding : GenericEnum { 26 let FilterClass = "MIMGEncoding"; 27} 28 29// Represent an ISA-level opcode, independent of the encoding and the 30// vdata/vaddr size. 31class MIMGBaseOpcode : PredicateControl { 32 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME); 33 bit Store = 0; 34 bit Atomic = 0; 35 bit AtomicX2 = 0; // (f)cmpswap 36 bit Sampler = 0; 37 bit Gather4 = 0; 38 bits<8> NumExtraArgs = 0; 39 bit Gradients = 0; 40 bit G16 = 0; 41 bit Coordinates = 1; 42 bit LodOrClampOrMip = 0; 43 bit HasD16 = 0; 44 bit IsAtomicRet = 0; 45 bit MSAA = 0; 46 bit BVH = 0; 47} 48 49def MIMGBaseOpcode : GenericEnum { 50 let FilterClass = "MIMGBaseOpcode"; 51} 52 53def MIMGBaseOpcodesTable : GenericTable { 54 let FilterClass = "MIMGBaseOpcode"; 55 let CppTypeName = "MIMGBaseOpcodeInfo"; 56 let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler", 57 "Gather4", "NumExtraArgs", "Gradients", "G16", "Coordinates", 58 "LodOrClampOrMip", "HasD16", "MSAA", "BVH"]; 59 string TypeOf_BaseOpcode = "MIMGBaseOpcode"; 60 61 let PrimaryKey = ["BaseOpcode"]; 62 let PrimaryKeyName = "getMIMGBaseOpcodeInfo"; 63} 64 65def MIMGDim : GenericEnum { 66 let FilterClass = "AMDGPUDimProps"; 67} 68 69def MIMGDimInfoTable : GenericTable { 70 let FilterClass = "AMDGPUDimProps"; 71 let CppTypeName = "MIMGDimInfo"; 72 let Fields = ["Dim", "NumCoords", "NumGradients", "MSAA", "DA", "Encoding", "AsmSuffix"]; 73 string TypeOf_Dim = "MIMGDim"; 74 75 let PrimaryKey = ["Dim"]; 76 let PrimaryKeyName = "getMIMGDimInfo"; 77} 78 79def getMIMGDimInfoByEncoding : SearchIndex { 80 let Table = MIMGDimInfoTable; 81 let Key = ["Encoding"]; 82} 83 84def getMIMGDimInfoByAsmSuffix : SearchIndex { 85 let Table = MIMGDimInfoTable; 86 let Key = ["AsmSuffix"]; 87} 88 89def MIMG { 90 int NOP = -1; 91} 92 93class mimgopc <int base, int vi = base, int si = base> { 94 field bits<8> BASE = base; // Opcode for all but atomics 95 field bits<8> VI = vi; // VI is only used for atomic instructions 96 field bits<8> SI = si; // SI is only used for atomic instructions 97 bit HAS_BASE = !ne(base, MIMG.NOP); 98 bit HAS_VI = !ne(vi, MIMG.NOP); 99 bit HAS_SI = !ne(si, MIMG.NOP); 100} 101 102class MIMGLZMapping<MIMGBaseOpcode l, MIMGBaseOpcode lz> { 103 MIMGBaseOpcode L = l; 104 MIMGBaseOpcode LZ = lz; 105} 106 107def MIMGLZMappingTable : GenericTable { 108 let FilterClass = "MIMGLZMapping"; 109 let CppTypeName = "MIMGLZMappingInfo"; 110 let Fields = ["L", "LZ"]; 111 string TypeOf_L = "MIMGBaseOpcode"; 112 string TypeOf_LZ = "MIMGBaseOpcode"; 113 114 let PrimaryKey = ["L"]; 115 let PrimaryKeyName = "getMIMGLZMappingInfo"; 116} 117 118class MIMGMIPMapping<MIMGBaseOpcode mip, MIMGBaseOpcode nonmip> { 119 MIMGBaseOpcode MIP = mip; 120 MIMGBaseOpcode NONMIP = nonmip; 121} 122 123def MIMGMIPMappingTable : GenericTable { 124 let FilterClass = "MIMGMIPMapping"; 125 let CppTypeName = "MIMGMIPMappingInfo"; 126 let Fields = ["MIP", "NONMIP"]; 127 string TypeOf_MIP = "MIMGBaseOpcode"; 128 string TypeOf_NONMIP = "MIMGBaseOpcode"; 129 130 let PrimaryKey = ["MIP"]; 131 let PrimaryKeyName = "getMIMGMIPMappingInfo"; 132} 133 134class MIMGBiasMapping<MIMGBaseOpcode bias, MIMGBaseOpcode nobias> { 135 MIMGBaseOpcode Bias = bias; 136 MIMGBaseOpcode NoBias = nobias; 137} 138 139def MIMGBiasMappingTable : GenericTable { 140 let FilterClass = "MIMGBiasMapping"; 141 let CppTypeName = "MIMGBiasMappingInfo"; 142 let Fields = ["Bias", "NoBias"]; 143 string TypeOf_Bias = "MIMGBaseOpcode"; 144 string TypeOf_NoBias = "MIMGBaseOpcode"; 145 146 let PrimaryKey = ["Bias"]; 147 let PrimaryKeyName = "getMIMGBiasMappingInfo"; 148} 149 150class MIMGOffsetMapping<MIMGBaseOpcode offset, MIMGBaseOpcode nooffset> { 151 MIMGBaseOpcode Offset = offset; 152 MIMGBaseOpcode NoOffset = nooffset; 153} 154 155def MIMGOffsetMappingTable : GenericTable { 156 let FilterClass = "MIMGOffsetMapping"; 157 let CppTypeName = "MIMGOffsetMappingInfo"; 158 let Fields = ["Offset", "NoOffset"]; 159 string TypeOf_Offset = "MIMGBaseOpcode"; 160 string TypeOf_NoOffset = "MIMGBaseOpcode"; 161 162 let PrimaryKey = ["Offset"]; 163 let PrimaryKeyName = "getMIMGOffsetMappingInfo"; 164} 165 166class MIMGG16Mapping<MIMGBaseOpcode g, MIMGBaseOpcode g16> { 167 MIMGBaseOpcode G = g; 168 MIMGBaseOpcode G16 = g16; 169} 170 171def MIMGG16MappingTable : GenericTable { 172 let FilterClass = "MIMGG16Mapping"; 173 let CppTypeName = "MIMGG16MappingInfo"; 174 let Fields = ["G", "G16"]; 175 string TypeOf_G = "MIMGBaseOpcode"; 176 string TypeOf_G16 = "MIMGBaseOpcode"; 177 178 let PrimaryKey = ["G"]; 179 let PrimaryKeyName = "getMIMGG16MappingInfo"; 180} 181 182class MIMG_Base <dag outs, string dns = ""> 183 : InstSI <outs, (ins), "", []> { 184 185 let VM_CNT = 1; 186 let EXP_CNT = 1; 187 let MIMG = 1; 188 let Uses = [EXEC]; 189 let mayLoad = 1; 190 let mayStore = 0; 191 let SchedRW = [WriteVMEM]; 192 let UseNamedOperandTable = 1; 193 let hasSideEffects = 0; // XXX ???? 194 195 let DecoderNamespace = dns; 196 let isAsmParserOnly = !eq(dns, ""); 197} 198 199class MIMG <dag outs, string dns = ""> 200 : MIMG_Base <outs, dns> { 201 202 let hasPostISelHook = 1; 203 let AsmMatchConverter = "cvtMIMG"; 204 205 Instruction Opcode = !cast<Instruction>(NAME); 206 MIMGBaseOpcode BaseOpcode; 207 MIMGEncoding MIMGEncoding; 208 bits<8> VDataDwords; 209 bits<8> VAddrDwords; 210} 211 212def MIMGInfoTable : GenericTable { 213 let FilterClass = "MIMG"; 214 let CppTypeName = "MIMGInfo"; 215 let Fields = ["Opcode", "BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"]; 216 string TypeOf_BaseOpcode = "MIMGBaseOpcode"; 217 string TypeOf_MIMGEncoding = "MIMGEncoding"; 218 219 let PrimaryKey = ["BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"]; 220 let PrimaryKeyName = "getMIMGOpcodeHelper"; 221} 222 223def getMIMGInfo : SearchIndex { 224 let Table = MIMGInfoTable; 225 let Key = ["Opcode"]; 226} 227 228// This class used to use !foldl to memoize the AddrAsmNames list. 229// It turned out that that was much slower than using !filter. 230class MIMGNSAHelper<int num_addrs> { 231 list<string> AddrAsmNames = 232 !foreach(i, !filter(i, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11], 233 !lt(i, num_addrs)), "vaddr" # i); 234 dag AddrIns = !dag(ins, !foreach(arg, AddrAsmNames, VGPR_32), AddrAsmNames); 235 string AddrAsm = "[$" # !interleave(AddrAsmNames, ", $") # "]"; 236 237 int NSA = !if(!le(num_addrs, 1), ?, 238 !if(!le(num_addrs, 5), 1, 239 !if(!le(num_addrs, 9), 2, 240 !if(!le(num_addrs, 13), 3, ?)))); 241} 242 243// Base class of all pre-gfx10 MIMG instructions. 244class MIMG_gfx6789<bits<8> op, dag outs, string dns = ""> 245 : MIMG<outs, dns>, MIMGe_gfx6789<op> { 246 let SubtargetPredicate = isGFX6GFX7GFX8GFX9NotGFX90A; 247 let AssemblerPredicate = isGFX6GFX7GFX8GFX9NotGFX90A; 248 249 let MIMGEncoding = MIMGEncGfx6; 250 251 let d16 = !if(BaseOpcode.HasD16, ?, 0); 252} 253 254class MIMG_gfx90a<bits<8> op, dag outs, string dns = ""> 255 : MIMG<outs, dns>, MIMGe_gfx90a<op> { 256 let SubtargetPredicate = isGFX90APlus; 257 let AssemblerPredicate = isGFX90APlus; 258 259 let MIMGEncoding = MIMGEncGfx90a; 260 261 let d16 = !if(BaseOpcode.HasD16, ?, 0); 262} 263 264// Base class of all non-NSA gfx10 MIMG instructions. 265class MIMG_gfx10<int op, dag outs, string dns = ""> 266 : MIMG<outs, dns>, MIMGe_gfx10<op> { 267 let SubtargetPredicate = isGFX10Plus; 268 let AssemblerPredicate = isGFX10Plus; 269 270 let MIMGEncoding = MIMGEncGfx10Default; 271 272 let d16 = !if(BaseOpcode.HasD16, ?, 0); 273 let nsa = 0; 274} 275 276// Base class for all NSA MIMG instructions. 277// Note that 1-dword addresses always use non-NSA variants. 278class MIMG_nsa_gfx10<int op, dag outs, int num_addrs, string dns=""> 279 : MIMG<outs, dns>, MIMGe_gfx10<op> { 280 let SubtargetPredicate = isGFX10Plus; 281 let AssemblerPredicate = isGFX10Plus; 282 283 let MIMGEncoding = MIMGEncGfx10NSA; 284 285 MIMGNSAHelper nsah = MIMGNSAHelper<num_addrs>; 286 dag AddrIns = nsah.AddrIns; 287 string AddrAsm = nsah.AddrAsm; 288 289 let d16 = !if(BaseOpcode.HasD16, ?, 0); 290 let nsa = nsah.NSA; 291} 292 293class MIMG_NoSampler_Helper <mimgopc op, string asm, 294 RegisterClass dst_rc, 295 RegisterClass addr_rc, 296 string dns=""> 297 : MIMG_gfx6789 <op.BASE, (outs dst_rc:$vdata), dns> { 298 let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc, 299 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 300 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 301 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 302 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da" 303 #!if(BaseOpcode.HasD16, "$d16", ""); 304} 305 306class MIMG_NoSampler_Helper_gfx90a <mimgopc op, string asm, 307 RegisterClass dst_rc, 308 RegisterClass addr_rc, 309 string dns=""> 310 : MIMG_gfx90a <op.BASE, (outs getLdStRegisterOperand<dst_rc>.ret:$vdata), dns> { 311 let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc, 312 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 313 R128A16:$r128, LWE:$lwe, DA:$da), 314 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 315 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da" 316 #!if(BaseOpcode.HasD16, "$d16", ""); 317} 318 319class MIMG_NoSampler_gfx10<mimgopc op, string opcode, 320 RegisterClass DataRC, RegisterClass AddrRC, 321 string dns=""> 322 : MIMG_gfx10<op.BASE, (outs DataRC:$vdata), dns> { 323 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask, 324 Dim:$dim, UNorm:$unorm, CPol:$cpol, 325 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 326 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 327 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" 328 #!if(BaseOpcode.HasD16, "$d16", ""); 329} 330 331class MIMG_NoSampler_nsa_gfx10<mimgopc op, string opcode, 332 RegisterClass DataRC, int num_addrs, 333 string dns=""> 334 : MIMG_nsa_gfx10<op.BASE, (outs DataRC:$vdata), num_addrs, dns> { 335 let InOperandList = !con(AddrIns, 336 (ins SReg_256:$srsrc, DMask:$dmask, 337 Dim:$dim, UNorm:$unorm, CPol:$cpol, 338 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 339 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 340 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" 341 #!if(BaseOpcode.HasD16, "$d16", ""); 342} 343 344multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm, 345 RegisterClass dst_rc, 346 bit enableDisasm, 347 bit ExtendedImageInst = 1> { 348 let ssamp = 0 in { 349 let VAddrDwords = 1 in { 350 if op.HAS_BASE then { 351 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32, 352 !if(enableDisasm, "AMDGPU", "")>; 353 if !not(ExtendedImageInst) then 354 def _V1_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPR_32, 355 !if(enableDisasm, "GFX90A", "")>; 356 def _V1_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPR_32, 357 !if(enableDisasm, "AMDGPU", "")>; 358 } 359 } 360 361 let VAddrDwords = 2 in { 362 if op.HAS_BASE then { 363 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>; 364 if !not(ExtendedImageInst) then 365 def _V2_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_64>; 366 def _V2_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_64>; 367 def _V2_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 2>; 368 } 369 } 370 371 let VAddrDwords = 3 in { 372 if op.HAS_BASE then { 373 def _V3 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_96>; 374 if !not(ExtendedImageInst) then 375 def _V3_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_96>; 376 def _V3_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_96>; 377 def _V3_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 3>; 378 } 379 } 380 381 let VAddrDwords = 4 in { 382 if op.HAS_BASE then { 383 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>; 384 if !not(ExtendedImageInst) then 385 def _V4_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_128>; 386 def _V4_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_128>; 387 def _V4_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 4, 388 !if(enableDisasm, "AMDGPU", "")>; 389 } 390 } 391 } 392} 393 394multiclass MIMG_NoSampler <mimgopc op, string asm, bit has_d16, bit mip = 0, 395 bit isResInfo = 0, 396 bit msaa = 0> { 397 def "" : MIMGBaseOpcode { 398 let Coordinates = !not(isResInfo); 399 let LodOrClampOrMip = mip; 400 let HasD16 = has_d16; 401 let MSAA = msaa; 402 } 403 404 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), 405 mayLoad = !not(isResInfo) in { 406 let VDataDwords = 1 in 407 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1, msaa>; 408 let VDataDwords = 2 in 409 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 0, msaa>; 410 let VDataDwords = 3 in 411 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 0, msaa>; 412 let VDataDwords = 4 in 413 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 0, msaa>; 414 let VDataDwords = 5 in 415 defm _V5 : MIMG_NoSampler_Src_Helper <op, asm, VReg_160, 0, msaa>; 416 } 417} 418 419class MIMG_Store_Helper <mimgopc op, string asm, 420 RegisterClass data_rc, 421 RegisterClass addr_rc, 422 string dns = ""> 423 : MIMG_gfx6789<op.BASE, (outs), dns> { 424 let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, 425 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 426 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 427 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 428 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da" 429 #!if(BaseOpcode.HasD16, "$d16", ""); 430} 431 432class MIMG_Store_Helper_gfx90a <mimgopc op, string asm, 433 RegisterClass data_rc, 434 RegisterClass addr_rc, 435 string dns = ""> 436 : MIMG_gfx90a<op.BASE, (outs), dns> { 437 let InOperandList = !con((ins getLdStRegisterOperand<data_rc>.ret:$vdata, 438 addr_rc:$vaddr, SReg_256:$srsrc, 439 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 440 R128A16:$r128, LWE:$lwe, DA:$da), 441 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 442 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da" 443 #!if(BaseOpcode.HasD16, "$d16", ""); 444} 445 446class MIMG_Store_gfx10<mimgopc op, string opcode, 447 RegisterClass DataRC, RegisterClass AddrRC, 448 string dns=""> 449 : MIMG_gfx10<op.BASE, (outs), dns> { 450 let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc, 451 DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol, 452 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 453 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 454 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" 455 #!if(BaseOpcode.HasD16, "$d16", ""); 456} 457 458class MIMG_Store_nsa_gfx10<mimgopc op, string opcode, 459 RegisterClass DataRC, int num_addrs, 460 string dns=""> 461 : MIMG_nsa_gfx10<op.BASE, (outs), num_addrs, dns> { 462 let InOperandList = !con((ins DataRC:$vdata), 463 AddrIns, 464 (ins SReg_256:$srsrc, DMask:$dmask, 465 Dim:$dim, UNorm:$unorm, CPol:$cpol, 466 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 467 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 468 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" 469 #!if(BaseOpcode.HasD16, "$d16", ""); 470} 471 472multiclass MIMG_Store_Addr_Helper <mimgopc op, string asm, 473 RegisterClass data_rc, 474 bit enableDisasm> { 475 let mayLoad = 0, mayStore = 1, hasSideEffects = 0, hasPostISelHook = 0, 476 DisableWQM = 1, ssamp = 0 in { 477 let VAddrDwords = 1 in { 478 if op.HAS_BASE then { 479 def _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32, 480 !if(enableDisasm, "AMDGPU", "")>; 481 let hasPostISelHook = 1 in 482 def _V1_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VGPR_32, 483 !if(enableDisasm, "GFX90A", "")>; 484 def _V1_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VGPR_32, 485 !if(enableDisasm, "AMDGPU", "")>; 486 } 487 } 488 let VAddrDwords = 2 in { 489 if op.HAS_BASE then { 490 def _V2 : MIMG_Store_Helper <op, asm, data_rc, VReg_64>; 491 def _V2_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_64>; 492 def _V2_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_64>; 493 def _V2_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 2>; 494 } 495 } 496 let VAddrDwords = 3 in { 497 if op.HAS_BASE then { 498 def _V3 : MIMG_Store_Helper <op, asm, data_rc, VReg_96>; 499 def _V3_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_96>; 500 def _V3_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_96>; 501 def _V3_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 3>; 502 } 503 } 504 let VAddrDwords = 4 in { 505 if op.HAS_BASE then { 506 def _V4 : MIMG_Store_Helper <op, asm, data_rc, VReg_128>; 507 def _V4_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_128>; 508 def _V4_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_128>; 509 def _V4_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 4, 510 !if(enableDisasm, "AMDGPU", "")>; 511 } 512 } 513 } 514} 515 516multiclass MIMG_Store <mimgopc op, string asm, bit has_d16, bit mip = 0> { 517 def "" : MIMGBaseOpcode { 518 let Store = 1; 519 let LodOrClampOrMip = mip; 520 let HasD16 = has_d16; 521 } 522 523 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in { 524 let VDataDwords = 1 in 525 defm _V1 : MIMG_Store_Addr_Helper <op, asm, VGPR_32, 1>; 526 let VDataDwords = 2 in 527 defm _V2 : MIMG_Store_Addr_Helper <op, asm, VReg_64, 0>; 528 let VDataDwords = 3 in 529 defm _V3 : MIMG_Store_Addr_Helper <op, asm, VReg_96, 0>; 530 let VDataDwords = 4 in 531 defm _V4 : MIMG_Store_Addr_Helper <op, asm, VReg_128, 0>; 532 let VDataDwords = 5 in 533 defm _V5 : MIMG_Store_Addr_Helper <op, asm, VReg_160, 0>; 534 } 535} 536 537class MIMG_Atomic_gfx6789_base <bits<8> op, string asm, RegisterClass data_rc, 538 RegisterClass addr_rc, string dns=""> 539 : MIMG_gfx6789 <op, (outs data_rc:$vdst), dns> { 540 let Constraints = "$vdst = $vdata"; 541 let AsmMatchConverter = "cvtMIMGAtomic"; 542 543 let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, 544 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 545 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da); 546 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da"; 547} 548 549class MIMG_Atomic_gfx90a_base <bits<8> op, string asm, RegisterClass data_rc, 550 RegisterClass addr_rc, string dns=""> 551 : MIMG_gfx90a <op, (outs getLdStRegisterOperand<data_rc>.ret:$vdst), dns> { 552 let Constraints = "$vdst = $vdata"; 553 let AsmMatchConverter = "cvtMIMGAtomic"; 554 555 let InOperandList = (ins getLdStRegisterOperand<data_rc>.ret:$vdata, 556 addr_rc:$vaddr, SReg_256:$srsrc, 557 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 558 R128A16:$r128, LWE:$lwe, DA:$da); 559 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da"; 560} 561 562class MIMG_Atomic_si<mimgopc op, string asm, RegisterClass data_rc, 563 RegisterClass addr_rc, bit enableDasm = 0> 564 : MIMG_Atomic_gfx6789_base<op.SI, asm, data_rc, addr_rc, 565 !if(enableDasm, "GFX6GFX7", "")> { 566 let AssemblerPredicate = isGFX6GFX7; 567} 568 569class MIMG_Atomic_vi<mimgopc op, string asm, RegisterClass data_rc, 570 RegisterClass addr_rc, bit enableDasm = 0> 571 : MIMG_Atomic_gfx6789_base<op.VI, asm, data_rc, addr_rc, !if(enableDasm, "GFX8", "")> { 572 let AssemblerPredicate = isGFX8GFX9NotGFX90A; 573 let MIMGEncoding = MIMGEncGfx8; 574} 575 576class MIMG_Atomic_gfx90a<mimgopc op, string asm, RegisterClass data_rc, 577 RegisterClass addr_rc, bit enableDasm = 0> 578 : MIMG_Atomic_gfx90a_base<op.VI, asm, data_rc, addr_rc, !if(enableDasm, "GFX90A", "")> { 579 let AssemblerPredicate = isGFX90APlus; 580 let MIMGEncoding = MIMGEncGfx90a; 581} 582 583class MIMG_Atomic_gfx10<mimgopc op, string opcode, 584 RegisterClass DataRC, RegisterClass AddrRC, 585 bit enableDisasm = 0> 586 : MIMG_gfx10<!cast<int>(op.BASE), (outs DataRC:$vdst), 587 !if(enableDisasm, "AMDGPU", "")> { 588 let Constraints = "$vdst = $vdata"; 589 let AsmMatchConverter = "cvtMIMGAtomic"; 590 591 let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc, 592 DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol, 593 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe); 594 let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"; 595} 596 597class MIMG_Atomic_nsa_gfx10<mimgopc op, string opcode, 598 RegisterClass DataRC, int num_addrs, 599 bit enableDisasm = 0> 600 : MIMG_nsa_gfx10<!cast<int>(op.BASE), (outs DataRC:$vdst), num_addrs, 601 !if(enableDisasm, "AMDGPU", "")> { 602 let Constraints = "$vdst = $vdata"; 603 let AsmMatchConverter = "cvtMIMGAtomic"; 604 605 let InOperandList = !con((ins DataRC:$vdata), 606 AddrIns, 607 (ins SReg_256:$srsrc, DMask:$dmask, 608 Dim:$dim, UNorm:$unorm, CPol:$cpol, 609 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe)); 610 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"; 611} 612 613multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm, 614 RegisterClass data_rc, 615 bit enableDasm = 0, 616 bit isFP = 0> { 617 let hasSideEffects = 1, // FIXME: remove this 618 mayLoad = 1, mayStore = 1, hasPostISelHook = 0, DisableWQM = 1, 619 ssamp = 0, FPAtomic = isFP in { 620 let VAddrDwords = 1 in { 621 if op.HAS_SI then { 622 def _V1_si : MIMG_Atomic_si <op, asm, data_rc, VGPR_32, enableDasm>; 623 } 624 if op.HAS_VI then { 625 def _V1_vi : MIMG_Atomic_vi <op, asm, data_rc, VGPR_32, enableDasm>; 626 let hasPostISelHook = 1 in 627 def _V1_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VGPR_32, enableDasm>; 628 } 629 if op.HAS_BASE then { 630 def _V1_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VGPR_32, enableDasm>; 631 } 632 } 633 let VAddrDwords = 2 in { 634 if op.HAS_SI then { 635 def _V2_si : MIMG_Atomic_si <op, asm, data_rc, VReg_64, 0>; 636 } 637 if op.HAS_VI then { 638 def _V2_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_64, 0>; 639 def _V2_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_64, 0>; 640 } 641 if op.HAS_BASE then { 642 def _V2_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_64, 0>; 643 def _V2_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 2, 0>; 644 } 645 } 646 let VAddrDwords = 3 in { 647 if op.HAS_SI then { 648 def _V3_si : MIMG_Atomic_si <op, asm, data_rc, VReg_96, 0>; 649 } 650 if op.HAS_VI then { 651 def _V3_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_96, 0>; 652 def _V3_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_96, 0>; 653 } 654 if op.HAS_BASE then { 655 def _V3_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_96, 0>; 656 def _V3_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 3, 0>; 657 } 658 } 659 let VAddrDwords = 4 in { 660 if op.HAS_SI then { 661 def _V4_si : MIMG_Atomic_si <op, asm, data_rc, VReg_128, 0>; 662 } 663 if op.HAS_VI then { 664 def _V4_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_128, 0>; 665 def _V4_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_128, 0>; 666 } 667 if op.HAS_BASE then { 668 def _V4_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_128, 0>; 669 def _V4_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 4, enableDasm>; 670 } 671 } 672 } 673} 674 675multiclass MIMG_Atomic <mimgopc op, string asm, bit isCmpSwap = 0, bit isFP = 0> { // 64-bit atomics 676 let IsAtomicRet = 1 in { 677 def "" : MIMGBaseOpcode { 678 let Atomic = 1; 679 let AtomicX2 = isCmpSwap; 680 } 681 682 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in { 683 // _V* variants have different dst size, but the size is encoded implicitly, 684 // using dmask and tfe. Only 32-bit variant is registered with disassembler. 685 // Other variants are reconstructed by disassembler using dmask and tfe. 686 let VDataDwords = !if(isCmpSwap, 2, 1) in 687 defm _V1 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_64, VGPR_32), 1, isFP>; 688 let VDataDwords = !if(isCmpSwap, 4, 2) in 689 defm _V2 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_128, VReg_64), 0, isFP>; 690 } 691 } // End IsAtomicRet = 1 692} 693 694class MIMG_Sampler_Helper <mimgopc op, string asm, RegisterClass dst_rc, 695 RegisterClass src_rc, string dns=""> 696 : MIMG_gfx6789 <op.BASE, (outs dst_rc:$vdata), dns> { 697 let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp, 698 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 699 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 700 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 701 let AsmString = asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$cpol$r128$tfe$lwe$da" 702 #!if(BaseOpcode.HasD16, "$d16", ""); 703} 704 705class MIMG_Sampler_gfx90a<mimgopc op, string asm, RegisterClass dst_rc, 706 RegisterClass src_rc, string dns=""> 707 : MIMG_gfx90a<op.BASE, (outs getLdStRegisterOperand<dst_rc>.ret:$vdata), dns> { 708 let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp, 709 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 710 R128A16:$r128, LWE:$lwe, DA:$da), 711 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 712 let AsmString = asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$cpol$r128$lwe$da" 713 #!if(BaseOpcode.HasD16, "$d16", ""); 714} 715 716class MIMG_Sampler_gfx10<mimgopc op, string opcode, 717 RegisterClass DataRC, RegisterClass AddrRC, 718 string dns=""> 719 : MIMG_gfx10<op.BASE, (outs DataRC:$vdata), dns> { 720 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, SReg_128:$ssamp, 721 DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol, 722 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 723 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 724 let AsmString = opcode#" $vdata, $vaddr0, $srsrc, $ssamp$dmask$dim$unorm" 725 #"$cpol$r128$a16$tfe$lwe" 726 #!if(BaseOpcode.HasD16, "$d16", ""); 727} 728 729class MIMG_Sampler_nsa_gfx10<mimgopc op, string opcode, 730 RegisterClass DataRC, int num_addrs, 731 string dns=""> 732 : MIMG_nsa_gfx10<op.BASE, (outs DataRC:$vdata), num_addrs, dns> { 733 let InOperandList = !con(AddrIns, 734 (ins SReg_256:$srsrc, SReg_128:$ssamp, DMask:$dmask, 735 Dim:$dim, UNorm:$unorm, CPol:$cpol, 736 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 737 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 738 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc, $ssamp$dmask$dim$unorm" 739 #"$cpol$r128$a16$tfe$lwe" 740 #!if(BaseOpcode.HasD16, "$d16", ""); 741} 742 743class MIMGAddrSize<int dw, bit enable_disasm> { 744 int NumWords = dw; 745 746 RegisterClass RegClass = !if(!le(NumWords, 0), ?, 747 !if(!eq(NumWords, 1), VGPR_32, 748 !if(!eq(NumWords, 2), VReg_64, 749 !if(!eq(NumWords, 3), VReg_96, 750 !if(!eq(NumWords, 4), VReg_128, 751 !if(!eq(NumWords, 5), VReg_160, 752 !if(!eq(NumWords, 6), VReg_192, 753 !if(!eq(NumWords, 7), VReg_224, 754 !if(!le(NumWords, 8), VReg_256, 755 !if(!le(NumWords, 16), VReg_512, ?)))))))))); 756 757 // Whether the instruction variant with this vaddr size should be enabled for 758 // the auto-generated disassembler. 759 bit Disassemble = enable_disasm; 760} 761 762// Return whether x is in lst. 763class isIntInList<int x, list<int> lst> { 764 bit ret = !foldl(0, lst, lhs, y, !or(lhs, !eq(x, y))); 765} 766 767// Return whether a value inside the range [min, max] (endpoints inclusive) 768// is in the given list. 769class isRangeInList<int min, int max, list<int> lst> { 770 bit ret = !foldl(0, lst, lhs, y, !or(lhs, !and(!le(min, y), !le(y, max)))); 771} 772 773class MIMGAddrSizes_dw_range<list<int> range> { 774 int Min = !head(range); 775 int Max = !if(!empty(!tail(range)), Min, !head(!tail(range))); 776} 777 778class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample> { 779 // List of all possible numbers of address words, taking all combinations of 780 // A16 and image dimension into account (note: no MSAA, since this is for 781 // sample/gather ops). 782 list<int> AllNumAddrWords = 783 !foreach(dw, !if(sample.Gradients, 784 !if(!eq(sample.LodOrClamp, ""), 785 [2, 3, 4, 5, 6, 7, 8, 9], 786 [2, 3, 4, 5, 6, 7, 8, 9, 10]), 787 !if(!eq(sample.LodOrClamp, ""), 788 [1, 2, 3], 789 [1, 2, 3, 4])), 790 !add(dw, !size(sample.ExtraAddrArgs))); 791 792 // Generate machine instructions based on possible register classes for the 793 // required numbers of address words. The disassembler defaults to the 794 // smallest register class. 795 list<MIMGAddrSize> MachineInstrs = 796 !foldl([]<MIMGAddrSize>, 797 !foreach(range, 798 // V4 is generated for V3 and V4 799 // V8 is generated for V5 through V8 800 // V16 is generated for V9 through V16 801 [[1],[2],[3],[3,4],[5],[6],[7],[5,8],[9,16]], 802 MIMGAddrSizes_dw_range<range>), 803 lhs, dw, 804 !if(isRangeInList<dw.Min, dw.Max, AllNumAddrWords>.ret, 805 !listconcat(lhs, [MIMGAddrSize<dw.Max, !empty(lhs)>]), 806 lhs)); 807 808 // For NSA, generate machine instructions for all possible numbers of words 809 // except 1 (which is already covered by the non-NSA case). 810 // The disassembler defaults to the largest number of arguments among the 811 // variants with the same number of NSA words, and custom code then derives 812 // the exact variant based on the sample variant and the image dimension. 813 list<MIMGAddrSize> NSAInstrs = 814 !foldl([]<MIMGAddrSize>, [[12, 11, 10], [9, 8, 7, 6], [5, 4, 3, 2]], prev, nsa_group, 815 !listconcat(prev, 816 !foldl([]<MIMGAddrSize>, nsa_group, lhs, dw, 817 !if(isIntInList<dw, AllNumAddrWords>.ret, 818 !listconcat(lhs, [MIMGAddrSize<dw, !empty(lhs)>]), 819 lhs)))); 820} 821 822multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm, 823 AMDGPUSampleVariant sample, RegisterClass dst_rc, 824 bit enableDisasm = 0, 825 bit ExtendedImageInst = 1> { 826 foreach addr = MIMG_Sampler_AddrSizes<sample>.MachineInstrs in { 827 let VAddrDwords = addr.NumWords in { 828 if op.HAS_BASE then { 829 def _V # addr.NumWords 830 : MIMG_Sampler_Helper <op, asm, dst_rc, addr.RegClass, 831 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 832 if !not(ExtendedImageInst) then 833 def _V # addr.NumWords # _gfx90a 834 : MIMG_Sampler_gfx90a <op, asm, dst_rc, addr.RegClass, 835 !if(!and(enableDisasm, addr.Disassemble), "GFX90A", "")>; 836 def _V # addr.NumWords # _gfx10 837 : MIMG_Sampler_gfx10 <op, asm, dst_rc, addr.RegClass, 838 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 839 } 840 } 841 } 842 843 foreach addr = MIMG_Sampler_AddrSizes<sample>.NSAInstrs in { 844 let VAddrDwords = addr.NumWords in { 845 if op.HAS_BASE then { 846 def _V # addr.NumWords # _nsa_gfx10 847 : MIMG_Sampler_nsa_gfx10<op, asm, dst_rc, addr.NumWords, 848 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 849 } 850 } 851 } 852} 853 854class MIMG_Sampler_BaseOpcode<AMDGPUSampleVariant sample> 855 : MIMGBaseOpcode { 856 let Sampler = 1; 857 let NumExtraArgs = !size(sample.ExtraAddrArgs); 858 let Gradients = sample.Gradients; 859 let LodOrClampOrMip = !ne(sample.LodOrClamp, ""); 860} 861 862multiclass MIMG_Sampler <mimgopc op, AMDGPUSampleVariant sample, bit wqm = 0, 863 bit isG16 = 0, bit isGetLod = 0, 864 string asm = "image_sample"#sample.LowerCaseMod#!if(isG16, "_g16", ""), 865 bit ExtendedImageInst = !ne(sample.LowerCaseMod, "")> { 866 def "" : MIMG_Sampler_BaseOpcode<sample> { 867 let HasD16 = !not(isGetLod); 868 let G16 = isG16; 869 } 870 871 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm, 872 mayLoad = !not(isGetLod) in { 873 let VDataDwords = 1 in 874 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, sample, VGPR_32, 1, ExtendedImageInst>; 875 let VDataDwords = 2 in 876 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64, 0, ExtendedImageInst>; 877 let VDataDwords = 3 in 878 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_96, 0, ExtendedImageInst>; 879 let VDataDwords = 4 in 880 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 0, ExtendedImageInst>; 881 let VDataDwords = 5 in 882 defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160, 0, ExtendedImageInst>; 883 } 884} 885 886multiclass MIMG_Sampler_WQM <mimgopc op, AMDGPUSampleVariant sample> 887 : MIMG_Sampler<op, sample, 1>; 888 889multiclass MIMG_Gather <mimgopc op, AMDGPUSampleVariant sample, bit wqm = 0, 890 string asm = "image_gather4"#sample.LowerCaseMod> { 891 def "" : MIMG_Sampler_BaseOpcode<sample> { 892 let HasD16 = 1; 893 let Gather4 = 1; 894 } 895 896 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm, 897 Gather4 = 1 in { 898 let VDataDwords = 2 in 899 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64>; /* for packed D16 only */ 900 let VDataDwords = 4 in 901 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 1>; 902 let VDataDwords = 5 in 903 defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160>; 904 } 905} 906 907multiclass MIMG_Gather_WQM <mimgopc op, AMDGPUSampleVariant sample> 908 : MIMG_Gather<op, sample, 1>; 909 910class MIMG_IntersectRay_Helper<bit Is64, bit A16> { 911 int num_addrs = !if(Is64, !if(A16, 9, 12), !if(A16, 8, 11)); 912 // TODO: MIMGAddrSize will choose VReg_512 which is a 16 register tuple, 913 // when we only need 9, 11 or 12 depending on A16 field and ptr size. 914 RegisterClass RegClass = MIMGAddrSize<num_addrs, 0>.RegClass; 915 int VAddrDwords = !srl(RegClass.Size, 5); 916} 917 918class MIMG_IntersectRay_gfx10<mimgopc op, string opcode, RegisterClass AddrRC, bit A16> 919 : MIMG_gfx10<op.BASE, (outs VReg_128:$vdata), "AMDGPU"> { 920 921 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_128:$srsrc), 922 !if(A16, (ins GFX10A16:$a16), (ins))); 923 let AsmString = opcode#" $vdata, $vaddr0, $srsrc"#!if(A16, "$a16", ""); 924 925 let nsa = 0; 926} 927 928class MIMG_IntersectRay_nsa_gfx10<mimgopc op, string opcode, int num_addrs, bit A16> 929 : MIMG_nsa_gfx10<op.BASE, (outs VReg_128:$vdata), num_addrs, "AMDGPU"> { 930 let InOperandList = !con(nsah.AddrIns, 931 (ins SReg_128:$srsrc), 932 !if(A16, (ins GFX10A16:$a16), (ins))); 933 let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc"#!if(A16, "$a16", ""); 934} 935 936multiclass MIMG_IntersectRay<mimgopc op, string opcode, bit Is64, bit A16> { 937 defvar info = MIMG_IntersectRay_Helper<Is64, A16>; 938 def "" : MIMGBaseOpcode { 939 let BVH = 1; 940 } 941 let AsmMatchConverter = !if(A16, "cvtIntersectRay", ""), 942 dmask = 0xf, 943 unorm = 1, 944 d16 = 0, 945 cpol = 0, 946 tfe = 0, 947 lwe = 0, 948 r128 = 1, 949 ssamp = 0, 950 dim = {0, 0, 0}, 951 a16 = A16, 952 d16 = 0, 953 BaseOpcode = !cast<MIMGBaseOpcode>(NAME), 954 VDataDwords = 4 in { 955 def _sa_gfx10 : MIMG_IntersectRay_gfx10<op, opcode, info.RegClass, A16> { 956 let VAddrDwords = info.VAddrDwords; 957 } 958 def _nsa_gfx10 : MIMG_IntersectRay_nsa_gfx10<op, opcode, info.num_addrs, A16> { 959 let VAddrDwords = info.num_addrs; 960 } 961 } 962} 963 964//===----------------------------------------------------------------------===// 965// MIMG Instructions 966//===----------------------------------------------------------------------===// 967let OtherPredicates = [HasImageInsts] in { 968 969defm IMAGE_LOAD : MIMG_NoSampler <mimgopc<0x00>, "image_load", 1>; 970defm IMAGE_LOAD_MIP : MIMG_NoSampler <mimgopc<0x01>, "image_load_mip", 1, 1>; 971defm IMAGE_LOAD_PCK : MIMG_NoSampler <mimgopc<0x02>, "image_load_pck", 0>; 972defm IMAGE_LOAD_PCK_SGN : MIMG_NoSampler <mimgopc<0x03>, "image_load_pck_sgn", 0>; 973defm IMAGE_LOAD_MIP_PCK : MIMG_NoSampler <mimgopc<0x04>, "image_load_mip_pck", 0, 1>; 974defm IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoSampler <mimgopc<0x05>, "image_load_mip_pck_sgn", 0, 1>; 975defm IMAGE_STORE : MIMG_Store <mimgopc<0x08>, "image_store", 1>; 976defm IMAGE_STORE_MIP : MIMG_Store <mimgopc<0x09>, "image_store_mip", 1, 1>; 977defm IMAGE_STORE_PCK : MIMG_Store <mimgopc<0x0a>, "image_store_pck", 0>; 978defm IMAGE_STORE_MIP_PCK : MIMG_Store <mimgopc<0x0b>, "image_store_mip_pck", 0, 1>; 979 980defm IMAGE_GET_RESINFO : MIMG_NoSampler <mimgopc<0x0e>, "image_get_resinfo", 0, 1, 1>; 981 982defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimgopc<0x0f, 0x10, 0x0f>, "image_atomic_swap">; 983defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimgopc<0x10, 0x11, 0x10>, "image_atomic_cmpswap", 1>; 984defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimgopc<0x11, 0x12, 0x11>, "image_atomic_add">; 985defm IMAGE_ATOMIC_SUB : MIMG_Atomic <mimgopc<0x12, 0x13, 0x12>, "image_atomic_sub">; 986defm IMAGE_ATOMIC_RSUB : MIMG_Atomic <mimgopc<MIMG.NOP, MIMG.NOP, 0x13>, "image_atomic_rsub">; 987defm IMAGE_ATOMIC_SMIN : MIMG_Atomic <mimgopc<0x14>, "image_atomic_smin">; 988defm IMAGE_ATOMIC_UMIN : MIMG_Atomic <mimgopc<0x15>, "image_atomic_umin">; 989defm IMAGE_ATOMIC_SMAX : MIMG_Atomic <mimgopc<0x16>, "image_atomic_smax">; 990defm IMAGE_ATOMIC_UMAX : MIMG_Atomic <mimgopc<0x17>, "image_atomic_umax">; 991defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimgopc<0x18>, "image_atomic_and">; 992defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimgopc<0x19>, "image_atomic_or">; 993defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimgopc<0x1a>, "image_atomic_xor">; 994defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimgopc<0x1b>, "image_atomic_inc">; 995defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimgopc<0x1c>, "image_atomic_dec">; 996defm IMAGE_ATOMIC_FCMPSWAP : MIMG_Atomic <mimgopc<0x1d, MIMG.NOP>, "image_atomic_fcmpswap", 1, 1>; 997defm IMAGE_ATOMIC_FMIN : MIMG_Atomic <mimgopc<0x1e, MIMG.NOP>, "image_atomic_fmin", 0, 1>; 998defm IMAGE_ATOMIC_FMAX : MIMG_Atomic <mimgopc<0x1f, MIMG.NOP>, "image_atomic_fmax", 0, 1>; 999 1000defm IMAGE_SAMPLE : MIMG_Sampler_WQM <mimgopc<0x20>, AMDGPUSample>; 1001let OtherPredicates = [HasExtendedImageInsts] in { 1002defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <mimgopc<0x21>, AMDGPUSample_cl>; 1003defm IMAGE_SAMPLE_D : MIMG_Sampler <mimgopc<0x22>, AMDGPUSample_d>; 1004defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <mimgopc<0x23>, AMDGPUSample_d_cl>; 1005defm IMAGE_SAMPLE_L : MIMG_Sampler <mimgopc<0x24>, AMDGPUSample_l>; 1006defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <mimgopc<0x25>, AMDGPUSample_b>; 1007defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <mimgopc<0x26>, AMDGPUSample_b_cl>; 1008defm IMAGE_SAMPLE_LZ : MIMG_Sampler <mimgopc<0x27>, AMDGPUSample_lz>; 1009defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <mimgopc<0x28>, AMDGPUSample_c>; 1010defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <mimgopc<0x29>, AMDGPUSample_c_cl>; 1011defm IMAGE_SAMPLE_C_D : MIMG_Sampler <mimgopc<0x2a>, AMDGPUSample_c_d>; 1012defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <mimgopc<0x2b>, AMDGPUSample_c_d_cl>; 1013defm IMAGE_SAMPLE_C_L : MIMG_Sampler <mimgopc<0x2c>, AMDGPUSample_c_l>; 1014defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <mimgopc<0x2d>, AMDGPUSample_c_b>; 1015defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <mimgopc<0x2e>, AMDGPUSample_c_b_cl>; 1016defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <mimgopc<0x2f>, AMDGPUSample_c_lz>; 1017defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <mimgopc<0x30>, AMDGPUSample_o>; 1018defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <mimgopc<0x31>, AMDGPUSample_cl_o>; 1019defm IMAGE_SAMPLE_D_O : MIMG_Sampler <mimgopc<0x32>, AMDGPUSample_d_o>; 1020defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <mimgopc<0x33>, AMDGPUSample_d_cl_o>; 1021defm IMAGE_SAMPLE_L_O : MIMG_Sampler <mimgopc<0x34>, AMDGPUSample_l_o>; 1022defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <mimgopc<0x35>, AMDGPUSample_b_o>; 1023defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <mimgopc<0x36>, AMDGPUSample_b_cl_o>; 1024defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <mimgopc<0x37>, AMDGPUSample_lz_o>; 1025defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <mimgopc<0x38>, AMDGPUSample_c_o>; 1026defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <mimgopc<0x39>, AMDGPUSample_c_cl_o>; 1027defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <mimgopc<0x3a>, AMDGPUSample_c_d_o>; 1028defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <mimgopc<0x3b>, AMDGPUSample_c_d_cl_o>; 1029defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <mimgopc<0x3c>, AMDGPUSample_c_l_o>; 1030defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <mimgopc<0x3e>, AMDGPUSample_c_b_cl_o>; 1031defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <mimgopc<0x3d>, AMDGPUSample_c_b_o>; 1032defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <mimgopc<0x3f>, AMDGPUSample_c_lz_o>; 1033defm IMAGE_GATHER4 : MIMG_Gather_WQM <mimgopc<0x40>, AMDGPUSample>; 1034defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <mimgopc<0x41>, AMDGPUSample_cl>; 1035defm IMAGE_GATHER4_L : MIMG_Gather <mimgopc<0x44>, AMDGPUSample_l>; 1036defm IMAGE_GATHER4_B : MIMG_Gather_WQM <mimgopc<0x45>, AMDGPUSample_b>; 1037defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <mimgopc<0x46>, AMDGPUSample_b_cl>; 1038defm IMAGE_GATHER4_LZ : MIMG_Gather <mimgopc<0x47>, AMDGPUSample_lz>; 1039defm IMAGE_GATHER4_C : MIMG_Gather_WQM <mimgopc<0x48>, AMDGPUSample_c>; 1040defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <mimgopc<0x49>, AMDGPUSample_c_cl>; 1041defm IMAGE_GATHER4_C_L : MIMG_Gather <mimgopc<0x4c>, AMDGPUSample_c_l>; 1042defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <mimgopc<0x4d>, AMDGPUSample_c_b>; 1043defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <mimgopc<0x4e>, AMDGPUSample_c_b_cl>; 1044defm IMAGE_GATHER4_C_LZ : MIMG_Gather <mimgopc<0x4f>, AMDGPUSample_c_lz>; 1045defm IMAGE_GATHER4_O : MIMG_Gather_WQM <mimgopc<0x50>, AMDGPUSample_o>; 1046defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <mimgopc<0x51>, AMDGPUSample_cl_o>; 1047defm IMAGE_GATHER4_L_O : MIMG_Gather <mimgopc<0x54>, AMDGPUSample_l_o>; 1048defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <mimgopc<0x55>, AMDGPUSample_b_o>; 1049defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <mimgopc<0x56>, AMDGPUSample_b_cl_o>; 1050defm IMAGE_GATHER4_LZ_O : MIMG_Gather <mimgopc<0x57>, AMDGPUSample_lz_o>; 1051defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <mimgopc<0x58>, AMDGPUSample_c_o>; 1052defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <mimgopc<0x59>, AMDGPUSample_c_cl_o>; 1053defm IMAGE_GATHER4_C_L_O : MIMG_Gather <mimgopc<0x5c>, AMDGPUSample_c_l_o>; 1054defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <mimgopc<0x5d>, AMDGPUSample_c_b_o>; 1055defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <mimgopc<0x5e>, AMDGPUSample_c_b_cl_o>; 1056defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <mimgopc<0x5f>, AMDGPUSample_c_lz_o>; 1057//defm IMAGE_GATHER4H : MIMG_Gather_WQM <mimgopc<0x61>, ?>; 1058 1059defm IMAGE_GET_LOD : MIMG_Sampler <mimgopc<0x60>, AMDGPUSample, 1, 0, 1, "image_get_lod">; 1060 1061defm IMAGE_SAMPLE_CD : MIMG_Sampler <mimgopc<0x68>, AMDGPUSample_cd>; 1062defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <mimgopc<0x69>, AMDGPUSample_cd_cl>; 1063defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <mimgopc<0x6a>, AMDGPUSample_c_cd>; 1064defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <mimgopc<0x6b>, AMDGPUSample_c_cd_cl>; 1065defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <mimgopc<0x6c>, AMDGPUSample_cd_o>; 1066defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <mimgopc<0x6d>, AMDGPUSample_cd_cl_o>; 1067defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <mimgopc<0x6e>, AMDGPUSample_c_cd_o>; 1068defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <mimgopc<0x6f>, AMDGPUSample_c_cd_cl_o>; 1069} // End OtherPredicates = [HasExtendedImageInsts] 1070 1071let OtherPredicates = [HasExtendedImageInsts,HasG16] in { 1072defm IMAGE_SAMPLE_D_G16 : MIMG_Sampler <mimgopc<0xa2>, AMDGPUSample_d, 0, 1>; 1073defm IMAGE_SAMPLE_D_CL_G16 : MIMG_Sampler <mimgopc<0xa3>, AMDGPUSample_d_cl, 0, 1>; 1074defm IMAGE_SAMPLE_C_D_G16 : MIMG_Sampler <mimgopc<0xaa>, AMDGPUSample_c_d, 0, 1>; 1075defm IMAGE_SAMPLE_C_D_CL_G16 : MIMG_Sampler <mimgopc<0xab>, AMDGPUSample_c_d_cl, 0, 1>; 1076defm IMAGE_SAMPLE_D_O_G16 : MIMG_Sampler <mimgopc<0xb2>, AMDGPUSample_d_o, 0, 1>; 1077defm IMAGE_SAMPLE_D_CL_O_G16 : MIMG_Sampler <mimgopc<0xb3>, AMDGPUSample_d_cl_o, 0, 1>; 1078defm IMAGE_SAMPLE_C_D_O_G16 : MIMG_Sampler <mimgopc<0xba>, AMDGPUSample_c_d_o, 0, 1>; 1079defm IMAGE_SAMPLE_C_D_CL_O_G16 : MIMG_Sampler <mimgopc<0xbb>, AMDGPUSample_c_d_cl_o, 0, 1>; 1080defm IMAGE_SAMPLE_CD_G16 : MIMG_Sampler <mimgopc<0xe8>, AMDGPUSample_cd, 0, 1>; 1081defm IMAGE_SAMPLE_CD_CL_G16 : MIMG_Sampler <mimgopc<0xe9>, AMDGPUSample_cd_cl, 0, 1>; 1082defm IMAGE_SAMPLE_C_CD_G16 : MIMG_Sampler <mimgopc<0xea>, AMDGPUSample_c_cd, 0, 1>; 1083defm IMAGE_SAMPLE_C_CD_CL_G16 : MIMG_Sampler <mimgopc<0xeb>, AMDGPUSample_c_cd_cl, 0, 1>; 1084defm IMAGE_SAMPLE_CD_O_G16 : MIMG_Sampler <mimgopc<0xec>, AMDGPUSample_cd_o, 0, 1>; 1085defm IMAGE_SAMPLE_CD_CL_O_G16 : MIMG_Sampler <mimgopc<0xed>, AMDGPUSample_cd_cl_o, 0, 1>; 1086defm IMAGE_SAMPLE_C_CD_O_G16 : MIMG_Sampler <mimgopc<0xee>, AMDGPUSample_c_cd_o, 0, 1>; 1087defm IMAGE_SAMPLE_C_CD_CL_O_G16 : MIMG_Sampler <mimgopc<0xef>, AMDGPUSample_c_cd_cl_o, 0, 1>; 1088} // End OtherPredicates = [HasExtendedImageInsts,HasG16] 1089 1090//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>; 1091//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>; 1092 1093let OtherPredicates = [HasGFX10_AEncoding] in 1094defm IMAGE_MSAA_LOAD_X : MIMG_NoSampler <mimgopc<0x80>, "image_msaa_load", 1, 0, 0, 1>; 1095 1096let OtherPredicates = [HasGFX10_AEncoding] in { 1097defm IMAGE_BVH_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<0xe6>, "image_bvh_intersect_ray", 0, 0>; 1098defm IMAGE_BVH_INTERSECT_RAY_a16 : MIMG_IntersectRay<mimgopc<0xe6>, "image_bvh_intersect_ray", 0, 1>; 1099defm IMAGE_BVH64_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<0xe7>, "image_bvh64_intersect_ray", 1, 0>; 1100defm IMAGE_BVH64_INTERSECT_RAY_a16 : MIMG_IntersectRay<mimgopc<0xe7>, "image_bvh64_intersect_ray", 1, 1>; 1101} // End OtherPredicates = [HasGFX10_AEncoding] 1102 1103} // End let OtherPredicates = [HasImageInsts] 1104 1105/********** ========================================= **********/ 1106/********** Table of dimension-aware image intrinsics **********/ 1107/********** ========================================= **********/ 1108 1109class ImageDimIntrinsicInfo<AMDGPUImageDimIntrinsic I> { 1110 Intrinsic Intr = I; 1111 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(!strconcat("IMAGE_", I.P.OpMod)); 1112 AMDGPUDimProps Dim = I.P.Dim; 1113 AMDGPUImageDimIntrinsicEval DimEval = AMDGPUImageDimIntrinsicEval<I.P>; 1114 1115 bits<8> NumOffsetArgs = DimEval.NumOffsetArgs; 1116 bits<8> NumBiasArgs = DimEval.NumBiasArgs; 1117 bits<8> NumZCompareArgs = DimEval.NumZCompareArgs; 1118 bits<8> NumGradients = DimEval.NumGradientArgs; 1119 bits<8> NumDmask = DimEval.NumDmaskArgs; 1120 bits<8> NumData = DimEval.NumDataArgs; 1121 bits<8> NumVAddrs = DimEval.NumVAddrArgs; 1122 bits<8> NumArgs = !add(DimEval.CachePolicyArgIndex, 1); 1123 1124 bits<8> DMaskIndex = DimEval.DmaskArgIndex; 1125 bits<8> VAddrStart = DimEval.VAddrArgIndex; 1126 bits<8> OffsetIndex = DimEval.OffsetArgIndex; 1127 bits<8> BiasIndex = DimEval.BiasArgIndex; 1128 bits<8> ZCompareIndex = DimEval.ZCompareArgIndex; 1129 bits<8> GradientStart = DimEval.GradientArgIndex; 1130 bits<8> CoordStart = DimEval.CoordArgIndex; 1131 bits<8> LodIndex = DimEval.LodArgIndex; 1132 bits<8> MipIndex = DimEval.MipArgIndex; 1133 bits<8> VAddrEnd = !add(DimEval.VAddrArgIndex, DimEval.NumVAddrArgs); 1134 bits<8> RsrcIndex = DimEval.RsrcArgIndex; 1135 bits<8> SampIndex = DimEval.SampArgIndex; 1136 bits<8> UnormIndex = DimEval.UnormArgIndex; 1137 bits<8> TexFailCtrlIndex = DimEval.TexFailCtrlArgIndex; 1138 bits<8> CachePolicyIndex = DimEval.CachePolicyArgIndex; 1139 1140 bits<8> BiasTyArg = !add(I.P.NumRetAndDataAnyTypes, 1141 !if(!eq(NumOffsetArgs, 0), 0, I.P.ExtraAddrArgs[0].Type.isAny)); 1142 bits<8> GradientTyArg = !add(I.P.NumRetAndDataAnyTypes, 1143 !foldl(0, I.P.ExtraAddrArgs, cnt, arg, !add(cnt, arg.Type.isAny))); 1144 bits<8> CoordTyArg = !add(GradientTyArg, !if(I.P.Gradients, 1, 0)); 1145} 1146 1147def ImageDimIntrinsicTable : GenericTable { 1148 let FilterClass = "ImageDimIntrinsicInfo"; 1149 let Fields = ["Intr", "BaseOpcode", "Dim", "NumOffsetArgs", "NumBiasArgs", "NumZCompareArgs", "NumGradients", "NumDmask", "NumData", "NumVAddrs", "NumArgs", 1150 "DMaskIndex", "VAddrStart", "OffsetIndex", "BiasIndex", "ZCompareIndex", "GradientStart", "CoordStart", "LodIndex", "MipIndex", "VAddrEnd", 1151 "RsrcIndex", "SampIndex", "UnormIndex", "TexFailCtrlIndex", "CachePolicyIndex", 1152 "BiasTyArg", "GradientTyArg", "CoordTyArg"]; 1153 string TypeOf_BaseOpcode = "MIMGBaseOpcode"; 1154 string TypeOf_Dim = "MIMGDim"; 1155 1156 let PrimaryKey = ["Intr"]; 1157 let PrimaryKeyName = "getImageDimIntrinsicInfo"; 1158 let PrimaryKeyEarlyOut = 1; 1159} 1160 1161def getImageDimIntrinsicByBaseOpcode : SearchIndex { 1162 let Table = ImageDimIntrinsicTable; 1163 let Key = ["BaseOpcode", "Dim"]; 1164} 1165 1166foreach intr = !listconcat(AMDGPUImageDimIntrinsics, 1167 AMDGPUImageDimAtomicIntrinsics) in { 1168 def : ImageDimIntrinsicInfo<intr>; 1169} 1170 1171// L to LZ Optimization Mapping 1172def : MIMGLZMapping<IMAGE_SAMPLE_L, IMAGE_SAMPLE_LZ>; 1173def : MIMGLZMapping<IMAGE_SAMPLE_C_L, IMAGE_SAMPLE_C_LZ>; 1174def : MIMGLZMapping<IMAGE_SAMPLE_L_O, IMAGE_SAMPLE_LZ_O>; 1175def : MIMGLZMapping<IMAGE_SAMPLE_C_L_O, IMAGE_SAMPLE_C_LZ_O>; 1176def : MIMGLZMapping<IMAGE_GATHER4_L, IMAGE_GATHER4_LZ>; 1177def : MIMGLZMapping<IMAGE_GATHER4_C_L, IMAGE_GATHER4_C_LZ>; 1178def : MIMGLZMapping<IMAGE_GATHER4_L_O, IMAGE_GATHER4_LZ_O>; 1179def : MIMGLZMapping<IMAGE_GATHER4_C_L_O, IMAGE_GATHER4_C_LZ_O>; 1180 1181// MIP to NONMIP Optimization Mapping 1182def : MIMGMIPMapping<IMAGE_LOAD_MIP, IMAGE_LOAD>; 1183def : MIMGMIPMapping<IMAGE_STORE_MIP, IMAGE_STORE>; 1184 1185// Bias to NoBias Optimization Mapping 1186def : MIMGBiasMapping<IMAGE_SAMPLE_B, IMAGE_SAMPLE>; 1187def : MIMGBiasMapping<IMAGE_SAMPLE_B_CL, IMAGE_SAMPLE_CL>; 1188def : MIMGBiasMapping<IMAGE_SAMPLE_C_B, IMAGE_SAMPLE_C>; 1189def : MIMGBiasMapping<IMAGE_SAMPLE_C_B_CL, IMAGE_SAMPLE_C_CL>; 1190def : MIMGBiasMapping<IMAGE_SAMPLE_B_O, IMAGE_SAMPLE_O>; 1191def : MIMGBiasMapping<IMAGE_SAMPLE_B_CL_O, IMAGE_SAMPLE_CL_O>; 1192def : MIMGBiasMapping<IMAGE_SAMPLE_C_B_O, IMAGE_SAMPLE_C_O>; 1193def : MIMGBiasMapping<IMAGE_SAMPLE_C_B_CL_O, IMAGE_SAMPLE_C_CL_O>; 1194def : MIMGBiasMapping<IMAGE_GATHER4_B, IMAGE_GATHER4>; 1195def : MIMGBiasMapping<IMAGE_GATHER4_B_CL, IMAGE_GATHER4_CL>; 1196def : MIMGBiasMapping<IMAGE_GATHER4_C_B, IMAGE_GATHER4_C>; 1197def : MIMGBiasMapping<IMAGE_GATHER4_C_B_CL, IMAGE_GATHER4_C_CL>; 1198def : MIMGBiasMapping<IMAGE_GATHER4_B_O, IMAGE_GATHER4_O>; 1199def : MIMGBiasMapping<IMAGE_GATHER4_B_CL_O, IMAGE_GATHER4_CL_O>; 1200def : MIMGBiasMapping<IMAGE_GATHER4_C_B_O, IMAGE_GATHER4_C_O>; 1201def : MIMGBiasMapping<IMAGE_GATHER4_C_B_CL_O, IMAGE_GATHER4_C_CL_O>; 1202 1203// Offset to NoOffset Optimization Mapping 1204def : MIMGOffsetMapping<IMAGE_SAMPLE_O, IMAGE_SAMPLE>; 1205def : MIMGOffsetMapping<IMAGE_SAMPLE_CL_O, IMAGE_SAMPLE_CL>; 1206def : MIMGOffsetMapping<IMAGE_SAMPLE_D_O, IMAGE_SAMPLE_D>; 1207def : MIMGOffsetMapping<IMAGE_SAMPLE_D_CL_O, IMAGE_SAMPLE_D_CL>; 1208def : MIMGOffsetMapping<IMAGE_SAMPLE_D_O_G16, IMAGE_SAMPLE_D_G16>; 1209def : MIMGOffsetMapping<IMAGE_SAMPLE_D_CL_O_G16, IMAGE_SAMPLE_D_CL_G16>; 1210def : MIMGOffsetMapping<IMAGE_SAMPLE_L_O, IMAGE_SAMPLE_L>; 1211def : MIMGOffsetMapping<IMAGE_SAMPLE_B_O, IMAGE_SAMPLE_B>; 1212def : MIMGOffsetMapping<IMAGE_SAMPLE_B_CL_O, IMAGE_SAMPLE_B_CL>; 1213def : MIMGOffsetMapping<IMAGE_SAMPLE_LZ_O, IMAGE_SAMPLE_LZ>; 1214def : MIMGOffsetMapping<IMAGE_SAMPLE_C_O, IMAGE_SAMPLE_C>; 1215def : MIMGOffsetMapping<IMAGE_SAMPLE_C_CL_O, IMAGE_SAMPLE_C_CL>; 1216def : MIMGOffsetMapping<IMAGE_SAMPLE_C_D_O, IMAGE_SAMPLE_C_D>; 1217def : MIMGOffsetMapping<IMAGE_SAMPLE_C_D_CL_O, IMAGE_SAMPLE_C_D_CL>; 1218def : MIMGOffsetMapping<IMAGE_SAMPLE_C_D_O_G16, IMAGE_SAMPLE_C_D_G16>; 1219def : MIMGOffsetMapping<IMAGE_SAMPLE_C_D_CL_O_G16, IMAGE_SAMPLE_C_D_CL_G16>; 1220def : MIMGOffsetMapping<IMAGE_SAMPLE_C_L_O, IMAGE_SAMPLE_C_L>; 1221def : MIMGOffsetMapping<IMAGE_SAMPLE_C_B_CL_O, IMAGE_SAMPLE_C_B_CL>; 1222def : MIMGOffsetMapping<IMAGE_SAMPLE_C_B_O, IMAGE_SAMPLE_C_B>; 1223def : MIMGOffsetMapping<IMAGE_SAMPLE_C_LZ_O, IMAGE_SAMPLE_C_LZ>; 1224def : MIMGOffsetMapping<IMAGE_GATHER4_O, IMAGE_GATHER4>; 1225def : MIMGOffsetMapping<IMAGE_GATHER4_CL_O, IMAGE_GATHER4_CL>; 1226def : MIMGOffsetMapping<IMAGE_GATHER4_L_O, IMAGE_GATHER4_L>; 1227def : MIMGOffsetMapping<IMAGE_GATHER4_B_O, IMAGE_GATHER4_B>; 1228def : MIMGOffsetMapping<IMAGE_GATHER4_B_CL_O, IMAGE_GATHER4_B_CL>; 1229def : MIMGOffsetMapping<IMAGE_GATHER4_LZ_O, IMAGE_GATHER4_LZ>; 1230def : MIMGOffsetMapping<IMAGE_GATHER4_C_O, IMAGE_GATHER4_C>; 1231def : MIMGOffsetMapping<IMAGE_GATHER4_C_CL_O, IMAGE_GATHER4_C_CL>; 1232def : MIMGOffsetMapping<IMAGE_GATHER4_C_L_O, IMAGE_GATHER4_C_L>; 1233def : MIMGOffsetMapping<IMAGE_GATHER4_C_B_O, IMAGE_GATHER4_C_B>; 1234def : MIMGOffsetMapping<IMAGE_GATHER4_C_B_CL_O, IMAGE_GATHER4_C_B_CL>; 1235def : MIMGOffsetMapping<IMAGE_GATHER4_C_LZ_O, IMAGE_GATHER4_C_LZ>; 1236def : MIMGOffsetMapping<IMAGE_SAMPLE_CD_O, IMAGE_SAMPLE_CD>; 1237def : MIMGOffsetMapping<IMAGE_SAMPLE_CD_CL_O, IMAGE_SAMPLE_CD_CL>; 1238def : MIMGOffsetMapping<IMAGE_SAMPLE_C_CD_O, IMAGE_SAMPLE_C_CD>; 1239def : MIMGOffsetMapping<IMAGE_SAMPLE_C_CD_CL_O, IMAGE_SAMPLE_C_CD_CL>; 1240def : MIMGOffsetMapping<IMAGE_SAMPLE_CD_O_G16, IMAGE_SAMPLE_CD_G16>; 1241def : MIMGOffsetMapping<IMAGE_SAMPLE_CD_CL_O_G16, IMAGE_SAMPLE_CD_CL_G16>; 1242def : MIMGOffsetMapping<IMAGE_SAMPLE_C_CD_O_G16, IMAGE_SAMPLE_C_CD_G16>; 1243def : MIMGOffsetMapping<IMAGE_SAMPLE_C_CD_CL_O_G16, IMAGE_SAMPLE_C_CD_CL_G16>; 1244 1245// G to G16 Optimization Mapping 1246def : MIMGG16Mapping<IMAGE_SAMPLE_D, IMAGE_SAMPLE_D_G16>; 1247def : MIMGG16Mapping<IMAGE_SAMPLE_D_CL, IMAGE_SAMPLE_D_CL_G16>; 1248def : MIMGG16Mapping<IMAGE_SAMPLE_C_D, IMAGE_SAMPLE_C_D_G16>; 1249def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_CL, IMAGE_SAMPLE_C_D_CL_G16>; 1250def : MIMGG16Mapping<IMAGE_SAMPLE_D_O, IMAGE_SAMPLE_D_O_G16>; 1251def : MIMGG16Mapping<IMAGE_SAMPLE_D_CL_O, IMAGE_SAMPLE_D_CL_O_G16>; 1252def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_O, IMAGE_SAMPLE_C_D_O_G16>; 1253def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_CL_O, IMAGE_SAMPLE_C_D_CL_O_G16>; 1254def : MIMGG16Mapping<IMAGE_SAMPLE_CD, IMAGE_SAMPLE_CD_G16>; 1255def : MIMGG16Mapping<IMAGE_SAMPLE_CD_CL, IMAGE_SAMPLE_CD_CL_G16>; 1256def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD, IMAGE_SAMPLE_C_CD_G16>; 1257def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_CL, IMAGE_SAMPLE_C_CD_CL_G16>; 1258def : MIMGG16Mapping<IMAGE_SAMPLE_CD_O, IMAGE_SAMPLE_CD_O_G16>; 1259def : MIMGG16Mapping<IMAGE_SAMPLE_CD_CL_O, IMAGE_SAMPLE_CD_CL_O_G16>; 1260def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_O, IMAGE_SAMPLE_C_CD_O_G16>; 1261def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_CL_O, IMAGE_SAMPLE_C_CD_CL_O_G16>; 1262