1//===-- MIMGInstructions.td - MIMG Instruction Defintions -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10class MIMG_Mask <string op, int channels> { 11 string Op = op; 12 int Channels = channels; 13} 14 15class mimg <bits<7> si, bits<7> vi = si> { 16 field bits<7> SI = si; 17 field bits<7> VI = vi; 18} 19 20class MIMG_Helper <dag outs, dag ins, string asm, 21 string dns=""> : MIMG<outs, ins, asm,[]> { 22 let mayLoad = 1; 23 let mayStore = 0; 24 let hasPostISelHook = 1; 25 let DecoderNamespace = dns; 26 let isAsmParserOnly = !if(!eq(dns,""), 1, 0); 27 let AsmMatchConverter = "cvtMIMG"; 28} 29 30class MIMG_NoSampler_Helper <bits<7> op, string asm, 31 RegisterClass dst_rc, 32 RegisterClass addr_rc, 33 string dns=""> : MIMG_Helper < 34 (outs dst_rc:$vdata), 35 (ins addr_rc:$vaddr, SReg_256:$srsrc, 36 dmask:$dmask, unorm:$unorm, glc:$glc, slc:$slc, 37 r128:$r128, tfe:$tfe, lwe:$lwe, da:$da), 38 asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da", 39 dns>, MIMGe<op> { 40 let ssamp = 0; 41} 42 43multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm, 44 RegisterClass dst_rc, 45 int channels> { 46 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32, 47 !if(!eq(channels, 1), "AMDGPU", "")>, 48 MIMG_Mask<asm#"_V1", channels>; 49 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>, 50 MIMG_Mask<asm#"_V2", channels>; 51 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>, 52 MIMG_Mask<asm#"_V4", channels>; 53} 54 55multiclass MIMG_NoSampler <bits<7> op, string asm> { 56 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>; 57 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>; 58 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>; 59 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>; 60} 61 62class MIMG_Store_Helper <bits<7> op, string asm, 63 RegisterClass data_rc, 64 RegisterClass addr_rc> : MIMG_Helper < 65 (outs), 66 (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, 67 dmask:$dmask, unorm:$unorm, glc:$glc, slc:$slc, 68 r128:$r128, tfe:$tfe, lwe:$lwe, da:$da), 69 asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" 70 >, MIMGe<op> { 71 let ssamp = 0; 72 let mayLoad = 1; // TableGen requires this for matching with the intrinsics 73 let mayStore = 1; 74 let hasSideEffects = 1; 75 let hasPostISelHook = 0; 76 let DisableWQM = 1; 77} 78 79multiclass MIMG_Store_Addr_Helper <bits<7> op, string asm, 80 RegisterClass data_rc, 81 int channels> { 82 def _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32>, 83 MIMG_Mask<asm#"_V1", channels>; 84 def _V2 : MIMG_Store_Helper <op, asm, data_rc, VReg_64>, 85 MIMG_Mask<asm#"_V2", channels>; 86 def _V4 : MIMG_Store_Helper <op, asm, data_rc, VReg_128>, 87 MIMG_Mask<asm#"_V4", channels>; 88} 89 90multiclass MIMG_Store <bits<7> op, string asm> { 91 defm _V1 : MIMG_Store_Addr_Helper <op, asm, VGPR_32, 1>; 92 defm _V2 : MIMG_Store_Addr_Helper <op, asm, VReg_64, 2>; 93 defm _V3 : MIMG_Store_Addr_Helper <op, asm, VReg_96, 3>; 94 defm _V4 : MIMG_Store_Addr_Helper <op, asm, VReg_128, 4>; 95} 96 97class MIMG_Atomic_Helper <string asm, RegisterClass data_rc, 98 RegisterClass addr_rc> : MIMG_Helper < 99 (outs data_rc:$vdst), 100 (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, 101 dmask:$dmask, unorm:$unorm, glc:$glc, slc:$slc, 102 r128:$r128, tfe:$tfe, lwe:$lwe, da:$da), 103 asm#" $vdst, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" 104 > { 105 let mayStore = 1; 106 let hasSideEffects = 1; 107 let hasPostISelHook = 0; 108 let DisableWQM = 1; 109 let Constraints = "$vdst = $vdata"; 110 let AsmMatchConverter = "cvtMIMGAtomic"; 111} 112 113class MIMG_Atomic_Real_si<mimg op, string name, string asm, 114 RegisterClass data_rc, RegisterClass addr_rc> : 115 MIMG_Atomic_Helper<asm, data_rc, addr_rc>, 116 SIMCInstr<name, SIEncodingFamily.SI>, 117 MIMGe<op.SI> { 118 let isCodeGenOnly = 0; 119 let AssemblerPredicates = [isSICI]; 120 let DecoderNamespace = "SICI"; 121 let DisableDecoder = DisableSIDecoder; 122} 123 124class MIMG_Atomic_Real_vi<mimg op, string name, string asm, 125 RegisterClass data_rc, RegisterClass addr_rc> : 126 MIMG_Atomic_Helper<asm, data_rc, addr_rc>, 127 SIMCInstr<name, SIEncodingFamily.VI>, 128 MIMGe<op.VI> { 129 let isCodeGenOnly = 0; 130 let AssemblerPredicates = [isVI]; 131 let DecoderNamespace = "VI"; 132 let DisableDecoder = DisableVIDecoder; 133} 134 135multiclass MIMG_Atomic_Helper_m <mimg op, string name, string asm, 136 RegisterClass data_rc, RegisterClass addr_rc> { 137 let isPseudo = 1, isCodeGenOnly = 1 in { 138 def "" : MIMG_Atomic_Helper<asm, data_rc, addr_rc>, 139 SIMCInstr<name, SIEncodingFamily.NONE>; 140 } 141 142 let ssamp = 0 in { 143 def _si : MIMG_Atomic_Real_si<op, name, asm, data_rc, addr_rc>; 144 145 def _vi : MIMG_Atomic_Real_vi<op, name, asm, data_rc, addr_rc>; 146 } 147} 148 149multiclass MIMG_Atomic <mimg op, string asm, RegisterClass data_rc = VGPR_32> { 150 defm _V1 : MIMG_Atomic_Helper_m <op, asm # "_V1", asm, data_rc, VGPR_32>; 151 defm _V2 : MIMG_Atomic_Helper_m <op, asm # "_V2", asm, data_rc, VReg_64>; 152 defm _V4 : MIMG_Atomic_Helper_m <op, asm # "_V3", asm, data_rc, VReg_128>; 153} 154 155class MIMG_Sampler_Helper <bits<7> op, string asm, 156 RegisterClass dst_rc, 157 RegisterClass src_rc, 158 int wqm, 159 string dns=""> : MIMG_Helper < 160 (outs dst_rc:$vdata), 161 (ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp, 162 dmask:$dmask, unorm:$unorm, glc:$glc, slc:$slc, 163 r128:$r128, tfe:$tfe, lwe:$lwe, da:$da), 164 asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da", 165 dns>, MIMGe<op> { 166 let WQM = wqm; 167} 168 169multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm, 170 RegisterClass dst_rc, 171 int channels, int wqm> { 172 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm, 173 !if(!eq(channels, 1), "AMDGPU", "")>, 174 MIMG_Mask<asm#"_V1", channels>; 175 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>, 176 MIMG_Mask<asm#"_V2", channels>; 177 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>, 178 MIMG_Mask<asm#"_V4", channels>; 179 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>, 180 MIMG_Mask<asm#"_V8", channels>; 181 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>, 182 MIMG_Mask<asm#"_V16", channels>; 183} 184 185multiclass MIMG_Sampler <bits<7> op, string asm, int wqm=0> { 186 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, wqm>; 187 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, wqm>; 188 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, wqm>; 189 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, wqm>; 190} 191 192multiclass MIMG_Sampler_WQM <bits<7> op, string asm> : MIMG_Sampler<op, asm, 1>; 193 194class MIMG_Gather_Helper <bits<7> op, string asm, 195 RegisterClass dst_rc, 196 RegisterClass src_rc, int wqm> : MIMG < 197 (outs dst_rc:$vdata), 198 (ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp, 199 dmask:$dmask, unorm:$unorm, glc:$glc, slc:$slc, 200 r128:$r128, tfe:$tfe, lwe:$lwe, da:$da), 201 asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da", 202 []>, MIMGe<op> { 203 let mayLoad = 1; 204 let mayStore = 0; 205 206 // DMASK was repurposed for GATHER4. 4 components are always 207 // returned and DMASK works like a swizzle - it selects 208 // the component to fetch. The only useful DMASK values are 209 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns 210 // (red,red,red,red) etc.) The ISA document doesn't mention 211 // this. 212 // Therefore, disable all code which updates DMASK by setting this: 213 let Gather4 = 1; 214 let hasPostISelHook = 0; 215 let WQM = wqm; 216 217 let isAsmParserOnly = 1; // TBD: fix it later 218} 219 220multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm, 221 RegisterClass dst_rc, 222 int channels, int wqm> { 223 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>, 224 MIMG_Mask<asm#"_V1", channels>; 225 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>, 226 MIMG_Mask<asm#"_V2", channels>; 227 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>, 228 MIMG_Mask<asm#"_V4", channels>; 229 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>, 230 MIMG_Mask<asm#"_V8", channels>; 231 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>, 232 MIMG_Mask<asm#"_V16", channels>; 233} 234 235multiclass MIMG_Gather <bits<7> op, string asm, int wqm=0> { 236 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, wqm>; 237 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, wqm>; 238 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, wqm>; 239 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, wqm>; 240} 241 242multiclass MIMG_Gather_WQM <bits<7> op, string asm> : MIMG_Gather<op, asm, 1>; 243 244//===----------------------------------------------------------------------===// 245// MIMG Instructions 246//===----------------------------------------------------------------------===// 247let SubtargetPredicate = isGCN in { 248defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load">; 249defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip">; 250//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"image_load_pck", 0x00000002>; 251//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"image_load_pck_sgn", 0x00000003>; 252//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"image_load_mip_pck", 0x00000004>; 253//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"image_load_mip_pck_sgn", 0x00000005>; 254defm IMAGE_STORE : MIMG_Store <0x00000008, "image_store">; 255defm IMAGE_STORE_MIP : MIMG_Store <0x00000009, "image_store_mip">; 256//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"image_store_pck", 0x0000000a>; 257//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"image_store_mip_pck", 0x0000000b>; 258defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo">; 259defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimg<0x0f, 0x10>, "image_atomic_swap">; 260defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimg<0x10, 0x11>, "image_atomic_cmpswap", VReg_64>; 261defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimg<0x11, 0x12>, "image_atomic_add">; 262defm IMAGE_ATOMIC_SUB : MIMG_Atomic <mimg<0x12, 0x13>, "image_atomic_sub">; 263//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>; -- not on VI 264defm IMAGE_ATOMIC_SMIN : MIMG_Atomic <mimg<0x14>, "image_atomic_smin">; 265defm IMAGE_ATOMIC_UMIN : MIMG_Atomic <mimg<0x15>, "image_atomic_umin">; 266defm IMAGE_ATOMIC_SMAX : MIMG_Atomic <mimg<0x16>, "image_atomic_smax">; 267defm IMAGE_ATOMIC_UMAX : MIMG_Atomic <mimg<0x17>, "image_atomic_umax">; 268defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimg<0x18>, "image_atomic_and">; 269defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimg<0x19>, "image_atomic_or">; 270defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimg<0x1a>, "image_atomic_xor">; 271defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimg<0x1b>, "image_atomic_inc">; 272defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimg<0x1c>, "image_atomic_dec">; 273//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d>; -- not on VI 274//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>; -- not on VI 275//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>; -- not on VI 276defm IMAGE_SAMPLE : MIMG_Sampler_WQM <0x00000020, "image_sample">; 277defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <0x00000021, "image_sample_cl">; 278defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "image_sample_d">; 279defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "image_sample_d_cl">; 280defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "image_sample_l">; 281defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <0x00000025, "image_sample_b">; 282defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <0x00000026, "image_sample_b_cl">; 283defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "image_sample_lz">; 284defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <0x00000028, "image_sample_c">; 285defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <0x00000029, "image_sample_c_cl">; 286defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "image_sample_c_d">; 287defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "image_sample_c_d_cl">; 288defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "image_sample_c_l">; 289defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <0x0000002d, "image_sample_c_b">; 290defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <0x0000002e, "image_sample_c_b_cl">; 291defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "image_sample_c_lz">; 292defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <0x00000030, "image_sample_o">; 293defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <0x00000031, "image_sample_cl_o">; 294defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "image_sample_d_o">; 295defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "image_sample_d_cl_o">; 296defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "image_sample_l_o">; 297defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <0x00000035, "image_sample_b_o">; 298defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <0x00000036, "image_sample_b_cl_o">; 299defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "image_sample_lz_o">; 300defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <0x00000038, "image_sample_c_o">; 301defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <0x00000039, "image_sample_c_cl_o">; 302defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "image_sample_c_d_o">; 303defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "image_sample_c_d_cl_o">; 304defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "image_sample_c_l_o">; 305defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <0x0000003d, "image_sample_c_b_o">; 306defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <0x0000003e, "image_sample_c_b_cl_o">; 307defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "image_sample_c_lz_o">; 308defm IMAGE_GATHER4 : MIMG_Gather_WQM <0x00000040, "image_gather4">; 309defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <0x00000041, "image_gather4_cl">; 310defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "image_gather4_l">; 311defm IMAGE_GATHER4_B : MIMG_Gather_WQM <0x00000045, "image_gather4_b">; 312defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <0x00000046, "image_gather4_b_cl">; 313defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "image_gather4_lz">; 314defm IMAGE_GATHER4_C : MIMG_Gather_WQM <0x00000048, "image_gather4_c">; 315defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <0x00000049, "image_gather4_c_cl">; 316defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "image_gather4_c_l">; 317defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <0x0000004d, "image_gather4_c_b">; 318defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <0x0000004e, "image_gather4_c_b_cl">; 319defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "image_gather4_c_lz">; 320defm IMAGE_GATHER4_O : MIMG_Gather_WQM <0x00000050, "image_gather4_o">; 321defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <0x00000051, "image_gather4_cl_o">; 322defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "image_gather4_l_o">; 323defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <0x00000055, "image_gather4_b_o">; 324defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "image_gather4_b_cl_o">; 325defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "image_gather4_lz_o">; 326defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <0x00000058, "image_gather4_c_o">; 327defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <0x00000059, "image_gather4_c_cl_o">; 328defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "image_gather4_c_l_o">; 329defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <0x0000005d, "image_gather4_c_b_o">; 330defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <0x0000005e, "image_gather4_c_b_cl_o">; 331defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "image_gather4_c_lz_o">; 332defm IMAGE_GET_LOD : MIMG_Sampler_WQM <0x00000060, "image_get_lod">; 333defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "image_sample_cd">; 334defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "image_sample_cd_cl">; 335defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "image_sample_c_cd">; 336defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "image_sample_c_cd_cl">; 337defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "image_sample_cd_o">; 338defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "image_sample_cd_cl_o">; 339defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "image_sample_c_cd_o">; 340defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "image_sample_c_cd_cl_o">; 341//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>; 342//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>; 343} 344 345/********** ======================= **********/ 346/********** Image sampling patterns **********/ 347/********** ======================= **********/ 348 349// Image + sampler 350class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat < 351 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm, 352 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe), 353 (opcode $addr, $rsrc, $sampler, 354 (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc), 355 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da)) 356>; 357 358multiclass SampleRawPatterns<SDPatternOperator name, string opcode> { 359 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>; 360 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>; 361 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>; 362 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>; 363 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>; 364} 365 366// Image + sampler for amdgcn 367// TODO: 368// 1. Handle half data type like v4f16, and add D16 bit support; 369// 2. Handle v4i32 rsrc type (Register Class for the instruction to be SReg_128). 370// 3. Add A16 support when we pass address of half type. 371multiclass AMDGCNSamplePattern<SDPatternOperator name, MIMG opcode, ValueType vt> { 372 def : Pat< 373 (v4f32 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i1:$unorm, i1:$glc, 374 i1:$slc, i1:$lwe, i1:$da)), 375 (opcode $addr, $rsrc, $sampler, 376 (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc), 377 0, 0, (as_i1imm $lwe), (as_i1imm $da)) 378 >; 379} 380 381multiclass AMDGCNSamplePatterns<SDPatternOperator name, string opcode> { 382 defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V4_V1), f32>; 383 defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V4_V2), v2f32>; 384 defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V4_V4), v4f32>; 385 defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V4_V8), v8f32>; 386 defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V4_V16), v16f32>; 387} 388 389// Image only 390class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat < 391 (name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$unorm, 392 imm:$r128, imm:$da, imm:$glc, imm:$slc, imm:$tfe, imm:$lwe), 393 (opcode $addr, $rsrc, 394 (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc), 395 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da)) 396>; 397 398multiclass ImagePatterns<SDPatternOperator name, string opcode> { 399 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>; 400 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>; 401 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>; 402} 403 404multiclass ImageLoadPattern<SDPatternOperator name, MIMG opcode, ValueType vt> { 405 def : Pat < 406 (v4f32 (name vt:$addr, v8i32:$rsrc, i32:$dmask, i1:$glc, i1:$slc, i1:$lwe, 407 i1:$da)), 408 (opcode $addr, $rsrc, 409 (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc), 410 0, 0, (as_i1imm $lwe), (as_i1imm $da)) 411 >; 412} 413 414multiclass ImageLoadPatterns<SDPatternOperator name, string opcode> { 415 defm : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>; 416 defm : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>; 417 defm : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>; 418} 419 420multiclass ImageStorePattern<SDPatternOperator name, MIMG opcode, ValueType vt> { 421 def : Pat < 422 (name v4f32:$data, vt:$addr, v8i32:$rsrc, i32:$dmask, i1:$glc, i1:$slc, 423 i1:$lwe, i1:$da), 424 (opcode $data, $addr, $rsrc, 425 (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc), 426 0, 0, (as_i1imm $lwe), (as_i1imm $da)) 427 >; 428} 429 430multiclass ImageStorePatterns<SDPatternOperator name, string opcode> { 431 defm : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>; 432 defm : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>; 433 defm : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>; 434} 435 436class ImageAtomicPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat < 437 (name i32:$vdata, vt:$addr, v8i32:$rsrc, imm:$r128, imm:$da, imm:$slc), 438 (opcode $vdata, $addr, $rsrc, 1, 1, 1, (as_i1imm $slc), (as_i1imm $r128), 0, 0, (as_i1imm $da)) 439>; 440 441multiclass ImageAtomicPatterns<SDPatternOperator name, string opcode> { 442 def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V1), i32>; 443 def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V2), v2i32>; 444 def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V4), v4i32>; 445} 446 447class ImageAtomicCmpSwapPattern<MIMG opcode, ValueType vt> : Pat < 448 (int_amdgcn_image_atomic_cmpswap i32:$vsrc, i32:$vcmp, vt:$addr, v8i32:$rsrc, 449 imm:$r128, imm:$da, imm:$slc), 450 (EXTRACT_SUBREG 451 (opcode (REG_SEQUENCE VReg_64, $vsrc, sub0, $vcmp, sub1), 452 $addr, $rsrc, 3, 1, 1, (as_i1imm $slc), (as_i1imm $r128), 0, 0, (as_i1imm $da)), 453 sub0) 454>; 455 456// ======= SI Image Intrinsics ================ 457 458// Image load 459defm : ImagePatterns<int_SI_image_load, "IMAGE_LOAD">; 460defm : ImagePatterns<int_SI_image_load_mip, "IMAGE_LOAD_MIP">; 461def : ImagePattern<int_SI_getresinfo, IMAGE_GET_RESINFO_V4_V1, i32>; 462 463// Basic sample 464defm : SampleRawPatterns<int_SI_image_sample, "IMAGE_SAMPLE">; 465defm : SampleRawPatterns<int_SI_image_sample_cl, "IMAGE_SAMPLE_CL">; 466defm : SampleRawPatterns<int_SI_image_sample_d, "IMAGE_SAMPLE_D">; 467defm : SampleRawPatterns<int_SI_image_sample_d_cl, "IMAGE_SAMPLE_D_CL">; 468defm : SampleRawPatterns<int_SI_image_sample_l, "IMAGE_SAMPLE_L">; 469defm : SampleRawPatterns<int_SI_image_sample_b, "IMAGE_SAMPLE_B">; 470defm : SampleRawPatterns<int_SI_image_sample_b_cl, "IMAGE_SAMPLE_B_CL">; 471defm : SampleRawPatterns<int_SI_image_sample_lz, "IMAGE_SAMPLE_LZ">; 472defm : SampleRawPatterns<int_SI_image_sample_cd, "IMAGE_SAMPLE_CD">; 473defm : SampleRawPatterns<int_SI_image_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">; 474 475// Sample with comparison 476defm : SampleRawPatterns<int_SI_image_sample_c, "IMAGE_SAMPLE_C">; 477defm : SampleRawPatterns<int_SI_image_sample_c_cl, "IMAGE_SAMPLE_C_CL">; 478defm : SampleRawPatterns<int_SI_image_sample_c_d, "IMAGE_SAMPLE_C_D">; 479defm : SampleRawPatterns<int_SI_image_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">; 480defm : SampleRawPatterns<int_SI_image_sample_c_l, "IMAGE_SAMPLE_C_L">; 481defm : SampleRawPatterns<int_SI_image_sample_c_b, "IMAGE_SAMPLE_C_B">; 482defm : SampleRawPatterns<int_SI_image_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">; 483defm : SampleRawPatterns<int_SI_image_sample_c_lz, "IMAGE_SAMPLE_C_LZ">; 484defm : SampleRawPatterns<int_SI_image_sample_c_cd, "IMAGE_SAMPLE_C_CD">; 485defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">; 486 487// Sample with offsets 488defm : SampleRawPatterns<int_SI_image_sample_o, "IMAGE_SAMPLE_O">; 489defm : SampleRawPatterns<int_SI_image_sample_cl_o, "IMAGE_SAMPLE_CL_O">; 490defm : SampleRawPatterns<int_SI_image_sample_d_o, "IMAGE_SAMPLE_D_O">; 491defm : SampleRawPatterns<int_SI_image_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">; 492defm : SampleRawPatterns<int_SI_image_sample_l_o, "IMAGE_SAMPLE_L_O">; 493defm : SampleRawPatterns<int_SI_image_sample_b_o, "IMAGE_SAMPLE_B_O">; 494defm : SampleRawPatterns<int_SI_image_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">; 495defm : SampleRawPatterns<int_SI_image_sample_lz_o, "IMAGE_SAMPLE_LZ_O">; 496defm : SampleRawPatterns<int_SI_image_sample_cd_o, "IMAGE_SAMPLE_CD_O">; 497defm : SampleRawPatterns<int_SI_image_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">; 498 499// Sample with comparison and offsets 500defm : SampleRawPatterns<int_SI_image_sample_c_o, "IMAGE_SAMPLE_C_O">; 501defm : SampleRawPatterns<int_SI_image_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">; 502defm : SampleRawPatterns<int_SI_image_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">; 503defm : SampleRawPatterns<int_SI_image_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">; 504defm : SampleRawPatterns<int_SI_image_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">; 505defm : SampleRawPatterns<int_SI_image_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">; 506defm : SampleRawPatterns<int_SI_image_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">; 507defm : SampleRawPatterns<int_SI_image_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">; 508defm : SampleRawPatterns<int_SI_image_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">; 509defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">; 510 511// Gather opcodes 512// Only the variants which make sense are defined. 513def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V2, v2i32>; 514def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V4, v4i32>; 515def : SampleRawPattern<int_SI_gather4_cl, IMAGE_GATHER4_CL_V4_V4, v4i32>; 516def : SampleRawPattern<int_SI_gather4_l, IMAGE_GATHER4_L_V4_V4, v4i32>; 517def : SampleRawPattern<int_SI_gather4_b, IMAGE_GATHER4_B_V4_V4, v4i32>; 518def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V4, v4i32>; 519def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8i32>; 520def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V2, v2i32>; 521def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V4, v4i32>; 522 523def : SampleRawPattern<int_SI_gather4_c, IMAGE_GATHER4_C_V4_V4, v4i32>; 524def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V4, v4i32>; 525def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8i32>; 526def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V4, v4i32>; 527def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8i32>; 528def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V4, v4i32>; 529def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8i32>; 530def : SampleRawPattern<int_SI_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8i32>; 531def : SampleRawPattern<int_SI_gather4_c_lz, IMAGE_GATHER4_C_LZ_V4_V4, v4i32>; 532 533def : SampleRawPattern<int_SI_gather4_o, IMAGE_GATHER4_O_V4_V4, v4i32>; 534def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V4, v4i32>; 535def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8i32>; 536def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V4, v4i32>; 537def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V8, v8i32>; 538def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V4, v4i32>; 539def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V8, v8i32>; 540def : SampleRawPattern<int_SI_gather4_b_cl_o, IMAGE_GATHER4_B_CL_O_V4_V8, v8i32>; 541def : SampleRawPattern<int_SI_gather4_lz_o, IMAGE_GATHER4_LZ_O_V4_V4, v4i32>; 542 543def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V4, v4i32>; 544def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V8, v8i32>; 545def : SampleRawPattern<int_SI_gather4_c_cl_o, IMAGE_GATHER4_C_CL_O_V4_V8, v8i32>; 546def : SampleRawPattern<int_SI_gather4_c_l_o, IMAGE_GATHER4_C_L_O_V4_V8, v8i32>; 547def : SampleRawPattern<int_SI_gather4_c_b_o, IMAGE_GATHER4_C_B_O_V4_V8, v8i32>; 548def : SampleRawPattern<int_SI_gather4_c_b_cl_o, IMAGE_GATHER4_C_B_CL_O_V4_V8, v8i32>; 549def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V4, v4i32>; 550def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V8, v8i32>; 551 552def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V1, i32>; 553def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V2, v2i32>; 554def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V4, v4i32>; 555 556// ======= amdgcn Image Intrinsics ============== 557 558// Image load 559defm : ImageLoadPatterns<int_amdgcn_image_load, "IMAGE_LOAD">; 560defm : ImageLoadPatterns<int_amdgcn_image_load_mip, "IMAGE_LOAD_MIP">; 561defm : ImageLoadPattern<int_amdgcn_image_getresinfo, IMAGE_GET_RESINFO_V4_V1, i32>; 562 563// Image store 564defm : ImageStorePatterns<int_amdgcn_image_store, "IMAGE_STORE">; 565defm : ImageStorePatterns<int_amdgcn_image_store_mip, "IMAGE_STORE_MIP">; 566 567// Basic sample 568defm : AMDGCNSamplePatterns<int_amdgcn_image_sample, "IMAGE_SAMPLE">; 569defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cl, "IMAGE_SAMPLE_CL">; 570defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_d, "IMAGE_SAMPLE_D">; 571defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_d_cl, "IMAGE_SAMPLE_D_CL">; 572defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_l, "IMAGE_SAMPLE_L">; 573defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_b, "IMAGE_SAMPLE_B">; 574defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_b_cl, "IMAGE_SAMPLE_B_CL">; 575defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_lz, "IMAGE_SAMPLE_LZ">; 576defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cd, "IMAGE_SAMPLE_CD">; 577defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">; 578 579// Sample with comparison 580defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c, "IMAGE_SAMPLE_C">; 581defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cl, "IMAGE_SAMPLE_C_CL">; 582defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_d, "IMAGE_SAMPLE_C_D">; 583defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">; 584defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_l, "IMAGE_SAMPLE_C_L">; 585defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_b, "IMAGE_SAMPLE_C_B">; 586defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">; 587defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_lz, "IMAGE_SAMPLE_C_LZ">; 588defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cd, "IMAGE_SAMPLE_C_CD">; 589defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">; 590 591// Sample with offsets 592defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_o, "IMAGE_SAMPLE_O">; 593defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cl_o, "IMAGE_SAMPLE_CL_O">; 594defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_d_o, "IMAGE_SAMPLE_D_O">; 595defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">; 596defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_l_o, "IMAGE_SAMPLE_L_O">; 597defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_b_o, "IMAGE_SAMPLE_B_O">; 598defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">; 599defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_lz_o, "IMAGE_SAMPLE_LZ_O">; 600defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cd_o, "IMAGE_SAMPLE_CD_O">; 601defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">; 602 603// Sample with comparison and offsets 604defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_o, "IMAGE_SAMPLE_C_O">; 605defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">; 606defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">; 607defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">; 608defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">; 609defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">; 610defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">; 611defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">; 612defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">; 613defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">; 614 615// Gather opcodes 616// Only the variants which make sense are defined. 617defm : AMDGCNSamplePattern<int_amdgcn_image_gather4, IMAGE_GATHER4_V4_V2, v2f32>; 618defm : AMDGCNSamplePattern<int_amdgcn_image_gather4, IMAGE_GATHER4_V4_V4, v4f32>; 619defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_cl, IMAGE_GATHER4_CL_V4_V4, v4f32>; 620defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_l, IMAGE_GATHER4_L_V4_V4, v4f32>; 621defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_b, IMAGE_GATHER4_B_V4_V4, v4f32>; 622defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V4, v4f32>; 623defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8f32>; 624defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_lz, IMAGE_GATHER4_LZ_V4_V2, v2f32>; 625defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_lz, IMAGE_GATHER4_LZ_V4_V4, v4f32>; 626 627defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c, IMAGE_GATHER4_C_V4_V4, v4f32>; 628defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V4, v4f32>; 629defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8f32>; 630defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_l, IMAGE_GATHER4_C_L_V4_V4, v4f32>; 631defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8f32>; 632defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_b, IMAGE_GATHER4_C_B_V4_V4, v4f32>; 633defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8f32>; 634defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8f32>; 635defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_lz, IMAGE_GATHER4_C_LZ_V4_V4, v4f32>; 636 637defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_o, IMAGE_GATHER4_O_V4_V4, v4f32>; 638defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V4, v4f32>; 639defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8f32>; 640defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_l_o, IMAGE_GATHER4_L_O_V4_V4, v4f32>; 641defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_l_o, IMAGE_GATHER4_L_O_V4_V8, v8f32>; 642defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_b_o, IMAGE_GATHER4_B_O_V4_V4, v4f32>; 643defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_b_o, IMAGE_GATHER4_B_O_V4_V8, v8f32>; 644defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_b_cl_o, IMAGE_GATHER4_B_CL_O_V4_V8, v8f32>; 645defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_lz_o, IMAGE_GATHER4_LZ_O_V4_V4, v4f32>; 646 647defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_o, IMAGE_GATHER4_C_O_V4_V4, v4f32>; 648defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_o, IMAGE_GATHER4_C_O_V4_V8, v8f32>; 649defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_cl_o, IMAGE_GATHER4_C_CL_O_V4_V8, v8f32>; 650defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_l_o, IMAGE_GATHER4_C_L_O_V4_V8, v8f32>; 651defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_b_o, IMAGE_GATHER4_C_B_O_V4_V8, v8f32>; 652defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_b_cl_o, IMAGE_GATHER4_C_B_CL_O_V4_V8, v8f32>; 653defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V4, v4f32>; 654defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V8, v8f32>; 655 656defm : AMDGCNSamplePattern<int_amdgcn_image_getlod, IMAGE_GET_LOD_V4_V1, f32>; 657defm : AMDGCNSamplePattern<int_amdgcn_image_getlod, IMAGE_GET_LOD_V4_V2, v2f32>; 658defm : AMDGCNSamplePattern<int_amdgcn_image_getlod, IMAGE_GET_LOD_V4_V4, v4f32>; 659 660// Image atomics 661defm : ImageAtomicPatterns<int_amdgcn_image_atomic_swap, "IMAGE_ATOMIC_SWAP">; 662def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V1, i32>; 663def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V2, v2i32>; 664def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V4, v4i32>; 665defm : ImageAtomicPatterns<int_amdgcn_image_atomic_add, "IMAGE_ATOMIC_ADD">; 666defm : ImageAtomicPatterns<int_amdgcn_image_atomic_sub, "IMAGE_ATOMIC_SUB">; 667defm : ImageAtomicPatterns<int_amdgcn_image_atomic_smin, "IMAGE_ATOMIC_SMIN">; 668defm : ImageAtomicPatterns<int_amdgcn_image_atomic_umin, "IMAGE_ATOMIC_UMIN">; 669defm : ImageAtomicPatterns<int_amdgcn_image_atomic_smax, "IMAGE_ATOMIC_SMAX">; 670defm : ImageAtomicPatterns<int_amdgcn_image_atomic_umax, "IMAGE_ATOMIC_UMAX">; 671defm : ImageAtomicPatterns<int_amdgcn_image_atomic_and, "IMAGE_ATOMIC_AND">; 672defm : ImageAtomicPatterns<int_amdgcn_image_atomic_or, "IMAGE_ATOMIC_OR">; 673defm : ImageAtomicPatterns<int_amdgcn_image_atomic_xor, "IMAGE_ATOMIC_XOR">; 674defm : ImageAtomicPatterns<int_amdgcn_image_atomic_inc, "IMAGE_ATOMIC_INC">; 675defm : ImageAtomicPatterns<int_amdgcn_image_atomic_dec, "IMAGE_ATOMIC_DEC">; 676 677/* SIsample for simple 1D texture lookup */ 678def : Pat < 679 (SIsample i32:$addr, v8i32:$rsrc, v4i32:$sampler, imm), 680 (IMAGE_SAMPLE_V4_V1 $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0) 681>; 682 683class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 684 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, imm), 685 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0) 686>; 687 688class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 689 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_RECT), 690 (opcode $addr, $rsrc, $sampler, 0xf, 1, 0, 0, 0, 0, 0, 0) 691>; 692 693class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 694 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_ARRAY), 695 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1) 696>; 697 698class SampleShadowPattern<SDNode name, MIMG opcode, 699 ValueType vt> : Pat < 700 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW), 701 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0) 702>; 703 704class SampleShadowArrayPattern<SDNode name, MIMG opcode, 705 ValueType vt> : Pat < 706 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY), 707 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1) 708>; 709 710/* SIsample* for texture lookups consuming more address parameters */ 711multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l, 712 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b, 713MIMG sample_d, MIMG sample_c_d, ValueType addr_type> { 714 def : SamplePattern <SIsample, sample, addr_type>; 715 def : SampleRectPattern <SIsample, sample, addr_type>; 716 def : SampleArrayPattern <SIsample, sample, addr_type>; 717 def : SampleShadowPattern <SIsample, sample_c, addr_type>; 718 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>; 719 720 def : SamplePattern <SIsamplel, sample_l, addr_type>; 721 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>; 722 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>; 723 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>; 724 725 def : SamplePattern <SIsampleb, sample_b, addr_type>; 726 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>; 727 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>; 728 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>; 729 730 def : SamplePattern <SIsampled, sample_d, addr_type>; 731 def : SampleArrayPattern <SIsampled, sample_d, addr_type>; 732 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>; 733 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>; 734} 735 736defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2, 737 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2, 738 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2, 739 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2, 740 v2i32>; 741defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4, 742 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4, 743 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4, 744 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4, 745 v4i32>; 746defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8, 747 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8, 748 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8, 749 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8, 750 v8i32>; 751defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16, 752 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16, 753 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16, 754 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16, 755 v16i32>; 756