1 //===-- SIMCCodeEmitter.cpp - SI Code Emitter -------------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The SI code emitter produces machine code that can be executed
12 /// directly on the GPU device.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPU.h"
17 #include "MCTargetDesc/AMDGPUFixupKinds.h"
18 #include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
19 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
20 #include "SIDefines.h"
21 #include "Utils/AMDGPUBaseInfo.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCFixup.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/raw_ostream.h"
31 
32 using namespace llvm;
33 
34 namespace {
35 
36 class SIMCCodeEmitter : public  AMDGPUMCCodeEmitter {
37   SIMCCodeEmitter(const SIMCCodeEmitter &) = delete;
38   void operator=(const SIMCCodeEmitter &) = delete;
39   const MCInstrInfo &MCII;
40   const MCRegisterInfo &MRI;
41 
42   /// \brief Encode an fp or int literal
43   uint32_t getLitEncoding(const MCOperand &MO, unsigned OpSize,
44                           const MCSubtargetInfo &STI) const;
45 
46 public:
47   SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
48                   MCContext &ctx)
49     : MCII(mcii), MRI(mri) { }
50 
51   ~SIMCCodeEmitter() override {}
52 
53   /// \brief Encode the instruction and write it to the OS.
54   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
55                          SmallVectorImpl<MCFixup> &Fixups,
56                          const MCSubtargetInfo &STI) const override;
57 
58   /// \returns the encoding for an MCOperand.
59   uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
60                              SmallVectorImpl<MCFixup> &Fixups,
61                              const MCSubtargetInfo &STI) const override;
62 
63   /// \brief Use a fixup to encode the simm16 field for SOPP branch
64   ///        instructions.
65   unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
66                              SmallVectorImpl<MCFixup> &Fixups,
67                              const MCSubtargetInfo &STI) const override;
68 };
69 
70 } // End anonymous namespace
71 
72 MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
73                                            const MCRegisterInfo &MRI,
74                                            MCContext &Ctx) {
75   return new SIMCCodeEmitter(MCII, MRI, Ctx);
76 }
77 
78 // Returns the encoding value to use if the given integer is an integer inline
79 // immediate value, or 0 if it is not.
80 template <typename IntTy>
81 static uint32_t getIntInlineImmEncoding(IntTy Imm) {
82   if (Imm >= 0 && Imm <= 64)
83     return 128 + Imm;
84 
85   if (Imm >= -16 && Imm <= -1)
86     return 192 + std::abs(Imm);
87 
88   return 0;
89 }
90 
91 static uint32_t getLit32Encoding(uint32_t Val, const MCSubtargetInfo &STI) {
92   uint32_t IntImm = getIntInlineImmEncoding(static_cast<int32_t>(Val));
93   if (IntImm != 0)
94     return IntImm;
95 
96   if (Val == FloatToBits(0.5f))
97     return 240;
98 
99   if (Val == FloatToBits(-0.5f))
100     return 241;
101 
102   if (Val == FloatToBits(1.0f))
103     return 242;
104 
105   if (Val == FloatToBits(-1.0f))
106     return 243;
107 
108   if (Val == FloatToBits(2.0f))
109     return 244;
110 
111   if (Val == FloatToBits(-2.0f))
112     return 245;
113 
114   if (Val == FloatToBits(4.0f))
115     return 246;
116 
117   if (Val == FloatToBits(-4.0f))
118     return 247;
119 
120   if (Val == 0x3e22f983 && // 1.0 / (2.0 * pi)
121       STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
122     return 248;
123 
124   return 255;
125 }
126 
127 static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) {
128   uint32_t IntImm = getIntInlineImmEncoding(static_cast<int64_t>(Val));
129   if (IntImm != 0)
130     return IntImm;
131 
132   if (Val == DoubleToBits(0.5))
133     return 240;
134 
135   if (Val == DoubleToBits(-0.5))
136     return 241;
137 
138   if (Val == DoubleToBits(1.0))
139     return 242;
140 
141   if (Val == DoubleToBits(-1.0))
142     return 243;
143 
144   if (Val == DoubleToBits(2.0))
145     return 244;
146 
147   if (Val == DoubleToBits(-2.0))
148     return 245;
149 
150   if (Val == DoubleToBits(4.0))
151     return 246;
152 
153   if (Val == DoubleToBits(-4.0))
154     return 247;
155 
156   if (Val == 0x3fc45f306dc9c882 && // 1.0 / (2.0 * pi)
157       STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
158     return 248;
159 
160   return 255;
161 }
162 
163 uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
164                                          unsigned OpSize,
165                                          const MCSubtargetInfo &STI) const {
166 
167   int64_t Imm;
168   if (MO.isExpr()) {
169     const MCConstantExpr *C = dyn_cast<MCConstantExpr>(MO.getExpr());
170     if (!C)
171       return 255;
172 
173     Imm = C->getValue();
174   } else {
175 
176     assert(!MO.isFPImm());
177 
178     if (!MO.isImm())
179       return ~0;
180 
181     Imm = MO.getImm();
182   }
183 
184   if (OpSize == 4)
185     return getLit32Encoding(static_cast<uint32_t>(Imm), STI);
186 
187   assert(OpSize == 8);
188 
189   return getLit64Encoding(static_cast<uint64_t>(Imm), STI);
190 }
191 
192 void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
193                                        SmallVectorImpl<MCFixup> &Fixups,
194                                        const MCSubtargetInfo &STI) const {
195 
196   uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
197   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
198   unsigned bytes = Desc.getSize();
199 
200   for (unsigned i = 0; i < bytes; i++) {
201     OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
202   }
203 
204   if (bytes > 4)
205     return;
206 
207   // Check for additional literals in SRC0/1/2 (Op 1/2/3)
208   for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {
209 
210     // Check if this operand should be encoded as [SV]Src
211     if (!AMDGPU::isSISrcOperand(Desc, i))
212       continue;
213 
214     int RCID = Desc.OpInfo[i].RegClass;
215     const MCRegisterClass &RC = MRI.getRegClass(RCID);
216 
217     // Is this operand a literal immediate?
218     const MCOperand &Op = MI.getOperand(i);
219     if (getLitEncoding(Op, AMDGPU::getRegBitWidth(RC) / 8, STI) != 255)
220       continue;
221 
222     // Yes! Encode it
223     int64_t Imm = 0;
224 
225     if (Op.isImm())
226       Imm = Op.getImm();
227     else if (Op.isExpr()) {
228       if (const MCConstantExpr *C = dyn_cast<MCConstantExpr>(Op.getExpr()))
229         Imm = C->getValue();
230 
231     } else if (!Op.isExpr()) // Exprs will be replaced with a fixup value.
232       llvm_unreachable("Must be immediate or expr");
233 
234     for (unsigned j = 0; j < 4; j++) {
235       OS.write((uint8_t) ((Imm >> (8 * j)) & 0xff));
236     }
237 
238     // Only one literal value allowed
239     break;
240   }
241 }
242 
243 unsigned SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
244                                             SmallVectorImpl<MCFixup> &Fixups,
245                                             const MCSubtargetInfo &STI) const {
246   const MCOperand &MO = MI.getOperand(OpNo);
247 
248   if (MO.isExpr()) {
249     const MCExpr *Expr = MO.getExpr();
250     MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br;
251     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
252     return 0;
253   }
254 
255   return getMachineOpValue(MI, MO, Fixups, STI);
256 }
257 
258 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
259                                             const MCOperand &MO,
260                                        SmallVectorImpl<MCFixup> &Fixups,
261                                        const MCSubtargetInfo &STI) const {
262   if (MO.isReg())
263     return MRI.getEncodingValue(MO.getReg());
264 
265   if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) {
266     const MCSymbolRefExpr *Expr = dyn_cast<MCSymbolRefExpr>(MO.getExpr());
267     MCFixupKind Kind;
268     if (Expr && Expr->getSymbol().isExternal())
269       Kind = FK_Data_4;
270     else
271       Kind = FK_PCRel_4;
272     Fixups.push_back(MCFixup::create(4, MO.getExpr(), Kind, MI.getLoc()));
273   }
274 
275   // Figure out the operand number, needed for isSrcOperand check
276   unsigned OpNo = 0;
277   for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) {
278     if (&MO == &MI.getOperand(OpNo))
279       break;
280   }
281 
282   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
283   if (AMDGPU::isSISrcOperand(Desc, OpNo)) {
284     uint32_t Enc = getLitEncoding(MO,
285                                   AMDGPU::getRegOperandSize(&MRI, Desc, OpNo),
286                                   STI);
287     if (Enc != ~0U && (Enc != 255 || Desc.getSize() == 4))
288       return Enc;
289 
290   } else if (MO.isImm())
291     return MO.getImm();
292 
293   llvm_unreachable("Encoding of this operand type is not supported yet.");
294   return 0;
295 }
296 
297