1 //===-- SIMCCodeEmitter.cpp - SI Code Emitter -----------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// The SI code emitter produces machine code that can be executed 11 /// directly on the GPU device. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "MCTargetDesc/AMDGPUFixupKinds.h" 16 #include "MCTargetDesc/AMDGPUMCCodeEmitter.h" 17 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 18 #include "SIDefines.h" 19 #include "Utils/AMDGPUBaseInfo.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCInstrInfo.h" 23 #include "llvm/MC/MCRegisterInfo.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/MC/SubtargetFeature.h" 26 #include "llvm/Support/Casting.h" 27 28 using namespace llvm; 29 30 namespace { 31 32 class SIMCCodeEmitter : public AMDGPUMCCodeEmitter { 33 const MCRegisterInfo &MRI; 34 35 /// Encode an fp or int literal 36 uint32_t getLitEncoding(const MCOperand &MO, const MCOperandInfo &OpInfo, 37 const MCSubtargetInfo &STI) const; 38 39 public: 40 SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri, 41 MCContext &ctx) 42 : AMDGPUMCCodeEmitter(mcii), MRI(mri) {} 43 SIMCCodeEmitter(const SIMCCodeEmitter &) = delete; 44 SIMCCodeEmitter &operator=(const SIMCCodeEmitter &) = delete; 45 46 /// Encode the instruction and write it to the OS. 47 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 48 SmallVectorImpl<MCFixup> &Fixups, 49 const MCSubtargetInfo &STI) const override; 50 51 /// \returns the encoding for an MCOperand. 52 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 53 SmallVectorImpl<MCFixup> &Fixups, 54 const MCSubtargetInfo &STI) const override; 55 56 /// Use a fixup to encode the simm16 field for SOPP branch 57 /// instructions. 58 unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, 59 SmallVectorImpl<MCFixup> &Fixups, 60 const MCSubtargetInfo &STI) const override; 61 62 unsigned getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo, 63 SmallVectorImpl<MCFixup> &Fixups, 64 const MCSubtargetInfo &STI) const override; 65 66 unsigned getSDWASrcEncoding(const MCInst &MI, unsigned OpNo, 67 SmallVectorImpl<MCFixup> &Fixups, 68 const MCSubtargetInfo &STI) const override; 69 70 unsigned getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo, 71 SmallVectorImpl<MCFixup> &Fixups, 72 const MCSubtargetInfo &STI) const override; 73 74 unsigned getAVOperandEncoding(const MCInst &MI, unsigned OpNo, 75 SmallVectorImpl<MCFixup> &Fixups, 76 const MCSubtargetInfo &STI) const override; 77 78 private: 79 uint64_t getImplicitOpSelHiEncoding(int Opcode) const; 80 }; 81 82 } // end anonymous namespace 83 84 MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII, 85 const MCRegisterInfo &MRI, 86 MCContext &Ctx) { 87 return new SIMCCodeEmitter(MCII, MRI, Ctx); 88 } 89 90 // Returns the encoding value to use if the given integer is an integer inline 91 // immediate value, or 0 if it is not. 92 template <typename IntTy> 93 static uint32_t getIntInlineImmEncoding(IntTy Imm) { 94 if (Imm >= 0 && Imm <= 64) 95 return 128 + Imm; 96 97 if (Imm >= -16 && Imm <= -1) 98 return 192 + std::abs(Imm); 99 100 return 0; 101 } 102 103 static uint32_t getLit16IntEncoding(uint16_t Val, const MCSubtargetInfo &STI) { 104 uint16_t IntImm = getIntInlineImmEncoding(static_cast<int16_t>(Val)); 105 return IntImm == 0 ? 255 : IntImm; 106 } 107 108 static uint32_t getLit16Encoding(uint16_t Val, const MCSubtargetInfo &STI) { 109 uint16_t IntImm = getIntInlineImmEncoding(static_cast<int16_t>(Val)); 110 if (IntImm != 0) 111 return IntImm; 112 113 if (Val == 0x3800) // 0.5 114 return 240; 115 116 if (Val == 0xB800) // -0.5 117 return 241; 118 119 if (Val == 0x3C00) // 1.0 120 return 242; 121 122 if (Val == 0xBC00) // -1.0 123 return 243; 124 125 if (Val == 0x4000) // 2.0 126 return 244; 127 128 if (Val == 0xC000) // -2.0 129 return 245; 130 131 if (Val == 0x4400) // 4.0 132 return 246; 133 134 if (Val == 0xC400) // -4.0 135 return 247; 136 137 if (Val == 0x3118 && // 1.0 / (2.0 * pi) 138 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) 139 return 248; 140 141 return 255; 142 } 143 144 static uint32_t getLit32Encoding(uint32_t Val, const MCSubtargetInfo &STI) { 145 uint32_t IntImm = getIntInlineImmEncoding(static_cast<int32_t>(Val)); 146 if (IntImm != 0) 147 return IntImm; 148 149 if (Val == FloatToBits(0.5f)) 150 return 240; 151 152 if (Val == FloatToBits(-0.5f)) 153 return 241; 154 155 if (Val == FloatToBits(1.0f)) 156 return 242; 157 158 if (Val == FloatToBits(-1.0f)) 159 return 243; 160 161 if (Val == FloatToBits(2.0f)) 162 return 244; 163 164 if (Val == FloatToBits(-2.0f)) 165 return 245; 166 167 if (Val == FloatToBits(4.0f)) 168 return 246; 169 170 if (Val == FloatToBits(-4.0f)) 171 return 247; 172 173 if (Val == 0x3e22f983 && // 1.0 / (2.0 * pi) 174 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) 175 return 248; 176 177 return 255; 178 } 179 180 static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) { 181 uint32_t IntImm = getIntInlineImmEncoding(static_cast<int64_t>(Val)); 182 if (IntImm != 0) 183 return IntImm; 184 185 if (Val == DoubleToBits(0.5)) 186 return 240; 187 188 if (Val == DoubleToBits(-0.5)) 189 return 241; 190 191 if (Val == DoubleToBits(1.0)) 192 return 242; 193 194 if (Val == DoubleToBits(-1.0)) 195 return 243; 196 197 if (Val == DoubleToBits(2.0)) 198 return 244; 199 200 if (Val == DoubleToBits(-2.0)) 201 return 245; 202 203 if (Val == DoubleToBits(4.0)) 204 return 246; 205 206 if (Val == DoubleToBits(-4.0)) 207 return 247; 208 209 if (Val == 0x3fc45f306dc9c882 && // 1.0 / (2.0 * pi) 210 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) 211 return 248; 212 213 return 255; 214 } 215 216 uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO, 217 const MCOperandInfo &OpInfo, 218 const MCSubtargetInfo &STI) const { 219 int64_t Imm; 220 if (MO.isExpr()) { 221 const auto *C = dyn_cast<MCConstantExpr>(MO.getExpr()); 222 if (!C) 223 return 255; 224 225 Imm = C->getValue(); 226 } else { 227 228 assert(!MO.isDFPImm()); 229 230 if (!MO.isImm()) 231 return ~0; 232 233 Imm = MO.getImm(); 234 } 235 236 switch (OpInfo.OperandType) { 237 case AMDGPU::OPERAND_REG_IMM_INT32: 238 case AMDGPU::OPERAND_REG_IMM_FP32: 239 case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED: 240 case AMDGPU::OPERAND_REG_INLINE_C_INT32: 241 case AMDGPU::OPERAND_REG_INLINE_C_FP32: 242 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: 243 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: 244 case AMDGPU::OPERAND_REG_IMM_V2INT32: 245 case AMDGPU::OPERAND_REG_IMM_V2FP32: 246 case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: 247 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: 248 return getLit32Encoding(static_cast<uint32_t>(Imm), STI); 249 250 case AMDGPU::OPERAND_REG_IMM_INT64: 251 case AMDGPU::OPERAND_REG_IMM_FP64: 252 case AMDGPU::OPERAND_REG_INLINE_C_INT64: 253 case AMDGPU::OPERAND_REG_INLINE_C_FP64: 254 case AMDGPU::OPERAND_REG_INLINE_AC_FP64: 255 return getLit64Encoding(static_cast<uint64_t>(Imm), STI); 256 257 case AMDGPU::OPERAND_REG_IMM_INT16: 258 case AMDGPU::OPERAND_REG_INLINE_C_INT16: 259 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: 260 return getLit16IntEncoding(static_cast<uint16_t>(Imm), STI); 261 case AMDGPU::OPERAND_REG_IMM_FP16: 262 case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED: 263 case AMDGPU::OPERAND_REG_INLINE_C_FP16: 264 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: 265 // FIXME Is this correct? What do inline immediates do on SI for f16 src 266 // which does not have f16 support? 267 return getLit16Encoding(static_cast<uint16_t>(Imm), STI); 268 case AMDGPU::OPERAND_REG_IMM_V2INT16: 269 case AMDGPU::OPERAND_REG_IMM_V2FP16: { 270 if (!isUInt<16>(Imm) && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) 271 return getLit32Encoding(static_cast<uint32_t>(Imm), STI); 272 if (OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_V2FP16) 273 return getLit16Encoding(static_cast<uint16_t>(Imm), STI); 274 LLVM_FALLTHROUGH; 275 } 276 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: 277 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: 278 return getLit16IntEncoding(static_cast<uint16_t>(Imm), STI); 279 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: 280 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: { 281 uint16_t Lo16 = static_cast<uint16_t>(Imm); 282 uint32_t Encoding = getLit16Encoding(Lo16, STI); 283 return Encoding; 284 } 285 case AMDGPU::OPERAND_KIMM32: 286 case AMDGPU::OPERAND_KIMM16: 287 return MO.getImm(); 288 default: 289 llvm_unreachable("invalid operand size"); 290 } 291 } 292 293 uint64_t SIMCCodeEmitter::getImplicitOpSelHiEncoding(int Opcode) const { 294 using namespace AMDGPU::VOP3PEncoding; 295 using namespace AMDGPU::OpName; 296 297 if (AMDGPU::getNamedOperandIdx(Opcode, op_sel_hi) != -1) { 298 if (AMDGPU::getNamedOperandIdx(Opcode, src2) != -1) 299 return 0; 300 if (AMDGPU::getNamedOperandIdx(Opcode, src1) != -1) 301 return OP_SEL_HI_2; 302 if (AMDGPU::getNamedOperandIdx(Opcode, src0) != -1) 303 return OP_SEL_HI_1 | OP_SEL_HI_2; 304 } 305 return OP_SEL_HI_0 | OP_SEL_HI_1 | OP_SEL_HI_2; 306 } 307 308 void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, 309 SmallVectorImpl<MCFixup> &Fixups, 310 const MCSubtargetInfo &STI) const { 311 verifyInstructionPredicates(MI, 312 computeAvailableFeatures(STI.getFeatureBits())); 313 314 int Opcode = MI.getOpcode(); 315 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI); 316 const MCInstrDesc &Desc = MCII.get(Opcode); 317 unsigned bytes = Desc.getSize(); 318 319 // Set unused op_sel_hi bits to 1 for VOP3P and MAI instructions. 320 // Note that accvgpr_read/write are MAI, have src0, but do not use op_sel. 321 if ((Desc.TSFlags & SIInstrFlags::VOP3P) || 322 Opcode == AMDGPU::V_ACCVGPR_READ_B32_vi || 323 Opcode == AMDGPU::V_ACCVGPR_WRITE_B32_vi) { 324 Encoding |= getImplicitOpSelHiEncoding(Opcode); 325 } 326 327 for (unsigned i = 0; i < bytes; i++) { 328 OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff)); 329 } 330 331 // NSA encoding. 332 if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) { 333 int vaddr0 = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 334 AMDGPU::OpName::vaddr0); 335 int srsrc = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 336 AMDGPU::OpName::srsrc); 337 assert(vaddr0 >= 0 && srsrc > vaddr0); 338 unsigned NumExtraAddrs = srsrc - vaddr0 - 1; 339 unsigned NumPadding = (-NumExtraAddrs) & 3; 340 341 for (unsigned i = 0; i < NumExtraAddrs; ++i) 342 OS.write((uint8_t)getMachineOpValue(MI, MI.getOperand(vaddr0 + 1 + i), 343 Fixups, STI)); 344 for (unsigned i = 0; i < NumPadding; ++i) 345 OS.write(0); 346 } 347 348 if ((bytes > 8 && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) || 349 (bytes > 4 && !STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal])) 350 return; 351 352 // Do not print literals from SISrc Operands for insts with mandatory literals 353 int ImmLitIdx = 354 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 355 if (ImmLitIdx != -1) 356 return; 357 358 // Check for additional literals 359 for (unsigned i = 0, e = Desc.getNumOperands(); i < e; ++i) { 360 361 // Check if this operand should be encoded as [SV]Src 362 if (!AMDGPU::isSISrcOperand(Desc, i)) 363 continue; 364 365 // Is this operand a literal immediate? 366 const MCOperand &Op = MI.getOperand(i); 367 if (getLitEncoding(Op, Desc.OpInfo[i], STI) != 255) 368 continue; 369 370 // Yes! Encode it 371 int64_t Imm = 0; 372 373 if (Op.isImm()) 374 Imm = Op.getImm(); 375 else if (Op.isExpr()) { 376 if (const auto *C = dyn_cast<MCConstantExpr>(Op.getExpr())) 377 Imm = C->getValue(); 378 379 } else if (!Op.isExpr()) // Exprs will be replaced with a fixup value. 380 llvm_unreachable("Must be immediate or expr"); 381 382 for (unsigned j = 0; j < 4; j++) { 383 OS.write((uint8_t) ((Imm >> (8 * j)) & 0xff)); 384 } 385 386 // Only one literal value allowed 387 break; 388 } 389 } 390 391 unsigned SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, 392 SmallVectorImpl<MCFixup> &Fixups, 393 const MCSubtargetInfo &STI) const { 394 const MCOperand &MO = MI.getOperand(OpNo); 395 396 if (MO.isExpr()) { 397 const MCExpr *Expr = MO.getExpr(); 398 MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br; 399 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 400 return 0; 401 } 402 403 return getMachineOpValue(MI, MO, Fixups, STI); 404 } 405 406 unsigned SIMCCodeEmitter::getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo, 407 SmallVectorImpl<MCFixup> &Fixups, 408 const MCSubtargetInfo &STI) const { 409 auto Offset = MI.getOperand(OpNo).getImm(); 410 // VI only supports 20-bit unsigned offsets. 411 assert(!AMDGPU::isVI(STI) || isUInt<20>(Offset)); 412 return Offset; 413 } 414 415 unsigned 416 SIMCCodeEmitter::getSDWASrcEncoding(const MCInst &MI, unsigned OpNo, 417 SmallVectorImpl<MCFixup> &Fixups, 418 const MCSubtargetInfo &STI) const { 419 using namespace AMDGPU::SDWA; 420 421 uint64_t RegEnc = 0; 422 423 const MCOperand &MO = MI.getOperand(OpNo); 424 425 if (MO.isReg()) { 426 unsigned Reg = MO.getReg(); 427 RegEnc |= MRI.getEncodingValue(Reg); 428 RegEnc &= SDWA9EncValues::SRC_VGPR_MASK; 429 if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) { 430 RegEnc |= SDWA9EncValues::SRC_SGPR_MASK; 431 } 432 return RegEnc; 433 } else { 434 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 435 uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI); 436 if (Enc != ~0U && Enc != 255) { 437 return Enc | SDWA9EncValues::SRC_SGPR_MASK; 438 } 439 } 440 441 llvm_unreachable("Unsupported operand kind"); 442 return 0; 443 } 444 445 unsigned 446 SIMCCodeEmitter::getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo, 447 SmallVectorImpl<MCFixup> &Fixups, 448 const MCSubtargetInfo &STI) const { 449 using namespace AMDGPU::SDWA; 450 451 uint64_t RegEnc = 0; 452 453 const MCOperand &MO = MI.getOperand(OpNo); 454 455 unsigned Reg = MO.getReg(); 456 if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) { 457 RegEnc |= MRI.getEncodingValue(Reg); 458 RegEnc &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 459 RegEnc |= SDWA9EncValues::VOPC_DST_VCC_MASK; 460 } 461 return RegEnc; 462 } 463 464 unsigned 465 SIMCCodeEmitter::getAVOperandEncoding(const MCInst &MI, unsigned OpNo, 466 SmallVectorImpl<MCFixup> &Fixups, 467 const MCSubtargetInfo &STI) const { 468 unsigned Reg = MI.getOperand(OpNo).getReg(); 469 uint64_t Enc = MRI.getEncodingValue(Reg); 470 471 // VGPR and AGPR have the same encoding, but SrcA and SrcB operands of mfma 472 // instructions use acc[0:1] modifier bits to distinguish. These bits are 473 // encoded as a virtual 9th bit of the register for these operands. 474 if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) || 475 MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) || 476 MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) || 477 MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) || 478 MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) || 479 MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) || 480 MRI.getRegClass(AMDGPU::AReg_224RegClassID).contains(Reg) || 481 MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) || 482 MRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg)) 483 Enc |= 512; 484 485 return Enc; 486 } 487 488 static bool needsPCRel(const MCExpr *Expr) { 489 switch (Expr->getKind()) { 490 case MCExpr::SymbolRef: { 491 auto *SE = cast<MCSymbolRefExpr>(Expr); 492 MCSymbolRefExpr::VariantKind Kind = SE->getKind(); 493 return Kind != MCSymbolRefExpr::VK_AMDGPU_ABS32_LO && 494 Kind != MCSymbolRefExpr::VK_AMDGPU_ABS32_HI; 495 } 496 case MCExpr::Binary: { 497 auto *BE = cast<MCBinaryExpr>(Expr); 498 if (BE->getOpcode() == MCBinaryExpr::Sub) 499 return false; 500 return needsPCRel(BE->getLHS()) || needsPCRel(BE->getRHS()); 501 } 502 case MCExpr::Unary: 503 return needsPCRel(cast<MCUnaryExpr>(Expr)->getSubExpr()); 504 case MCExpr::Target: 505 case MCExpr::Constant: 506 return false; 507 } 508 llvm_unreachable("invalid kind"); 509 } 510 511 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, 512 const MCOperand &MO, 513 SmallVectorImpl<MCFixup> &Fixups, 514 const MCSubtargetInfo &STI) const { 515 if (MO.isReg()) 516 return MRI.getEncodingValue(MO.getReg()); 517 518 if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) { 519 // FIXME: If this is expression is PCRel or not should not depend on what 520 // the expression looks like. Given that this is just a general expression, 521 // it should probably be FK_Data_4 and whatever is producing 522 // 523 // s_add_u32 s2, s2, (extern_const_addrspace+16 524 // 525 // And expecting a PCRel should instead produce 526 // 527 // .Ltmp1: 528 // s_add_u32 s2, s2, (extern_const_addrspace+16)-.Ltmp1 529 MCFixupKind Kind; 530 if (needsPCRel(MO.getExpr())) 531 Kind = FK_PCRel_4; 532 else 533 Kind = FK_Data_4; 534 535 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 536 uint32_t Offset = Desc.getSize(); 537 assert(Offset == 4 || Offset == 8); 538 539 Fixups.push_back( 540 MCFixup::create(Offset, MO.getExpr(), Kind, MI.getLoc())); 541 } 542 543 // Figure out the operand number, needed for isSrcOperand check 544 unsigned OpNo = 0; 545 for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) { 546 if (&MO == &MI.getOperand(OpNo)) 547 break; 548 } 549 550 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 551 if (AMDGPU::isSISrcOperand(Desc, OpNo)) { 552 uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI); 553 if (Enc != ~0U) 554 return Enc; 555 556 } else if (MO.isImm()) 557 return MO.getImm(); 558 559 llvm_unreachable("Encoding of this operand type is not supported yet."); 560 return 0; 561 } 562 563 #define ENABLE_INSTR_PREDICATE_VERIFIER 564 #include "AMDGPUGenMCCodeEmitter.inc" 565