1 //===-- SIMCCodeEmitter.cpp - SI Code Emitter -------------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The SI code emitter produces machine code that can be executed
12 /// directly on the GPU device.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPU.h"
17 #include "MCTargetDesc/AMDGPUFixupKinds.h"
18 #include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
19 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
20 #include "SIDefines.h"
21 #include "Utils/AMDGPUBaseInfo.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCFixup.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/raw_ostream.h"
31 
32 using namespace llvm;
33 
34 namespace {
35 
36 class SIMCCodeEmitter : public  AMDGPUMCCodeEmitter {
37   SIMCCodeEmitter(const SIMCCodeEmitter &) = delete;
38   void operator=(const SIMCCodeEmitter &) = delete;
39   const MCInstrInfo &MCII;
40   const MCRegisterInfo &MRI;
41 
42   /// \brief Encode an fp or int literal
43   uint32_t getLitEncoding(const MCOperand &MO, unsigned OpSize,
44                           const MCSubtargetInfo &STI) const;
45 
46 public:
47   SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
48                   MCContext &ctx)
49     : MCII(mcii), MRI(mri) { }
50 
51   ~SIMCCodeEmitter() override {}
52 
53   /// \brief Encode the instruction and write it to the OS.
54   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
55                          SmallVectorImpl<MCFixup> &Fixups,
56                          const MCSubtargetInfo &STI) const override;
57 
58   /// \returns the encoding for an MCOperand.
59   uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
60                              SmallVectorImpl<MCFixup> &Fixups,
61                              const MCSubtargetInfo &STI) const override;
62 
63   /// \brief Use a fixup to encode the simm16 field for SOPP branch
64   ///        instructions.
65   unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
66                              SmallVectorImpl<MCFixup> &Fixups,
67                              const MCSubtargetInfo &STI) const override;
68 };
69 
70 } // End anonymous namespace
71 
72 MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
73                                            const MCRegisterInfo &MRI,
74                                            MCContext &Ctx) {
75   return new SIMCCodeEmitter(MCII, MRI, Ctx);
76 }
77 
78 // Returns the encoding value to use if the given integer is an integer inline
79 // immediate value, or 0 if it is not.
80 template <typename IntTy>
81 static uint32_t getIntInlineImmEncoding(IntTy Imm) {
82   if (Imm >= 0 && Imm <= 64)
83     return 128 + Imm;
84 
85   if (Imm >= -16 && Imm <= -1)
86     return 192 + std::abs(Imm);
87 
88   return 0;
89 }
90 
91 static uint32_t getLit32Encoding(uint32_t Val, const MCSubtargetInfo &STI) {
92   uint32_t IntImm = getIntInlineImmEncoding(static_cast<int32_t>(Val));
93   if (IntImm != 0)
94     return IntImm;
95 
96   if (Val == FloatToBits(0.5f))
97     return 240;
98 
99   if (Val == FloatToBits(-0.5f))
100     return 241;
101 
102   if (Val == FloatToBits(1.0f))
103     return 242;
104 
105   if (Val == FloatToBits(-1.0f))
106     return 243;
107 
108   if (Val == FloatToBits(2.0f))
109     return 244;
110 
111   if (Val == FloatToBits(-2.0f))
112     return 245;
113 
114   if (Val == FloatToBits(4.0f))
115     return 246;
116 
117   if (Val == FloatToBits(-4.0f))
118     return 247;
119 
120   if (AMDGPU::isVI(STI) && Val == 0x3e22f983) // 1/(2*pi)
121     return 248;
122 
123   return 255;
124 }
125 
126 static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) {
127   uint32_t IntImm = getIntInlineImmEncoding(static_cast<int64_t>(Val));
128   if (IntImm != 0)
129     return IntImm;
130 
131   if (Val == DoubleToBits(0.5))
132     return 240;
133 
134   if (Val == DoubleToBits(-0.5))
135     return 241;
136 
137   if (Val == DoubleToBits(1.0))
138     return 242;
139 
140   if (Val == DoubleToBits(-1.0))
141     return 243;
142 
143   if (Val == DoubleToBits(2.0))
144     return 244;
145 
146   if (Val == DoubleToBits(-2.0))
147     return 245;
148 
149   if (Val == DoubleToBits(4.0))
150     return 246;
151 
152   if (Val == DoubleToBits(-4.0))
153     return 247;
154 
155   if (AMDGPU::isVI(STI) && Val == 0x3fc45f306dc9c882) // 1/(2*pi)
156     return 248;
157 
158   return 255;
159 }
160 
161 uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
162                                          unsigned OpSize,
163                                          const MCSubtargetInfo &STI) const {
164 
165   int64_t Imm;
166   if (MO.isExpr()) {
167     const MCConstantExpr *C = dyn_cast<MCConstantExpr>(MO.getExpr());
168     if (!C)
169       return 255;
170 
171     Imm = C->getValue();
172   } else {
173 
174     assert(!MO.isFPImm());
175 
176     if (!MO.isImm())
177       return ~0;
178 
179     Imm = MO.getImm();
180   }
181 
182   if (OpSize == 4)
183     return getLit32Encoding(static_cast<uint32_t>(Imm), STI);
184 
185   assert(OpSize == 8);
186 
187   return getLit64Encoding(static_cast<uint64_t>(Imm), STI);
188 }
189 
190 void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
191                                        SmallVectorImpl<MCFixup> &Fixups,
192                                        const MCSubtargetInfo &STI) const {
193 
194   uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
195   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
196   unsigned bytes = Desc.getSize();
197 
198   for (unsigned i = 0; i < bytes; i++) {
199     OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
200   }
201 
202   if (bytes > 4)
203     return;
204 
205   // Check for additional literals in SRC0/1/2 (Op 1/2/3)
206   for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {
207 
208     // Check if this operand should be encoded as [SV]Src
209     if (!AMDGPU::isSISrcOperand(Desc, i))
210       continue;
211 
212     int RCID = Desc.OpInfo[i].RegClass;
213     const MCRegisterClass &RC = MRI.getRegClass(RCID);
214 
215     // Is this operand a literal immediate?
216     const MCOperand &Op = MI.getOperand(i);
217     if (getLitEncoding(Op, RC.getSize(), STI) != 255)
218       continue;
219 
220     // Yes! Encode it
221     int64_t Imm = 0;
222 
223     if (Op.isImm())
224       Imm = Op.getImm();
225     else if (Op.isExpr()) {
226       if (const MCConstantExpr *C = dyn_cast<MCConstantExpr>(Op.getExpr()))
227         Imm = C->getValue();
228 
229     } else if (!Op.isExpr()) // Exprs will be replaced with a fixup value.
230       llvm_unreachable("Must be immediate or expr");
231 
232     for (unsigned j = 0; j < 4; j++) {
233       OS.write((uint8_t) ((Imm >> (8 * j)) & 0xff));
234     }
235 
236     // Only one literal value allowed
237     break;
238   }
239 }
240 
241 unsigned SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
242                                             SmallVectorImpl<MCFixup> &Fixups,
243                                             const MCSubtargetInfo &STI) const {
244   const MCOperand &MO = MI.getOperand(OpNo);
245 
246   if (MO.isExpr()) {
247     const MCExpr *Expr = MO.getExpr();
248     MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br;
249     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
250     return 0;
251   }
252 
253   return getMachineOpValue(MI, MO, Fixups, STI);
254 }
255 
256 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
257                                             const MCOperand &MO,
258                                        SmallVectorImpl<MCFixup> &Fixups,
259                                        const MCSubtargetInfo &STI) const {
260   if (MO.isReg())
261     return MRI.getEncodingValue(MO.getReg());
262 
263   if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) {
264     const MCSymbolRefExpr *Expr = dyn_cast<MCSymbolRefExpr>(MO.getExpr());
265     MCFixupKind Kind;
266     if (Expr && Expr->getSymbol().isExternal())
267       Kind = FK_Data_4;
268     else
269       Kind = FK_PCRel_4;
270     Fixups.push_back(MCFixup::create(4, MO.getExpr(), Kind, MI.getLoc()));
271   }
272 
273   // Figure out the operand number, needed for isSrcOperand check
274   unsigned OpNo = 0;
275   for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) {
276     if (&MO == &MI.getOperand(OpNo))
277       break;
278   }
279 
280   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
281   if (AMDGPU::isSISrcOperand(Desc, OpNo)) {
282     uint32_t Enc = getLitEncoding(MO,
283                                   AMDGPU::getRegOperandSize(&MRI, Desc, OpNo),
284                                   STI);
285     if (Enc != ~0U && (Enc != 255 || Desc.getSize() == 4))
286       return Enc;
287 
288   } else if (MO.isImm())
289     return MO.getImm();
290 
291   llvm_unreachable("Encoding of this operand type is not supported yet.");
292   return 0;
293 }
294 
295